Abstract: Systems, methods, and computer-readable media for improving user navigation of a multi-page article on a small screen user device. In embodiments, as a user progresses through the multi-page article, pages and/or lines of text of the multi-page article are cached. In response to a user request to view the multi-page article in a full-page format, the cached content is compared against text of the full-page document and used to determine a presentation of the text that displays nonduplicative content to the user.

Abstract: A storage controller that includes a cache, receives a command from a host, wherein a set of criteria corresponding to read response times for executing the command have to be satisfied. A destage application that destages tracks based at least on recency of usage and spatial location of the tracks is executed, wherein a spatial ordering of the tracks is maintained in a data structure, and the destage application traverses the spatial ordering of the tracks. Tracks are destaged from at least inside or outside diameters of disks at periodic intervals, while traversing the spatial ordering of the tracks, wherein the set of criteria corresponding to the read response times for executing the command are satisfied.

Abstract: Embodiments of the present invention provide a method and an apparatus for constructing a memory access model, and relate to the field of computers. The method includes: obtaining a page table corresponding to a process referencing a memory block, and clearing a Present bit included in each page table entry stored in the page table; and constructing a memory access model of the memory block according to the number of access times of each page in the memory block and time obtained through timing, where the memory access model at least includes the number of access times and an access frequency of each page in the memory block. The apparatus includes: a first obtaining module, a first monitoring module, a first increasing module, and a second obtaining module. The present invention can reduce the memory consumption and an impact on the system performance, and avoid a system breakdown.

Abstract: Methods and systems to intelligently cache content in a virtualization environment using virtualization software such as VMWare ESX or Citrix XenServer or Microsoft HyperV or Redhat KVM or their variants are disclosed. Storage IO operations (reads from and writes to disk) are analyzed (or characterized) for their overall value and pinned to cache if their value exceeds a certain defined threshold based on criteria specific to the New Technology File System (NTFS) file-system. Analysis/characterization of NTFS file systems for intelligent dynamic caching include analyzing storage block data associated with a Virtual Machine of interest in accordance with a pre-determined data model to determine the value of the block under analysis for long term or short term caching. Integer values assigned to different types of NTFS objects in a white list data structure called a catalog that can be used to analyze the storage block data.

Abstract: Efficient techniques are described for extending the usable lifetime for memories with limited write endurance. A technique for wear-leveling of caches addresses unbalanced write traffic on cache lines which cause heavily written cache lines to fail much fast than other lines in the cache. A counter is incremented for each write operation to a cache array. A line affected by a current write operation which caused the counter to meet a threshold is evicted from the cache rather than writing data to the affected line. A dynamic adjustment of the threshold can be made depending on the operating program. Updates to a current replacement policy pointer are stopped due to the counter meeting the threshold.

Abstract: Methods and systems to intelligently cache content in a virtualization environment using virtualization software such as VMWare ESX or Citrix XenServer or Microsoft HyperV or Redhat KVM or their variants are disclosed. Storage IO operations (reads from and writes to disk) are analyzed (or characterized) for their overall value and pinned to cache if their value exceeds a certain defined threshold based on criteria specific to the New Technology File System (NTFS) file-system. Analysis/characterization of NTFS file systems for intelligent dynamic caching include analyzing storage block data associated with a Virtual Machine of interest in accordance with a pre-determined data model to determine the value of the block under analysis for long term or short term caching. Integer values assigned to different types of NTFS objects in a white list data structure called a catalog that can be used to analyze the storage block data.

Abstract: A social data aggregator generates entries of action data describing actions taken by users. A portion of the entries are stored in an action cache to expedite retrieval. To store more recent or relevant entries in the action cache, entries are removed from the action cache based on engagement scores associated with the entries. An engagement score indicates a likelihood of a user requesting content interacting with a notification based on an entry. Entries having the lowest engagement scores or having engagement scores below a threshold are removed from the action cache.

Abstract: Technologies are described herein generally relate to aggregation of cache eviction notifications to a directory. Some example technologies may be utilized to update an aggregation table to reflect evictions of a plurality of blocks from a plurality of block addresses of at least one cache memory. An aggregate message can be generated, where the message specifies the evictions of the plurality of blocks as reflected in the aggregation table. The aggregate message can be sent to the directory. The directory can parse the aggregate message and update a plurality of directory entries to reflect the evictions from the cache memory as specified in the aggregate message.

Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for cutting senior store latency using store prefetching. For example, in one embodiment, such means may include an integrated circuit or an out of order processor means that processes out of order instructions and enforces in-order requirements for a cache. Such an integrated circuit or out of order processor means further includes means for receiving a store instruction; means for performing address generation and translation for the store instruction to calculate a physical address of the memory to be accessed by the store instruction; and means for executing a pre-fetch for a cache line based on the store instruction and the calculated physical address before the store instruction retires.

Abstract: Technologies generally described herein relate to cache directories in multi-core processors. Various examples may include, methods, systems, and devices. A first tile may receive a request to transfer a thread from the first tile to a second tile. An instruction may be sent from the first tile to map a virtual cache identifier to identifiers of caches of the first and second tiles. The thread may be transferred from the first tile to the second tile. Thereafter, a request may be generated for a data block. After a determination that the data block is not stored in the second tile's cache, and that the virtual cache identifier is mapped to the first and second cache identifiers, a request may be sent for the data block to the first tile.

Abstract: A cache memory system using temporal locality information and a data storage method are provided. The cache memory system including: a main cache which stores data accessed by a central processing unit; an extended cache which stores the data if the data is evicted from the main cache; and a separation cache which stores the data of the extended cache when the data of the extended cache is evicted from the extended cache and temporal locality information corresponding to the data of the extended cache satisfies a predetermined condition.

Abstract: A controller receives a request to perform staging or destaging operations with respect to an area of a cache. A determination is made as to whether more than a threshold number of discard scans are waiting to be performed. The controller avoids satisfying the request to perform the staging or the destaging operations or a read hit with respect to the area of the cache, in response to determining that more than the threshold number of discard scans are waiting to be performed.

Abstract: The exemplary embodiments described herein relate to systems and methods for improved process switching of a paravirtualized guest with a software-based memory management unit (“MMU”). One embodiment relates to a non-transitory computer readable storage medium including a set of instructions executable by a processor, the set of instructions, when executed, resulting in a performance of the following: create a plurality of new processes for each of a plurality of virtual environments, each of the virtual environments assigned one of a plurality of address space identifiers (“ASIDs”) stored in a cache memory, perform a process switch to one of the virtual environments thereby designating the one of the virtual environments as the active virtual environment, determine whether the active virtual environment has exhausted each of the ASIDs, and flush a cache memory when it is determined that the active virtual environment has exhausted each of the ASIDs.

Abstract: According to some embodiments, a method and apparatus are provided to receive, at a cache entity, a refresh request associated with a resource. A determination is made, via a processor, and based on the refresh request, to reload the resource from a server. The reloaded resource is replaced at the cache entity.

Abstract: Systems, methods, and computer-program products store file segments by receiving a first file segment, and storing the first file segment in a first memory area having a highest ranking. The first memory area is reassigned as a memory area having a next highest ranking when a second file segment is received and the first memory area has reached a maximum capacity. The second file segment is stored in another memory that is reassigned as the memory area having the highest ranking.

Abstract: A computer implemented method creates a snapshot of a logical volume of a computer. The computer stores a system state of the computer in persistent memory. The computer flushes a cash of the computer. The computer identifies a preceding snapshot. Responsive to identifying the preceding snapshot, the computer hardens changes occurring after the preceding snapshot. The computer then switches from a first indirection table to a second indirection table.

Abstract: A first nonvolatile storage device has a higher access speed in a continuous access than a random access and a second nonvolatile storage device has a higher access speed in the random access than the continuous access. The information processing apparatus selects a first storage method in which an amount of continuous data is larger than an amount of random data if data stored in a volatile storage device is saved in the first nonvolatile storage device, and selects a second storage method in which an amount of random data is larger than an amount of continuous data if the data stored in the volatile storage device is saved in the second nonvolatile storage device, and saves the data stored in the volatile storage device into the specified nonvolatile storage device using the selected storage method when a predetermined condition is satisfied.

Abstract: Embodiments of an invention for measuring applications loaded in secure enclaves at runtime are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit. The instruction unit is to receive an instruction to extend a first measurement of a secure enclave with a second measurement. The execution unit is to execute the instruction after initialization of the secure enclave.

Abstract: A virtually tagged cache may be configured to index virtual address entries in the cache into lockable sets based on a page offset value. When a memory operation misses on the virtually tagged cache, only the one set of virtual address entries with the same page offset may be locked. Thereafter, this general lock may be released and only an address stored in the physical tag array matching the physical address and a virtual address in the virtual tag array corresponding to the matching address stored in the physical tag array may be locked to reduce the amount and duration of locked addresses. The machine may be stalled only if a particular memory address request hits and/or tries to access one or more entries in a locked set. Devices, systems, methods, and computer readable media are provided.

Abstract: A method and apparatus for providing a memory model for hardware attributes to support transactional execution is herein described. Upon encountering a load of a hardware attribute, such as a test monitor operation to load a read monitor, write monitor, or buffering attribute, a fault is issued in response to a loss field indicating the hardware attribute has been lost. Furthermore, dependency actions, such as blocking and forwarding, are provided for the attribute access operations based on address dependency and access type dependency. As a result, different scenarios for attribute loss and testing thereof are allowed and restricted in a memory model.

Abstract: A processor includes a processor core including an execution unit to execute instructions, and a cache memory. The cache memory includes a controller to update each of a plurality of stale indicators in response to a lazy flush instruction. Each stale indicator is associated with respective data, and each updated stale indicator is to indicate that the respective data is stale. The cache memory also includes a plurality of cache lines. Each cache line is to store corresponding data and a foreground tag that includes a respective virtual address associated with the corresponding data, and that includes the associated stale indicator. Other embodiments are described as claimed.

Abstract: A network storage server includes a main buffer cache to buffer writes requested by clients before committing them to primary persistent storage. The server further uses a secondary cache, implemented as low-cost, solid-state memory, such as flash memory, to store data evicted from the main buffer cache or data read from the primary persistent storage. To prevent bursts of writes to the secondary cache, data is copied from the main buffer cache to the secondary cache speculatively, before there is a need to evict data from the main buffer cache. Data can be copied to the secondary cache as soon as the data is marked as clean in the main buffer cache. Data can be written to secondary cache at a substantially constant rate, which can be at or close to the maximum write rate of the secondary cache.

Abstract: A system and method are presented. Some embodiments include a processing unit, at least one memory coupled to the processing unit, and at least one cache coupled to the processing unit and divided into a series of blocks, wherein at least one of the series of cache blocks includes data identified as being in a modified state. The modified state data is flushed by writing the data to the at least one memory based on a write back policy and the aggressiveness of the policy is based on at least one factor including the number of idle cores, the proximity of the last cache flush, the activity of the thread associated with the data, and which cores are idle and if the idle core is associated with the data.

Abstract: Responsive to receiving a write request for a cache line from an input/output device, a caching agent of a first processor determines that the cache line is managed by a home agent of a second processor. The caching agent sends an ownership request for the cache line to the second processor. A home agent of the second processor receives the ownership request, generates an entry in a directory cache for the cache line, the entry identifying the remote caching agent as having ownership of the cache line, and grants ownership of the cache line to the remote caching agent. Responsive to receiving the grant of ownership for the cache line from the home agent an input/output controller of the first processor adds an entry for the cache line to an input/output write cache, the entry comprising a first indicator that the cache line is managed by the home agent of the second processor.

Abstract: A system and method for efficiently limiting storage space for data with particular properties in a cache memory. A computing system includes a cache array and a corresponding cache controller. The cache array includes multiple banks, wherein a first bank is powered down. In response a write request to a second bank for data indicated to be stored in the powered down first bank, the cache controller determines a respective bypass condition for the data. If the bypass condition exceeds a threshold, then the cache controller invalidates any copy of the data stored in the second bank. If the bypass condition does not exceed the threshold, then the cache controller stores the data with a clean state in the second bank. The cache controller writes the data in a lower-level memory for both cases.

Abstract: A data processing system includes a first master having a cache, a second master, a memory operably coupled to the first master and the second master via a system interconnect. The cache includes a cache controller which implements a set of cache coherency states for data units of the cache. The cache coherency states include an invalid state; an unmodified non-coherent state indicating that data in a data unit of the cache has not been modified and is not guaranteed to be coherent with data in at least one other storage device of the data processing system, and an unmodified coherent state indicating that the data of the data unit has not been modified and is coherent with data in the at least one other storage device of the data processing system.

Abstract: Embodiments include methods, systems, and articles of manufacture directed to identifying transient data upon storing the transient data in a cache memory, and invalidating the identified transient data in the cache memory.

Abstract: The present invention relates to a method of optimizing the provisioning of a bootable image onto a storage device. In some embodiments, a host device executes a provisioning application to image a storage drive as a bootable drive. During the provisioning process, the storage device is configured to disguise its use of write caching during the provisioning process. In one embodiment, the storage device is configured to suppress forced unit access commands and cache flush commands for the provisioning application. In another embodiment, the storage device is configured to reject forced unit access commands. The storage device may disguise its use of write caching based on various criteria, such as a length of time, a counter, and the like.

Abstract: A data processing system includes a cache memory 58 and cache control circuitry 56 for applying a cache replacement policy based upon a retention priority value PV stored with each cache line 66 within the cache memory 58. The initial retention priority value set upon inserting a cache line 66 into the cache memory 58 is dependent upon either or both of which of a plurality of sources issued the access memory request that resulted in the insertion or the privilege level of the memory access request resulting in the insertion. The initial retention priority level of cache lines resulting from instruction fetches may be set differently from cache lines resulting from data accesses.

Abstract: A method of operating a memory system is provided. The method includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or more FLASH devices. Wear leveling components along with read and write processing components are provided to facilitate efficient operations of the FLASH memory devices.

Abstract: Disclosed is a computer system (100) comprising a processor unit (110) adapted to run a virtual machine in a first operating mode; a cache (120) accessible to the processor unit, said cache comprising a plurality of cache rows (1210), each cache row comprising a cache line (1214) and an image modification flag (1217) indicating a modification of said cache line caused by the running of the virtual machine; and a memory (140) accessible to the cache controller for storing an image of said virtual machine; wherein the processor unit comprises a replication manager adapted to define a log (200) in the memory prior to running the virtual machine in said first operating mode; and said cache further includes a cache controller (122) adapted to periodically check said image modification flags; write only the memory address of the flagged cache lines in the defined log and subsequently clear the image modification flags.

Abstract: The present invention provides a method and apparatus for use with a hierarchical cache system. The method may include concurrently flushing one or more first caches and a second cache of a multi-level cache. Each first cache is smaller and at a lower level in the multi-level cache than the second level cache.

Abstract: A context of a mobile device is determined. A context preference of a user associated with the mobile device is determined. The context of the mobile device and the user context preference is transmitted to another node and responsively returned data is received. Available free space in the mobile device is determined. All data whose timestamp is within a predetermined threshold is cached. The data is cached in at least a portion of the free space.

Abstract: A deleted cache determining part determines a cache data which is to be deleted from a data storing part in a case where a sum of a data amount of a data which is recorded to the data storing part and a data amount of a cache data which is stored to the data storing part and a data amount of a buffer data which is stored to the storing part is equal to or more than a predetermined threshold, and an accumulated data control part deletes the cache data which is determined by the deleted cache determining part from the data storing part.

Abstract: An information processing apparatus includes a detection unit configured to detect a damaged file from files stored in a cache area, a determination unit configured to determine whether the damaged file detected by the detection unit is restorable, a restoration unit configured to, if the determination unit determines that the damaged file is restorable, delete every restorable file in the cache area including the damaged file and restore the deleted file in the cache area, and an initialization unit configured to, if the determination unit determines that the damaged file is not restorable, delete every file in the cache area and initialize the cache area.

Abstract: A processor with coherency-leveraged support for low latency message signaled interrupt handling includes multiple execution cores and their associated cache memories. A first cache memory associated a first of the execution cores includes a plurality of cache lines. The first cache memory has a cache controller including hardware logic, microcode, or both to identify a first cache line as an interrupt reserved cache line and map the first cache line to a selected memory address associated with an I/O device. The selected system address may be a portion of configuration data in persistent storage accessible to the processor. The controller may set a coherency state of the first cache line to shared and, in response to detecting an I/O transaction including I/O data from the I/O device and containing a reference to the selected memory address, emulate a first message signaled interrupt identifying the selected memory address.

Abstract: Reducing contentions between processes or tasks that are trying to access shared resources is described herein. According to embodiments of the invention, a method of writing a set of data associated with a task to a memory resource is provided. The method includes calculating the amount of memory required to write said data to the memory resource and updating an expected end marker to reflect the amount of memory required to write the data to the memory resource. A flag is then set to an incomplete state, and the data is written to the memory resource. The flag can be set to a complete state and an end marker is updated. The end marker indicates the end of the data stored in the memory resource.

Abstract: A storage system comprises a cache for caching data blocks and storage devices for storing blocks. A storage operating system may deduplicate sets of redundant blocks on the storage devices based on a deduplication requirement. Blocks in cache are typically deduplicated based on the deduplication on the storage devices. Sets of redundant blocks that have not met the deduplication requirement for storage devices and have not been deduplicated on the storage devices and cache are targeted for further deduplication processing. Sets of redundant blocks may be further deduplicated based on their popularity (number of accesses) in cache. If a set of redundant blocks in cache is determined to have a combined number of accesses being greater than a predetermined threshold number of accesses, the set of redundant blocks is determined to be “popular.” Popular sets of redundant blocks are selected for deduplication in cache and the storage devices.

Abstract: A system and method are described for dynamically changing the size of a computer memory such as level 2 cache as used in a graphics processing unit. In an embodiment, a relatively large cache memory can be implemented in a computing system so as to meet the needs of memory intensive applications. But where cache utilization is reduced, the capacity of the cache can be reduced. In this way, power consumption is reduced by powering down a portion of the cache.

Abstract: Systems and methods for predictive cache replacement policies are provided. In particular, some embodiments dynamically capture and predict access patterns of data to determine which data should be evicted from the cache. A novel tree data structure can be dynamically built that allows for immediate use in the identification of developing patterns and the eviction determination. In some cases, the data can be dynamically organized into histograms, strings, and other representations allowing traditional analysis techniques to be applied. Data organized into histogram-like structures can also be converted into strings allowing for well-known string pattern recognition analysis. The pattern recognition and prediction techniques disclosed also have applications outside of caching.

Abstract: A method for managing keys in a computer memory including receiving a request to store a first key to a first key repository, storing the first key to a second key repository in response to the request, and storing the first key from the second key repository to the first key repository within said computer memory based on a predetermined periodicity.

Abstract: A computer-implemented method in a distributed network system is disclosed. The computer-implemented method includes: receiving, at a server, a first object update message from a server-side application, wherein the first object update message includes a first object identifier; identifying, among a plurality of object-client registration records, an object-client registration record that includes the first object identifier; updating the object-client registration record in accordance with the first object update message; selecting a set of client identifiers associated with the first object identifier from the object-client registration record; and, for a first client identifier in the selected set of client identifiers, sending a second object update message to a first client device associated with the first client identifier, wherein the second object update message includes the first object identifier.

Abstract: An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first number based on processor clock cycles per instruction (CPI) associated with a second core is higher than a first threshold. The controller is operable to increase the operating point of the first core if the first number is lower than a second threshold.

Abstract: A method, computer program product, and cache management system for receiving an indication of a data portion update within an electromechanical storage system. Information concerning the data portion update is provided to at least one proprietary, solid-state, non-volatile, cache memory system. The proprietary, solid-state, non-volatile, cache memory system is associated with at least a first of a plurality of computing devices and is not associated with at least a second of the plurality of computing devices.

Abstract: A processor (600) in a distributed shared memory multi-processor computer system (10) may initiate a flush request to remove data from its cache. A processor interface (24) receives the flush request and performs a snoop operation to determine whether the data is maintained in a one of the local processors (601) and whether the data has been modified. If the data is maintained locally and it has been modified, the processor interface (24) initiates removal of the data from the cache of the identified processor (601). The identified processor (601) initiates a writeback to a memory directory interface unit (24) associated with a home memory 17 for the data in order to preserve the modification to the data. If the data is not maintained locally or has not been modified, the processor interface (24) forwards the flush request to the memory directory interface unit (22).

Abstract: Systems and methods for non-blocking implementation of cache flush instructions are disclosed. As a part of a method, data is accessed that is received in a write-back data holding buffer from a cache flushing operation, the data is flagged with a processor identifier and a serialization flag, and responsive to the flagging, the cache is notified that the cache flush is completed. Subsequent to the notifying, access is provided to data then present in the write-back data holding buffer to determine if data then present in the write-back data holding buffer is flagged.

Abstract: A portion of a nonvolatile memory is partitioned from a main multi-level memory array to operate as a cache. The cache memory is configured to store at less capacity per memory cell and finer granularity of write units compared to the main memory. In a block-oriented memory architecture, the cache has multiple functions, not merely to improve access speed, but is an integral part of a sequential update block system. Decisions to archive data from the cache memory to the main memory depend on the attributes of the data to be archived, the state of the blocks in the main memory portion and the state of the blocks in the cache portion.

Abstract: A method and system to allow power fail-safe write-back or write-through caching of data in a persistent storage device into one or more cache lines of a caching device. No metadata associated with any of the cache lines is written atomically into the caching device when the data in the storage device is cached. As such, specialized cache hardware to allow atomic writing of metadata during the caching of data is not required.

Abstract: A method and system for precisely tracking lines evicted from a region coherence array (RCA) without requiring eviction of the lines from a processor's cache hierarchy. The RCA is a set-associative array which contains region entries consisting of a region address tag, a set of bits for the region coherence state, and a line-count for tracking the number of region lines cached by the processor. Tracking of the RCA is facilitated by a non-tagged hash table of counts represented by a Region Victim Hash (RVH). When a region is evicted from the RCA, and lines from the evicted region still reside in the processor's caches (i.e., the region's line-count is non-zero), the RCA line-count is added to the corresponding RVH count. The RVH count is decremented by the value of the region line count following a subsequent processor cache eviction/invalidation of the region previously evicted from the RCA.

Abstract: An invention that expires cached virtual content in a virtual universe is provided. In one embodiment, there is an expiration tool, including an identification component configured to identify virtual content associated with an avatar in the virtual universe; an analysis component configured to analyze a behavior of the avatar in a region of the virtual universe; and an expiration component configured to expire cached virtual content associated with the avatar based on the behavior of the avatar in the region of the virtual universe.