Abstract: A memory system includes: a first cache; a second cache; and a control unit configured to access the first cache as a first level cache in a first cache mode of operation of the memory system and access the second cache as the first level cache in a second cache mode of operation of the memory system.

Abstract: A device may be run in a timing testing mode in which the device is configured to disrupt timing of processing that takes place on the one or more processors while running an application with the one or more processors. The application may be tested for errors while the device is running in the timing testing mode.

Abstract: A processing arrangement having a first processing component and a second processing component is provided. The first component has a first output memory and a second output memory and a control device using the first memory storing a value to be output and the second memory stores a value that is based according to a prescribed function on the value. The control device stores a new value in the first memory whenever the second component has read a value stored in the first memory. The second component has a reading device reading the values stored in the first and second memories, and a processing device that checks whether the value read from the second memory is based according to the prescribed function on the value read from the first memory and, depending on the result, to process the value read from the first memory.

Abstract: Described herein are systems and methods to prevent a controller in a DDIO (data direct input output) system from shifting currently-required data out of a cache memory. In one embodiment, a compute element disables caching of some specific addresses in a non-cache memory, but still enables caching of other addresses in the non-cache memory, thereby practically disabling the DDIO system, so that data sets not currently needed are placed in the addresses in the non-cache memory which are not cached. As a result, currently-required data are not shifted out of cache memory. The compute element then determines that the data sets, which formerly avoided being cached, are now required. The system therefore copies the data sets that are now required from addresses in non-cache memory not accessible to cache memory, to addresses in non-cache memory accessible to cache memory, thereby allowing the caching and processing of such data sets.

Abstract: Systems, methods, and computer readable media for accessing and compressing data at a virtually provisioned storage entity are disclosed. According to one aspect, a method includes receiving, at a data storage entity, an input/output (I/O) command to perform an operation on data associated with a logical block address (LBA) in a virtually provisioned device in the data storage entity, wherein the data storage entity has established an expanded private LBA space for the virtually provisioned device in the data storage entity to include both a compressed LBA space portion for storing compressed data and an associated uncompressed LBA space portion for storing uncompressed data. The method further includes determining if a data chunk containing the data in the uncompressed LBA space is available using the LBA in the I/O command to access the data chunk. If the data chunk in the uncompressed LBA space is available, the method includes performing the operation on the data chunk.

Abstract: In one embodiment, a processor comprises a plurality of hardware resources, each hardware resource having a clock cycle. The processor also comprises a plurality of work stores, each work store assigned into one of a plurality of virtual functions if a mode of the processor is set to a virtual function mode, and each work store assigned into one physical function if the mode of the processor is set to a physical function mode. The processor further comprises dispatch logic configured to dispatch work from any work store corresponding to any virtual function or physical function to any released hardware resources.

Abstract: The present disclosure relates to techniques for system and methods for software-based management of protected data-blocks insertion into the memory cache mechanism of a computerized device. In particular the disclosure relates to preventing protected data blocks from being altered and evicted from the CPU cache coupled with buffered software execution. The technique is based upon identifying at least one conflicting data-block having a memory mapping indication to a designated memory cache-line and preventing the conflicting data-block from being cached. Functional characteristics of the software product of a vendor, such as gaming or video, may be partially encrypted to allow for protected and functional operability and avoid hacking and malicious usage of non-licensed user.

Abstract: In a disc device according to the present invention, when a controller 2 abandons a block from a cache memory 4 used as a primary cache, it is determined whether or not the number of readings of data in the block exceeds the specified number of times. Only when the number of readings exceeds the specified number of times, the block is written into an SSD 8 used as a secondary cache. When the number of readings is equal to or smaller than the specified number of times, the block is rewritten into an HDD 7.

Abstract: A computer system that supports virtualization may maintain multiple address spaces. Each guest operating system employs guest virtual addresses (GVAs), which are translated to guest physical addresses (GPAs). A hypervisor, which manages one or more guest operating systems, translates GPAs to root physical addresses (RPAs). A merged translation lookaside buffer (MTLB) caches translations between the multiple addressing domains, enabling faster address translation and memory access. The MTLB can be logically addressable as multiple different caches, and can be reconfigured to allot different spaces to each logical cache. Lookups to the caches of the MTLB can be selectively bypassed based on a control configuration and the attributes of a received address.

Abstract: In one embodiment, a memory that is delineated into transparent and non-transparent portions. The transparent portion may be controlled by a control unit coupled to the memory, along with a corresponding tag memory. The non-transparent portion may be software controlled by directly accessing the non-transparent portion via an input address. In an embodiment, the memory may include a decoder configured to decode the address and select a location in either the transparent or non-transparent portion. Each request may include a non-transparent attribute identifying the request as either transparent or non-transparent. In an embodiment, the size of the transparent portion may be programmable. Based on the non-transparent attribute indicating transparent, the decoder may selectively mask bits of the address based on the size to ensure that the decoder only selects a location in the transparent portion.

Abstract: A scatter/gather technique optimizes unstructured streaming memory accesses, providing off-chip bandwidth efficiency by accessing only useful data at a fine granularity, and off-loading memory access overhead by supporting address calculation, data shuffling, and format conversion.

Abstract: Embodiments of the present disclosure provide a system on a chip (SOC) comprising a processing core including a core bus agent, a bus interface unit (BIU), and a bridge module operatively coupling the processing core to the BIU, the bridge module configured to selectively route information from the core bus agent to a cache or to the BIU by bypassing the cache. Other embodiments are also described and claimed.

Abstract: A data processing system includes a system memory and a cache hierarchy that caches contents of the system memory. According to one method of data processing, a storage modifying operation having a cacheable target real memory address is received. A determination is made whether or not the storage modifying operation has an associated bypass indication. In response to determining that the storage modifying operation has an associated bypass indication, the cache hierarchy is bypassed, and an update indicated by the storage modifying operation is performed in the system memory. In response to determining that the storage modifying operation does not have an associated bypass indication, the update indicated by the storage modifying operation is performed in the cache hierarchy.

Abstract: A multi-core processing apparatus may provide a cache probe and data retrieval method. The method may comprise sending a memory request from a requester to a record keeping structure. The memory request may have a memory address of a memory that stores requested data. The method may further comprise determining a last accessor of the memory address, sending a cache probe to the last accessor, determining the last accessor no longer has a copy of the line; and sending a request for the previously accessed version of the line. The request may bypass the tag-directories and obtain the requested data from memory.

Abstract: A method for maintaining a cache of dynamically generated objects. The method includes storing in the cache dynamically generated objects previously served from an originating server to a client. A communication between the client and server is intercepted by the cache. The cache parses the communication to identify an object determinant and to determine whether the object determinant indicates whether a change has occurred or will occur in an object at the originating server. The cache marks the object stored in the cache as invalid if the object determinant so indicates. If the object has been marked as invalid, the cache retrieves the object from the originating server.

Abstract: A method to monitor the behavior of a working set cache of a full data set at run time and determine whether it provides a performance benefit is disclosed. An effectiveness metric of the working set cache is tracked over a period of time by efficiently computing the amount of physical memory consumption the cache saves and comparing this to a straightforward measure of its overhead. If the effectiveness metric is determined to be on an ineffective side of a selected threshold amount, the working set cache is disabled. The working set cache can be re-enabled in response to a predetermined event.

Abstract: Embodiments of the present disclosure provide a system on a chip (SOC) comprising a processing core including a core bus agent, a bus interface unit (BIU), and a bridge module operatively coupling the processing core to the BIU, the bridge module configured to selectively route information from the core bus agent to a cache or to the BIU by bypassing the cache. Other embodiments are also described and claimed.

Abstract: A scatter/gather technique optimizes unstructured streaming memory accesses, providing off-chip bandwidth efficiency by accessing only useful data at a fine granularity, and off-loading memory access overhead by supporting address calculation, data shuffling, and format conversion.

Abstract: A method includes determining if a data processing instruction is a decorated access instruction with cache bypass, and determining if the data processing instruction generates a cache hit to a cache. When the data processing instruction is determined to be a decorated access instruction with cache bypass and the data processing instruction is determined to generate a cache hit, the method further includes invalidating a cache entry of the cache associated with the cache hit; and performing by a memory controller of the memory, a decoration operation specified by the data processor instruction on a location in the memory designated by a target address of the data processor instruction, wherein the performing the decorated access includes the memory controller performing a read of a value of the location in memory, modifying the value to generate a modified value, and writing the modified value to the location.

Abstract: According to embodiments described in the specification, a method and apparatus for managing memory in a mobile electronic device are provided. The method comprises: receiving a request to install an application; receiving at least one indication of data intended to be maintained in a shared cache; determining, based on the at least one indication, whether data corresponding to the intended data exists in the shared cache; upon a negative determination, writing the intended data to the shared cache; and repeating the receiving at least one indication, the determining and the writing for at least one additional application.

Abstract: A host system includes an operating system having a user space and a kernel space with a memory. A device driver performs download cycles to download a firmware file from the user space to the memory. The download cycles are performed based on blocks of data remaining in the user space and not downloaded from the user space. The device driver: transfers a first block of data to a first segment of the memory; transfers a second block of data from the user space to a second segment of the memory; copies the first block into the second segment; and appends the first block to the second block to form a combined block. The first block is transferred from the user space to the first segment during a first download cycle. The first block is transferred from a second segment to the first segment during a second download cycle.

Abstract: In one embodiment, a memory that is delineated into transparent and non-transparent portions. The transparent portion may be controlled by a control unit coupled to the memory, along with a corresponding tag memory. The non-transparent portion may be software controlled by directly accessing the non-transparent portion via an input address. In an embodiment, the memory may include a decoder configured to decode the address and select a location in either the transparent or non-transparent portion. Each request may include a non-transparent attribute identifying the request as either transparent or non-transparent. In an embodiment, the size of the transparent portion may be programmable. Based on the non-transparent attribute indicating transparent, the decoder may selectively mask bits of the address based on the size to ensure that the decoder only selects a location in the transparent portion.

Abstract: In an embodiment, a non-transparent memory unit is provided which includes a non-transparent memory and a control circuit. The control circuit may manage the non-transparent memory as a set of non-transparent memory blocks. Software executing on one or more processors may request a non-transparent memory block in which to process data. The control circuit may allocate a first block, and may return an address (or other indication) of the allocated block so that the software can access the block. The control circuit may also provide automatic data movement between the non-transparent memory and a main memory system to which the non-transparent memory unit is coupled. For example, the automatic data movement may include filling data from the main memory system to the allocated block, or flushing the data in the allocated block to the main memory system after the processing of the allocated block is complete.

Abstract: Embodiments of the invention provide methods and apparatus for selectively bypassing cache levels when processing non-reusable transient data in a cache coherent system. To selectively bypass cache levels a page table entry (PTE) mechanism may be employed. To limit the number of PTE bits, the PTE may have a 2-bit “bypass type” field among other attribute bits that index which bits of a Special Purpose Register (SPR) identify the cache levels to be bypassed.

Abstract: A computing system includes: first and second I/O interfaces that are associated with a server; and an I/O management unit that connects the server with the first and second I/O interfaces. The I/O management unit includes: an I/O buffer; an I/O mapping unit that stores an access request of the server to the first I/O interface in the I/O buffer in response to a change start request of the first I/O interface associated with the server to the second I/O interface; an I/O changing unit that associates the second I/O interface with the server; and an I/O synchronizing unit that converts the access request stored in the I/O buffer into an access request to the second I/O interface, in response to the completion of the association by the I/O changing unit, and executes the converted access request.

Abstract: A scatter/gather technique optimizes unstructured streaming memory accesses, providing off-chip bandwidth efficiency by accessing only useful data at a fine granularity, and off-loading memory access overhead by supporting address calculation, data shuffling, and format conversion.

Abstract: The present invention is directed towards a “flash crowd” technique for handling situations where the cache receives additional requests, e.g.,. nearly simultaneous requests, for the same object during the time the server is processing and returning the response object for a first requester. Once all such nearly simultaneous requests are responded to by the cache, the object is flushed from the cache, with no additional expire time or invalidation action needed. This technique of the present invention enables data to be cached and served for very small amounts of time for objects that would otherwise be considered non-cacheable. As such, this technique yields a significant improvement in applications that serve fast changing data to a large volume of concurrent users, such, for example, as real time stock quotes, or a fast evolving news story.

Abstract: A computing system includes: first and second I/O interfaces that are associated with a server; and an I/O management unit that connects the server with the first and second I/O interfaces. The I/O management unit includes: an I/O buffer; an I/O mapping unit that stores an access request of the server to the first I/O interface in the I/O buffer in response to a change start request of the first I/O interface associated with the server to the second I/O interface; an I/O changing unit that associates the second I/O interface with the server; and an I/O synchronizing unit that converts the access request stored in the I/O buffer into an access request to the second I/O interface, in response to the completion of the association by the I/O changing unit, and executes the converted access request.

Abstract: The present invention is directed towards a method and system for modifying by a cache responses from a server that do not identify a dynamically generated object as cacheable to identify the dynamically generated object to a client as cacheable in the response. In some embodiments, such as an embodiment handling HTTP requests and responses for objects, the techniques of the present invention insert an entity tag, or “etag” into the response to provide cache control for objects provided without entity tags and/or cache control information from an originating server. This technique of the present invention provides an increase in cache hit rates by inserting information, such as entity tag and cache control information for an object, in a response to a client to enable the cache to check for a hit in a subsequent request.

Abstract: The present invention is directed towards a method and system for modifying by a cache responses from a server that do not identify a dynamically generated object as cacheable to identify the dynamically generated object to a client as cacheable in the response. In some embodiments, such as an embodiment handling HTTP requests and responses for objects, the techniques of the present invention insert an entity tag, or “etag” into the response to provide cache control for objects provided without entity tags and/or cache control information from an originating server. This technique of the present invention provides an increase in cache hit rates by inserting information, such as entity tag and cache control information for an object, in a response to a client to enable the cache to check for a hit in a subsequent request.

Abstract: Embodiments include retrieving data of a web page from a remote system in response to a request for the web page. It is determined that the web page is indicated in a data structure that indicates web pages not to be cached in a cache of a web browser on a data processing system. The data structure and the cache of the web browser are distinct from each other. The web page is presented with the web browser using the data retrieved from the remote system. The data of the web page is prevented from being cached in the cache of the web browser in accordance with said determining that the web page is indicated in the data structure that indicates web pages not to be cached in the cache of the web browser on the data processing system.

Abstract: Techniques are generally described for a multi-core processor with a plurality of processor cores. At least one cache is accessible to at least two of the plurality of processor cores. The multi-core processor can be configured for separately allocating a memory space within the cache to the individual processor cores accessing the cache.

Abstract: Some embodiments of the present invention provide a system that performs stores in a memory system. During operation, the system performs a store for a first thread, which involves creating an entry for the store in a store queue for the first thread. It also involves attempting to store-mark a corresponding cache line for the first thread by sending a store-mark request for the first thread to the memory system, wherein a store-mark on the cache line indicates that one or more store queue entries are waiting to be committed to the cache line. If the attempt to store-mark the cache line fails because a second thread holds a store-mark on the cache line, and if obtaining the store-mark will ensure forward progress for the first thread, the system forces the second thread to release the store-mark, so the first thread can acquire a store-mark for the cache line.

Abstract: A computer-implemented method, apparatus, and computer program product are disclosed for managing direct memory access (DMA) write page faults using a pool of substitute pages. A computer system platform resolves a DMA write page fault for a page that is dedicated to an Input/Output (I/O) adapter. The I/O adapter attempts to write DMA data to the page. A determination is made that the page is unavailable for writing. The DMA data is then written to data locations in a substitute page that was selected from the pool of substitute pages. A flag is then set in a flag location for each one of the data locations. The flag locations correspond to the data locations. When a flag is set, the flag indicates that DMA write data is present in the data location that corresponds to that flag's flag location.

Abstract: A data structure for enforcing consistent per-physical page cacheability attributes is disclosed. The data structure is used with a method for enforcing consistent per-physical page cacheability attributes, which maintains memory coherency within a processor addressing memory, such as by comparing a desired cacheability attribute of a physical page address in a PTE against an authoritative table that indicates the current cacheability status. This comparison can be made at the time the PTE is inserted into a TLB. When the comparison detects a mismatch between the desired cacheability attribute of the page and the page's current cacheability status, corrective action can be taken to transition the page into the desired cacheability state.

Abstract: A first storage system is connected to a second storage system, and an external device within the first storage system is provided to a host as a device of the second storage system. The second storage system includes a cache control section having cache adaptors, each controlling a disk and a cache, a protocol conversion section including protocol adaptors that switch requests from the host to appropriate ones of the cache adaptors, a management adaptor, and an internal network that mutually connects the cache adaptors, the protocol adaptors and the management adaptor. The first storage system being connected to any of the protocol adaptors is connected to the second storage system. The second storage system executes a processing for the external device by the cache control section, or connects to the first storage system through the protocol conversion section without the cache control section executing processing for the external device.

Abstract: A technique for partially offloading, from a main cache in a storage server, the storage of cache tags for data blocks in a victim cache of the storage server, is described. The technique includes storing, in the main cache, a first subset of the cache tag information for each of the data blocks, and storing, in a victim cache of the storage server, a second subset of the cache tag information for each of the data blocks. This technique avoids the need to store the second subset of the cache tag information in the main cache.

Abstract: Embodiments of the invention provide methods and apparatus for selectively bypassing cache levels when processing non-reusable transient data in a cache coherent system. To selectively bypass cache levels a page table entry (PTE) mechanism may be employed. To limit the number of PTE bits, the PTE may have a 2-bit “bypass type” field among other attribute bits that index which bits of a Special Purpose Register (SPR) identify the cache levels to be bypassed.

Abstract: The page table walker is moved from its conventional location in the memory management unit associated with the data processor to a location in main memory i.e. the main memory controller. As a result, an implementation is provided wherein the processing of requests for data could selectively avoid or bypass cumbersome caches associated with the data processor.

Abstract: Systems and methods are provided for a data processing system and a cache arrangement. The data processing system includes at least one processor, a first-level cache, a second-level cache, and a memory arrangement. The first-level cache bypasses storing data for a memory request when a do-not-cache attribute is associated with the memory request. The second-level cache stores the data for the memory request. The second-level cache also bypasses updating of least-recently-used indicators of the second-level cache when the do-not-cache attribute is associated with the memory request.

Abstract: Apparatus, methods, and program products for storing data address a first cache and a second cache. The second cache is capable of operating in a first mode wherein data read for storage in the first cache is also stored in the second cache, and is capable of operating in a second mode wherein the data stored in the second cache does not include at least some of the data read for storage in the first cache. The data stored in the second cache includes data that has been removed from the first cache. Thus the contents of the second cache are at least partially exclusive of the contents of the first cache. The described apparatus, methods, and program products are advantageously employed in multi-level caching systems wherein the caches may be approximately the same size.

Abstract: A processor comprises decode logic that determines an instruction type for each instruction fetched, a first level cache, a second level cache coupled to the first level cache, and control logic operatively coupled to the first and second level caches. The control logic preferably causes cache linefills to be performed to the first level cache upon cache misses for a first type of instruction, but precludes linefills from being performed to the first level cache for a second type of instruction.

Abstract: A cache memory device with a cache section, which is provided between a CPU and a main memory and operates as a fast buffer memory, has a capability of storing input data in the cache section when attribute information affixed to the input data indicates a predetermined attribute.

Abstract: The basic idea comprised of the present invention is to provide two sets of descriptors having each at least three descriptors and each set is used in an alternating manner for defining the location of source and target of the copy operations which are to be performed during the defragmentation procedure. The defragmentation procedure is performed as a sequence of copy operations on copy chunks, i.e., a certain number of sequentially arranged bytes to be copied being part of a valid data block to be copied. In each of said copy operations in said sequence the values which are assigned to said descriptors Change. According to a characterizing feature of the present invention during the whole sequence of copy operations comprised of the defragmentation process one of the two sets of descriptors holds information which is usable for restoring the contents of a copy chunk in case of a power break during a copy operation on said copy chunk. Thus, defragmenting is a safe procedure, and data integrity is assured.

Abstract: Data shared by plural processes of a program are identified and identification information is affixed to the shared data. When the program is linked by a linker, only the shared data to which identification information is affixed are extracted and a shared data area is created for the shared data. During program execution, this shared data area is prevented from being and the main memory is referred to or updated or the cache is invalidated prior to access of the shared data area by the linker. An address of data in a processor is computed from an address of the data in another processor based on a specific expression.

Abstract: A cache interface circuit includes a processor interface for receiving memory access requests from a processor, and for transmitting memory data back to the processor in response to processor requests. A main memory interface provides for issuing main memory access requests to a main memory and for receiving main memory data in response. A cache memory interface provides for issuing memory access requests to a cache memory, if operating in a cache mode, and for receiving cache memory data in response. A cache-bypass mode-control signal input provides for the processor to indicate a cache-bypass mode in which memory access requests are serviced from the main memory. A power control output provides for switching off operating power to the cache memory in response to a command received at the cache-bypass mode-control signal input that indicates all memory access requests should be serviced from the main memory.

Abstract: A system includes at least one memory operable to store a first flag identifying whether a cache is disabled and a second flag identifying whether use of the cache is blocked. The system also includes combinatorial logic operable to use the first and second flags to determine whether the cache is used during execution of at least one instruction by a processor. The first flag identifies that the cache is enabled and the second flag identifies that the use of the cache is blocked when the processor is operating in a debugging mode.

Abstract: A cache memory device with a cache section, which is provided between a CPU and a main memory and operates as a fast buffer memory, has a capability of storing input data in the cache section when attribute information affixed to the input data indicates a predetermined attribute.

Abstract: An apparatus, program product and method utilize a cache payback parameter for selectively and dynamically disabling caching for potentially cacheable operations performed in connection with a memory. The cache payback parameter is tracked concurrently with the performance of a plurality of cacheable operations on a memory, and is used to determine the effectiveness, or potential payback, of caching in a particular implementation or environment. The selective disabling of caching, in turn, is applied at least to future cacheable operations based upon a determination that the cache payback parameter meets a caching disable threshold.

Abstract: A method for determining an aging period for retaining a write-back data in a cache memory prior to writing the write-back data to a storage media is determined through use of a write-back aging routine. The aging period is based on a proportional utilization level of the cache memory by the write-back data, the higher the memory utilization level, the shorter the period for aging the write-back data. The aging period takes a form of an aging threshold, which differs depending on the memory utilization level, i.e., the amount of cache memory utilized by the write-back data. The method includes, identifying the memory utilization level, selecting the data aging threshold based on the memory utilization level; and writing the data from the cache memory to the storage media when an age of the data in the memory exceeds the selected data aging threshold.