Abstract: In a processor module having a local software visible data memory and a write through cache connected to an external memory space external to the processor module over a bus, a method and apparatus for supplementing the local software visible data memory utilizing the write through cache is disclosed which may comprise: a processor bus interface and memory management unit adapted to detect a processor write operation to a preselected location in the external memory space that is not currently a cached address line, that will cause a cache miss, to decode the write operation to the preselected external memory space location as a RAM emulation write operation and to place in the cache pseudo data at the respective address line in the cache, without executing a fetch and store from the actual external memory location in response to the cache miss.

Abstract: A multiple-processor integrated circuit has convertible cache modules capable of operating in a local memory mode and a cache mode associated with at least one of its multiple processors. The integrated circuit also has at least one peripheral-specific apparatus for interfacing at least one of its processors to common peripheral devices. At least one processor is capable of operating as a general purpose processor when the convertible cache is operated in the cache mode, and as a processor of an intelligent peripheral when the convertible cache is operated in the local memory mode.

Abstract: A method of and apparatus for improving the scheduling efficiency of a data processing system using the facilities which maintain coherency of the system's level cache memories. These efficiencies result from monitoring the cache memory lines which indicate invalidation of a cache memory entry because of a storage operation within backing memory. This invalidity signal is utilized to generate a doorbell type interface indication of a new application entry within the work queue.

Abstract: A multiprocessor data processing system comprising a plurality of processing units, a plurality of caches, that is each affiliated with one of the processing units, and processing logic that, responsive to a receipt of a first system bus response to a coherency operation, causes the requesting processor to execute operations utilizing super-coherent data. The data processing system further includes logic eventually returning to coherent operations with other processing units responsive to an occurrence of a pre-determined condition. The coherency protocol of the data processing system includes a first coherency state that indicates that modification of data within a shared cache line of a second cache of a second processor has been snooped on a system bus of the data processing system. When the cache line is in the first coherency state, subsequent requests for the cache line is issued as a Z1 read on a system bus and one of two responses are received.

Abstract: Apparatus and methods relating to a cache coherency administrator. The cache coherency administrator can include a display to indicate a cache coherency status of a non-volatile cache.

Abstract: A multiprocessor data processing system comprising, in addition to a first and second processor having an respective first and second cache and a main cache directory affiliated with the first processor's cache, a secondary cache directory of the first cache, which contains a subset of cache line addresses from the main cache directory corresponding to cache lines that are in a first or second coherency state, where the second coherency state indicates to the first processor that requests issued from the first processor for a cache line whose address is within the secondary directory should utilize super-coherent data currently available in the first cache and should not be issued on the system interconnect. Additionally, the cache controller logic includes a clear on barrier flag (COBF) associated with the secondary directory, which is set whenever an operation of the first processor is issued to said system interconnect.

Abstract: A data processing system (100, 600) has a memory hierarchy including a cache (124, 624) and a lower-level memory system (170, 650). A data element having a special write with inject attribute is received from a data producer (160, 640), such as an Ethernet controller. The data element is forwarded to the cache (124, 624) without accessing the lower-level memory system (170, 650). Subsequently at least one cache line containing the data element is updated in the cache (124, 624).

Abstract: A method for improving performance of a multiprocessor data processing system comprising snooping a request for data held within a shared cache line on a system bus of the data processing system whose cache contains an updated copy of the shared cache line, and responsive to a snoop of the request by the second processor, issuing a first response on the system bus indicating to the requesting processor that the requesting processor may utilize data currently stored within the shared cache line of a cache of the requesting processor. When the request is snooped by the second processor and the second processor decides to release a lock on the cache line to the requesting processor, the second processor issues a second response on the system bus indicating that the first processor should utilize new/coherent data and then the second processor releases the lock to the first processor.

Abstract: Adaptive write policy for handling host write commands to write-back system drives in a dual active controller environment. Method for adaptive write policy in data storage system, where data storage system includes host system connected to primary controller and alternate controller. Controllers are coupled to system drive that includes one or more disk storage devices. Primary is connected to first memory and alternate is connected to second memory. Primary and alternate manage data storage system in dual-active configuration. Primary controller receives host write command from host system and write data request includes host write data. When system drive is configured with write-back policy, primary determines whether host write command encompasses an entire RAID stripe, and if so, primary processes host write command in accordance with write-through policy. Otherwise, primary processes command in accordance with write-back policy.

Abstract: The data storage facility includes a plurality of data storage devices coupled through multi-path connections to cache memory. A plurality of interfaces to host processors communicates with the cache memory and with cache tag controllers that define the cache memory again over multiple paths.

Abstract: A method is provided for cache flushing in a computer system having a processor, a cache, a synchronization primitive detector, and a cache flush engine. The method includes providing a synchronization primitive from the processor into the computer system; detecting the synchronization primitive in the synchronization primitive detector; providing a trigger signal from the synchronization primitive detector in response to detection of the synchronization primitive; providing cache information from the recall unit into the computer system in response to the trigger signal; and flushing the cache in response to the cache information in the computer system.

Abstract: An arrangement and method for update of configuration cache data in a disk storage subsystem in which a cache memory (110) is updated using two-phase (220, 250) commit technique.

Abstract: A data processing system having an efficient logging mechanism which stores log records for repairing a file system when its consistency is lost. When there is a transaction attempting to update metadata stored in metadata volumes, a metadata loading unit reads the requested metadata objects out of the volumes and loads them to a metadata cache. At that time, a metadata manager updates its internal database to record from which metadata volume each metadata object has been fetched. Each time the transaction updates a metadata object in the cache, a log collection unit collects a copy of the updated metadata object, together with a volume ID which indicates its home metadata volume. The collected data is temporarily stored in a log buffer, and finally saved into a log volume by a log writing unit.

Abstract: Apparatus and methods relating to a cache coherency administrator. The cache coherency administrator can include a display to indicate a cache coherency status of a non-volatile cache.

Abstract: The invention provides a cache management system comprising in various embodiments pre-load and pre-own functionality to enhance cache efficiency in shared memory distributed cache multiprocessor computer systems. Some embodiments of the invention comprise an invalidation history table to record the line addresses of cache lines invalidated through dirty or clean invalidation, and which is used such that invalidated cache lines recorded in an invalidation history table are reloaded into cache by monitoring the bus for cache line addresses of cache lines recorded in the invalidation history table. In some further embodiments, a write-back bit associated with each L2 cache entry records when either a hit to the same line in another processor is detected or when the same line is invalidated in another processor's cache, and the system broadcasts write-backs from the selected local cache only when the line being written back has a write-back bit that has been set.

Abstract: A method for accelerating input/output operations within a data processing system is disclosed. Initially, a determination is initially made in a cache controller as to whether or not a bus operation is a data transfer from a first memory to a second memory without intervening communications through a processor, such as a direct memory access (DMA) transfer. If the bus operation is such data transfer, a determination is made in a cache memory as to whether or not the cache memory includes a copy of data from the data transfer. If the cache memory does not include a copy of data from the data transfer, a cache line is allocated within the cache memory to store a copy of data from the data transfer.

Abstract: A method for increasing performance optimization in a multiprocessor data processing system. A number of predetermined thresholds are provided within a system controller logic and utilized to trigger specific bandwidth utilization responses. Both an address bus and data bus bandwidth utilization are monitored. Responsive to a fall of a percentage of data bus bandwidth utilization below a first predetermined threshold value, the system controller provides a particular response to a request for a cache line at a snooping processor having the cache line, where the response indicates to a requesting processor that the cache line will be provided. Conversely, if the percentage of data bus bandwidth utilization rises above a second predetermined threshold value, the system controller provides a next response to the request that indicates to any requesting processors that the requesting processor should utilize super-coherent data which is currently within its local cache.

Abstract: A translation lookaside buffer (TLB) that caches memory types of memory address ranges. A data unit includes a TLB which, in addition to caching page table entries including translated page base addresses of virtual page numbers as in a conventional TLB, also caches memory address range memory types provided by a memory type unit (MTU). In the case of a hit of a virtual address in the TLB, the TLB provides the memory type along with the page table entry, thereby avoiding the need for a serialized accessed to the MTU using the physical address output by the TLB. Logic which controls a processor bus access necessitated by the virtual address makes use of the memory type output by the TLB sooner than would be available from the MTU in conventional data units. If the MTU is updated, the TLB is flushed to insure consistency of memory type values.

Abstract: A method and system that enables independent burst lengths for reads and writes to a DRAM subsystem. Specifically, the method provides a mechanism by which read bursts may be longer than write bursts since there are statistically more reads than writes to the DRAM and only some beats of read data are modified and need to be re-written to memory. In the preferred embodiment, the differences in the burst length is controlled by an architected address tenure, i.e., a set of bits added to the read and write commands that specify the specific number of beats to read and/or write. The bits are set by the processor during generation of the read and write commands and prior to forwarding the commands to the memory controller for execution.

Abstract: A cache coherent distributed shared memory multi-processor computer system is provided with a memory controller which includes a recall unit. The recall unit allows selective forced write-backs of dirty cache lines to the home memory. After a request is posted in the recall unit, a recall (“flush”) command is issued which forces the owner cache to write-back the dirty cache line to be flushed. The memory controller will inform the recall unit as each recall operation is completed. The recall unit operation will be interrupted when all flush requests are completed.

Abstract: A method of maintaining coherency in a cache hierarchy of a processing unit of a computer system, wherein the upper level (L1) cache includes a split instruction/data cache. In one implementation, the L1 data cache is store-through, and each processing unit has a lower level (L2) cache. When the lower level cache receives a cache operation requiring invalidation of a program instruction in the L1 instruction cache (i.e., a store operation or a snooped kill), the L2 cache sends an invalidation transaction (e.g., icbi) to the instruction cache. The L2 cache is fully inclusive of both instructions and data. In another implementation, the L1 data cache is write-back, and a store address queue in the processor core is used to continually propagate pipelined address sequences to the lower levels of the memory hierarchy, i.e., to an L2 cache or, if there is no L2 cache, then to the system bus. If there is no L2 cache, then the cache operations may be snooped directly against the L1 instruction cache.

Abstract: A method of operating a processing device is provided. The method includes defining an effective memory address space with a cached address space and a non-cached address space wherein the cached address space and the non-cached address space each translate to overlap a single physical memory space. Further, the method includes accessing a memory address of the physical memory space without accessing a cache memory system from the non-cached effective address space. The method also includes accessing a memory address of the physical memory space from the cached effective address space with the benefit of the cache memory system.

Abstract: A cache memory includes a plurality of memory chips, or other separately addressable memory sections, which are configured to collectively store a plurality of cache lines. Each cache line includes data and an associated cache tag. The cache tag may include an address tag which identifies the line as well as state information indicating the coherency state for the line. Each cache line is stored across the memory chips in a row formed by corresponding entries (i.e., entries accessed using the same index address). The plurality of cache lines is grouped into separate subsets based on index addresses, thereby forming several separate classes of cache lines. The cache tags associated with cache lines of different classes are stored in different memory chips. During operation, the cache controller may receive multiple snoop requests corresponding to, for example, transactions initiated by various processors.

Abstract: A single chip, embedded symmetric multiprocessor (ESMP) having parallel multiprocessing architecture composed of identical processors allows application developers to write code for a single processor case. This code can be ported to a multiprocessor platform with minimal changes. The application boot or kernel code must be modified to support the parallel processing platform. However, the hardware architecture allows the program stream, at the application task or process level, to be divided among different central processing units without change to the application code. The embedded symmetric processor system includes central processing units, complex memory architectures and a wide range of peripheral devices on the single integrated circuit. Such a system normally also includes an interface to large amounts of external memory. Special hardware manages central processing unit interactions with program memory, data memory and peripherals.

Abstract: A direct memory access (DMA) receiver adapted to receive data from a source, such data to be written into a random access memory is provided. The random access memory and DMA receiver being coupled are to a central processing unit by a bus. The central processing unit is coupled to a local cache memory. The source of such data provides an address for the data, such address being the location the random access memory where the data is to be stored. The DMA receiver includes an address register, a first data register and a duplicate data register. The duplicate register has an input coupled to an output of the first data register. A selector is provided having a pair of inputs, one being coupled to the output of the first data register and another one of the pair of inputs being coupled to an output of the duplicate data register. The selector couples one of the pair of inputs to an output thereof selectively in accordance with a select signal. A state machine is included in the DMA receiver.

Abstract: A method, apparatus and article of manufacture for ensuring cache coherency in a database containing a data store on a central data storage device connected to a plurality of computers. When an immediate write option is set, the data in a local buffer pool changed by a first transaction on a first computer is immediately written to a group buffer pool at the central data storage device, prior to initiating a second transaction upon a second computer that relies upon the modified data. Local buffer pools are then invalidated thereby facilitating local buffer pool updates from the group buffer pool. The immediate write (IW) option may be a subsystem parameter set at a system level or a bind option set at a plan level. The immediate write option may be set so that data is written to the group buffer pool at or before a phase one commit.

Abstract: A data storage system comprising a network of PCs each of which includes a cache memory, I/O channel adapter for transmitting data over the channel and a network adapter for transmitting control signals and data over the network. In one embodiment, a method for managing resources in a cache manager ensures consistency of data stored in the distributed cache. In another embodiment, a method for sharing data between two or more heterogeneous hosts including the steps of: reading a record in a format compatible with one computer; identifying a translation module with the second computer; translating the record into a format compatible with the second computer and writing said translated record into a cache memory.

Abstract: According to the present invention, a data processing system includes a cache having a cache directory. A status indication indicative of the status of at least one of a plurality of data entries in the cache is stored in the cache directory. In response to receipt of a cache operation request, a determination is made whether to update the status indication. In response to the determination that the status indication is to be updated, the status indication is copied into a shadow register and updated. The status indication is then written back into the cache directory at a later time. The shadow register thus serves as a virtual cache controller queue that dynamically mimics a cache directory entry without functional latency.

Abstract: A data storage system and method to promote integrity of data written, optionally using a cache with buffer to persistent memory. Health of a computer system is dynamically monitored. If good health is present, during a data write operation, the cache system is configured so data is buffered within the cache, thus promoting faster performance. But if good health is absent, the cache system is configured to write through to persistent memory, thus trading off speed for integrity of the data stored. Optionally, a multi-level cache hierarchy system can be used as the caching system.

Abstract: A cache access control system for dynamically conducting specification of dedicated and common regions and thereby always conducting optimum cache coherency control. In a processor, an L1 cache including an L1 data array and a directory is provided. A plurality of L2 caches are connected to each L1 cache. The L2 caches are connected to a main memory L3. An L2 cache history manager is supplied with L2 cache status information and an L2 cache access request from L2 caches. The L2 cache history manager judges an attribute (a dedicated region or a common region) of each line of L2. On the basis of the attribute, a cache coherency manager conducts coherency control of each L2 cache by using an invalidation type protocol or an update type protocol. The attribute is judged to be the common region, only in the case where a line shared by a plurality of L2 caches in the past is canceled once by the invalidation type protocol and then accessed again.

Abstract: A method of maintaining coherency in a cache hierarchy of a processing unit of a computer system, wherein the upper level (L1) cache includes a split instruction/data cache. In one implementation, the L1 data cache is store-through, and each processing unit has a lower level (L2) cache. When the lower level cache receives a cache operation requiring invalidation of a program instruction in the L1 instruction cache (i.e., a store operation or a snooped kill), the L2 cache sends an invalidation transaction (e.g., icbi) to the instruction cache. The L2 cache is fully inclusive of both instructions and data. In another implementation, the L1 data cache is write-back, and a store address queue in the processor core is used to continually propagate pipelined address sequences to the lower levels of the memory hierarchy, i.e., to an L2 cache or, if there is no L2 cache, then to the system bus. If there is no L2 cache, then the cache operations may be snooped directly against the L1 instruction cache.

Abstract: A method of avoiding deadlocks in cache coherency protocol for a multi-processor computer system, by loading a memory value into a plurality of cache blocks, assigning a first coherency state having a higher collision priority to only one of the cache blocks, and assigning one or more additional coherency states having lower collision priorities to all of the remaining cache blocks. Different system bus codes can be used to indicate the priority of conflicting requests (e.g., DClaim operations) to modify the memory value. The invention also allows folding or elimination of redundant DClaim operations, and can be applied in a global versus local manner within a multi-processor computer system having processing units grouped into at least two clusters.

Abstract: A method and system for performing write-through store operations of valid data of varying sizes in a data processing system, where the data processing system includes multiple processors that are coupled to an interconnect through a memory hierarchy, where the memory hierarchy includes multiple levels of cache, where at least one lower level of cache of the multiple of levels of cache requires store operations of all valid data of at least a predetermined size. First, it is determined whether or not a write-through store operation is a cache hit in a higher level of cache of the multiple levels of cache. In response to a determination that cache hit has occurred in the higher level of cache, the write-through store operation is merged with data read from the higher level of cache to provide a merged write-through operation of all valid data of at least the predetermined size to a lower level of cache.

Abstract: A dedicated block random access memory (RAM) is provided for a programmable logic device (PLD), such as a field programmable gate array (FPGA). The block RAM includes a memory cell array and control logic that is configurable to select one of a plurality of write modes for accessing the memory cell array. In one embodiment, the write modes include a write with write-back mode, a write without write-back mode, and a read then write mode. The control logic selects the write mode in response to configuration bits stored in corresponding configuration memory cells of the PLD. The configuration bits are programmed during configuration of the PLD. In one variation, the control logic selects the write mode in response to user signals. In a particular embodiment, the block RAM is a dual-port memory having a first port and a second port. In this embodiment, the first and second ports can be independently configured to have different (or the same) write modes.

Abstract: A write combining buffer that supports snoop requests includes a first cache memory and a second cache memory. The apparatus also includes a write combining buffer, coupled to the first and second cache memories, to combine data from a plurality of store operations. Each of the plurality of store operations is to at least a part of a cache line, and the write combining buffer can be snooped in response to requests initiated external to the apparatus.

Abstract: A lower level cache detects when a line of memory has been evicted from a higher level cache. The cache coherency protocol for the lower level cache places the line into a special state. If a line in the special state is evicted from the lower level cache, the lower level cache knows that the line is not cached at a higher level, and therefore a back-invalidate transaction is not needed. Reducing the number of back-invalidate transactions improves the performance of the system.

Abstract: A cache coherency mechanism for a computer system having a plurality of processors, each for executing a sequence of instructions, at least one of the processors having a cache memory associated therewith. The computer system includes a memory that provides an address space where data items are stored for use by all of the processors. A behavior store holds in association with an address of each item, a cache behavior identifying the cacheable behavior of the item, the cacheable behaviors including a software coherent behavior and an automatically coherent behavior. When a cache coherency operation is instigated by a cache coherency instruction, the operation is effected dependent on the cacheable behavior associated with the specified address of the item. Methods for modifying the coherency status of a cache are also described.

Abstract: A shared memory parallel processing system interconnected by a multi-stage network combines new system configuration techniques with special-purpose hardware to provide remote memory accesses across the network, while controlling cache coherency efficiently across the network. The system configuration techniques include a systematic method for partitioning and controlling the memory in relation to local verses remote accesses and changeable verses unchangeable data. Most of the special-purpose hardware is implemented in the memory controller and network adapter, which implements three send FIFOs and three receive FIFOs at each node to segregate and handle efficiently invalidate functions, remote stores, and remote accesses requiring cache coherency. The segregation of these three functions into different send and receive FIFOs greatly facilitates the cache coherency function over the network. In addition, the network itself is tailored to provide the best efficiency for remote accesses.

Abstract: An apparatus is presented for expediting the execution of dependent micro instructions in a pipeline microprocessor having design characteristics—complexity, power, and timing—that are not significantly impacted by the number of stages in the microprocessor's pipeline. In contrast to conventional result distribution schemes where an intermediate result is distributed to multiple pipeline stages, the present invention provides a cache for storage of multiple intermediate results. The cache is accessed by a dependent micro instruction to retrieve required operands. The apparatus includes a result forwarding cache, result update logic, and operand configuration logic. The result forwarding cache stores the intermediate results. The result update logic receives the intermediate results as they are generated and enters the intermediate results into the result forwarding cache.

Abstract: An information processing system and a multi-level hierarchical storage device for use in the information processing system having a plurality of instruction processors and a plurality of main storage devices. The multi-level hierarchical storage device includes a first-cache storage device of a write-through type provided for each instruction processor, a second-cache storage device of a write-back type provided for each main storage device, and a third-cache storage device of a write-through type provided between the first-cache storage device and the second-cache storage device.

Abstract: An integrated circuit memory device incorporating a non-volatile memory array and a relatively faster access time memory cache integrated monolithically therewith improves the overall access time in page and provides faster cycle time for read operations. In a particular embodiment, the cache may be provided as static random access memory (“SRAM”) and the non-volatile memory array provided as ferroelectric random access memory wherein on a read, the row is cached and the write back cycle is started allowing subsequent in page reads to occur very quickly. If in page accesses are sufficient the memory array precharge may be hidden and writes can occur utilizing write back or write through caching.

Abstract: A method for avoiding livelocks due to colliding writebacks within a NUMA computer system is disclosed. The NUMA computer system includes at least two nodes coupled to an interconnect. Each of the two nodes includes a local system memory. In response to an attempt by a processor located at a home node to access a modified cache line at a remote node via a memory request at substantially the same time when a processor located at the remote node attempts to writeback the modified cache line to the home node, the writeback is allowed to complete at the home node without retry only if the writeback is from what a coherency directory within the home node considered as an owning node of the modified cache line. The memory request is then allowed to retry and completed at the home node.

Abstract: A cache and method of maintaining cache coherency in a data processing system are described. The data processing system includes a system memory, a plurality of processors, and a plurality of caches coupled to an interconnect. According to the method, a first data item is stored in a first of the caches in association with an address tag indicating an address of the first data item. A coherency indicator in the first cache is set to a first state that indicates that the address tag is valid and that the first data item is invalid. If, while the coherency indicator is set to the first state, the first cache detects a data transfer on the interconnect associated with the address indicated by the address tag, where the data transfer includes a second data item that is modified with respect to a corresponding data item in the system memory, the second data item is stored in the first cache in association with the address tag.

Abstract: A cache and method of maintaining cache coherency in a data processing system are described. The data processing system includes a system memory, a plurality of processors, and a plurality of caches coupled to an interconnect. According to the method, a first data item is stored in a first of the caches in association with an address tag indicating an address of the first data item. A coherency indicator in the first cache is set to a first state that indicates that the address tag is valid and that the first data item is invalid. If, while the coherency indicator is set to the first state, the first cache receives a data transfer on the interconnect associated with the address indicated by the address tag, where the data transfer includes a second data item that is modified with respect to a corresponding data item in the system memory, the second data item is stored in the first cache in association with the address tag.

Abstract: Isochronous information is transferred between an IO device and a first buffer (N) of a plurality of buffers in a system memory. The isochronous information stored in the plurality of buffers is also stored in a memory cache accessible to a system processor. The state of the memory cache is managed according to an isochronous “X-T” contract that is independent of the “X-T” contact with which data are moved between the IO device and system memory. Further, data associated with a given buffer are moved into and out of the memory cache substantially simultaneously with the transfer of isochronous information between the IO device and other buffers in the system memory.

Abstract: A method and apparatus in a computer system selectively stores CPU state related information in parallel in a first and a second set of registers. The two sets of registers can selectively transfer data in parallel therebetween to restore the CPU state related information used by the CPU. The second set of registers cm be organized in a cascaded structure or in selective banks of registers to keep track of multiple CPU state related information such as during nested interrupts. The second set of registers can tansfer data with a third data storage device asynchronously to the operation of the CPU.

Abstract: In a data processing system where a plurality of nodes, each having a plurality of processors and cache memories associated with each of the processors, are connected via a bus, tag information is added to each data block stored in the cache memories. The tag information has state information which includes information (INTERNODE-SHARED) indicative of whether or not the data block is cached in another node. When a write-access is transmitted to the data block in the cache memory, if the state information added to the data block is INTERNODE-SHARED, invalidation of the data block is requested to the other node.

Abstract: In a distributed computing system in which replicas of a document are separately stored and revised, the document containing data arranged in a number of fields, a method for replicating data contained in a revised document replica to the other of the replicas by replicating only the field or fields which have been revised since an earlier replication. The method includes the steps of dynamically maintaining a two byte document sequence number for each of the document replicas representing the number of revisions made to the replicas, and dynamically maintaining a one byte field sequence number for each of the fields in the replicas. The field sequence numbers for revised fields are set equal to the lower byte of the current document sequence number.

Abstract: A microprocessor preemptively write-backs dirty entries of an internal cache. Each cache entry is checked once each predetermined time period to determine if the cache entry is dirty. If dirty, a write history is checked to determine if the cache entry is stale. If stale, the cache entry in preemptively written back to main memory and then marked as clean. The write history includes a count of the number of consecutive predetermined time periods during which there is no write to the cache entry. The cache entry is stale if the count exceeds a predetermined number. For each check of the write history the nonwrite count is incremented if the cache entry has been written to during the prior cycle and decremented if not. Alternatively, the nonwrite count is set to zero if the cache entry has been written to. The dirty cache entry may be marked as clean upon copying to the write-back buffer or, alternatively, when the write-back buffer writes the dirty cache entry to the main memory.

Abstract: Depending on a processor or instruction mode, a data cache block store (dcbst) or equivalent instruction is treated differently. A coherency maintenance mode for the instruction, in which the instruction is utilized to maintain coherency between bifurcated data and instruction caches, may be entered by setting bits in a processor register or by setting hint bits within the instruction. In the coherency maintenance mode, the instruction both pushes modified data to system memory and invalidates the cache entry in instruction caches. Subsequent instruction cache block invalidate (icbi) or equivalent instructions targeting the same cache location are no-oped when issued by a processor following a data cache block store or equivalent instruction executed in coherency maintenance mode. Execution of the data cache clock store instruction in coherency maintenance mode results in a novel system bus operation being initiated on the system bus.