Abstract: A multilevel memory system includes a nonvolatile memory (NVM) device with an NVM media having a media write unit that is different in size than a host write unit of a host controller of the system that has the multilevel memory system. The memory device includes a media controller that controls writes to the NVM media. The host controller sends a write transaction to the media controller. The write transaction can include the write data in host write units, while the media controller will commit data in media write units to the NVM media. The media controller can send a transaction message to indicate whether the write data for the write transaction was successfully committed to the NVM media.

Abstract: A method to provide network storage services to a remote host system, including: generating, from packets received from the remote host system, first control messages and first data messages; buffering, in a random-access memory of a memory sub-system, the first control messages for a local host system to fetch the first control messages, process the first control messages, and generate second control messages; sending the first data messages to a storage device of the memory sub-system without the first data messages being buffered in the random-access memory; communicating the second control messages generated by the local host system to the storage device of the memory sub-system; and processing, within the storage device, the second control messages and the first data messages to provide the network storage services.

Abstract: Various embodiments include a system for managing cache memory in a computing system. The system includes a sectored cache memory that provides a mechanism for sharing sectors in a cache line among multiple cache line allocations. Traditionally, different cache line allocations are assigned to different cache lines in the cache memory. Further, cache line allocations may not use all of the sectors of the cache line, leading to low utilization of the cache memory. With the present techniques, multiple cache lines share the same cache line, leading to improved cache memory utilization relative to prior techniques. Further, sectors of cache allocations can be assigned to reduce data bank conflicts when accessing cache memory. Reducing such data bank conflicts can result in improved memory access performance, even when cache lines are shared with multiple allocations.

Abstract: In described examples, a processor system includes a processor core that generates memory write requests, a cache memory, and a memory controller. The memory controller has a memory pipeline. The memory controller is coupled to control the cache memory and communicatively coupled to the processor core. The memory controller is configured to receive the memory write requests from the processor core; schedule the memory write requests on the memory pipeline; and contemporaneously with scheduling respective ones of the memory write requests on the memory pipeline, send to the processor core a write acknowledgment confirming that writing of a data payload of the respective memory write request to the cache memory has completed.

Abstract: Embodiments of the present invention generally provide for multi-dimensional disk arrays and methods for managing same and can be used in video surveillance systems for the management of real-time video data, image data, or combinations thereof.

Abstract: Provided herein is a memory device including a memory block with memory cells to which word lines and bit lines are connected; page buffers, connected to the memory block through the bit lines, during a program operation, configured to convert original data that is received from an external device into variable data that is divided into groups according to a number of specific data, and configured to apply a program enable voltage or a program inhibit voltage to the bit lines according to the variable data; and a data pattern manager configured to control the page buffers to convert the original data into the variable data during the program operation.

Abstract: Embodiments of the present disclosure generally relate to a target device handling overlap write commands. In one embodiment, a target device includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller includes a random accumulated buffer, a sequential accumulated buffer, and an overlap accumulated buffer. The controller is configured to receive a new write command, classify the new write command, and write data associated with the new write command to one of the random accumulated buffer, the sequential accumulated buffer, or the overlap accumulated buffer. Once the overlap accumulated buffer becomes available, the controller first flushes to the non-volatile memory the data in the random accumulated buffer and the sequential accumulated buffer that was received prior in sequence to the data in the overlap accumulated buffer. The controller then flushes the available overlap accumulated buffer, ensuring that new write commands override prior write commands.

Abstract: A computer implemented method includes obtaining positional information corresponding to end of data (EOD) on a tape and a data extent stored in the tape, wherein the positional information includes longitudinal position (LPOS), latitudinal position (wrap), and number of data blocks, comparing a block number of at least one of a currently read or located data with the positional information of the data extent to identify a current position of a tape head, identifying a positional relationship between a location of data to be read, the positional information of the EOD on the tape, and the current position of the tape head, identifying a directional relationship between a current direction of the tape head locating to data to be read and a pending write direction, and determining an appendable range for data after the EOD on the tape based on the identified positional relationship and the identified directional relationship.

Abstract: In some examples, a system dynamically adjusts a prefetching load with respect to a prefetch cache based on a measure of past utilizations of the prefetch cache, wherein the prefetching load is to prefetch data from storage into the prefetch cache.

Abstract: A method to store a data value onto a cache of a storage hierarchy. A range of a collection of values that resides on a first tier of the hierarchy is initialized. The range is partitioned into disjointed range partitions; a first subset of which is designated as cached; a second subset is designated as uncached. The collection is partitioned into a subset of uncached data and cached data and placed into respective partitions. The range partition to which the data value belongs (i.e. the target range partition) is identified as being cached. If the cache is full, all of the disjointed range partitions are deleted. A first new cached partition range that contains the data value is created; it excludes at least one value that had been cached. The remaining values are placed in uncached range partitions; contents of the cache are updated to reflect the new range partition.

Abstract: An approach is provided that receives a request to write an entry to a database. Database caches are then checked for a portion of the entry, such as a portion that includes a primary key. Based on the checking, the approach determines whether to write the entry to the database. In response to the determination being that the entry cannot be written to the database, an error is returned with the error being returned without accessing the database, only the caches. On the other hand, the entry is written to the database in response to the determination being that the entry can be written to the database.

Abstract: A server having a host processor coupled to a programmable coprocessor is provided. One or more virtual machines may run on the host processor. The coprocessor may be coupled to an auxiliary memory that stores virtual machine (VM) states. During live migration, the coprocessor may determine when to move the VM states from the auxiliary memory to a remote server node. The coprocessor may include a coherent protocol home agent and state tracking circuitry configured to track data modification at a cache line granularity. Whenever a particular cache line has been modified, only the data associated with that cache line will be moved to the remote server without having to copy over the entire page, thereby substantially reducing the amount of data that needs to be transferred during migration events.

Abstract: Disclosed herein is a data structure which includes a sequence of events, each event associated with a sequence number indicating a temporal position of an event within the sequence of events; one or more read-offsets, each read-offset associated with a consumer, wherein each read-offset indicates a sequence number up to which a consumer has read events within the sequence of events; and at least one snapshot which represents events with sequence numbers smaller than the smallest read-offset in a compacted form. Disclosed herein is also a computer-implemented method of maintaining the data structure.

Abstract: Region summaries of database data are stored in persistent memory of a storage cell. Because the region summaries are stored in persistent memory, when a storage cell is powered off and data in volatile memory is not retained, region summaries are nevertheless preserved in persistent memory. When the storage cell comes online, the region summaries already exist and may be used without the delay attendant to regenerating the region summaries stored in volatile memory.

Abstract: An example system includes a processor to receive, from a client device, a delete query requesting deletion of a row of in a fully homomorphically encrypted (FHE) database. The processor can store an identifier of the row to be deleted in a deletion queue, where the row is to be replaced with values of a row to be inserted from a received insertion query.

Abstract: A method to store a data value onto a cache of a storage hierarchy. A range of a collection of values that resides on a first tier of the hierarchy is initialized. The range is partitioned into disjointed range partitions; a first subset of which is designated as cached; a second subset is designated as uncached. The collection is partitioned into a subset of uncached data and cached data and placed into respective partitions. The range partition to which the data value belongs (i.e. the target range partition) is identified as being cached. If the cache is full, the range of the target range partition is reduced until either: the data value is excluded (if the data value is an end point of the partition range); or elements within the target range are evicted to make space for the data value.

Abstract: Disclosed are devices, systems and methods for an audio assistant in an autonomous or semi-autonomous vehicle. In one aspect the informational audio assistant receives a first set of data from a vehicle sensor and identifies an object or condition using the data from the vehicle sensor. Audio is generated representative of a perceived danger of an object or condition. A second set of data from the vehicle sensor subsystem is received and the informational audio assistant determines whether an increased danger exists based on a comparison of the first set of data to the second set of data. The informational audio assistant will apply a sound profile to the generated audio based on the increased danger.

Abstract: A method to store a data value onto a cache of a storage hierarchy. A range of a collection of values that resides on a first tier of the hierarchy is initialized. The range is partitioned into disjointed range partitions; a first subset of which is designated as cached; a second subset is designated as uncached. The collection is partitioned into a subset of uncached data and cached data and placed into respective portions. The range partition to which the data value belongs (i.e. the target range partition) is identified as being cached. If the cache is full, the target range partition is divided into two partitions, the partition that excludes the data value is designated as uncached; the values therein are evicted. If the cache has space, the data value is copied onto the cache; otherwise the division/eviction are repeated until the cache has space.

Abstract: Described is a data cache implementing hybrid writebacks and writethroughs. A processing system includes a memory, a memory controller, and a processor. The processor includes a data cache including cache lines, a write buffer, and a store queue. The store queue writes data to a hit cache line and an allocated entry in the write buffer when the hit cache line is initially in at least a shared coherence state, resulting in the hit cache line being in a shared coherence state with data and the allocated entry being in a modified coherence state with data. The write buffer requests and the memory controller upgrades the hit cache line to a modified coherence state with data based on tracked coherence states. The write buffer retires the data upon upgrade. The data cache writebacks the data to memory for a defined event.

Abstract: Embodiments disclosed herein provide systems, methods, and computer-readable media to implement an object store with removable storage media. In a particular embodiment, a method provides identifying first data for storage on a first removable storage medium and designating at least a portion of the first data to a first data object. The method further provides determining a first location where to store the first data object in a first value store partition of the first removable storage medium and writing the first data object to the first location. Also, the method provides writing a first key that identifies the first data object and indicates the first location to a first key store partition of the first removable storage medium.

Abstract: Aspects of the invention include defining one or more processor units having a plurality of caches, each processor unit comprising a processor having at least one cache, and wherein each of the one or more processor units are coupled together by an interconnect fabric, for each of the plurality of caches, arranging a plurality of cache lines into one or more congruence classes, each congruence class comprises a chronology vector, arranging each cache in the plurality of caches into a cluster of caches based on a plurality of scope domains, determining a first cache line to evict based on the chronology vector, and determining a target cache for installing the first cache line based on a scope of the first cache line and a saturation metric associated with the target cache, wherein the scope of the first cache line is determined based on lateral persistence tag bits.

Abstract: In response to receiving a read request for target data, an external address of the target data is obtained from the read request, which is an address unmapped to a storage system; hit information of the target data in cache of the storage system is determined based on the external address; and based on the hit information, an address from the external address and an internal address for providing the target data is determined. The internal address is determined based on the external address and a mapping relationship. Therefore, it can shorten the data access path, accelerate the responding speed for the data access request, and allow the cache to prefetch the data more efficiently.

Abstract: A data prefetching method and a terminal device are provided. The CPU core cluster is configured to deliver a data access request to a first cache of the at least one level of cache, where the data access request carries a first address, and the first address is an address of data that the CPU core cluster currently needs to access in the memory. The prefetcher in the terminal device provided in embodiments of this application may generate a prefetch-from address, and load data corresponding to the generated prefetch-from address to the first cache. When needing to access the data, the CPU core cluster can read from the first cache, without a need to read from the memory. This helps increase an operating rate of the CPU core cluster.

Abstract: Disclosed herein are system, method, and computer program product embodiments for utilizing an extended cache to access an object store efficiently. An embodiment operates by executing a database transaction, thereby causing pages to be written from a buffer cache to an extended cache and to an object store. The embodiment determines a transaction type of the database transaction. The transaction type can a read-only transaction or an update transaction. The embodiment determines a phase of the database transaction based on the determined transaction type. The phase can be an execution phase or a commit phase. The embodiment then applies a caching policy to the extended cache for the evicted pages based on the determined transaction type of the database transaction and the determined phase of the database transaction.

Abstract: A storage unit includes an interface configured to interface and communicate with a dispersed storage network (DSN), a memory that stores operational instructions, and processing circuitry. The storage unit receives a set of read slice requests for a set of encoded data slices (EDSs) associated with a data object stored within a first set of storage units, where the storage the first set of storage units includes the storage unit. When at least a read threshold number of EDSs and fewer than all of the set of EDSs can be successfully retrieved from the first set of storage units, the storage unit identifies at least one EDS associated with a data object that is stored in a second set of storage units, obtains the at least one EDS and stores the at least one EDS in the storage unit.

Abstract: A processing device can determine a configuration parameter based on a memory type of a memory component that is managed by a memory system controller. The processing device can receive data from a host system. The processing device can generate, by performing a memory operation using the configuration parameter, an instruction based on the data. The processing device can identify a sequencer of a plurality of sequencers that are collocated, within a single package external to the memory system controller, wherein each sequencer of the plurality of sequencers interfaces with a respective memory component. The processing device can send the instruction to the sequencer.

Abstract: A system and method are disclosed for a cache IP that includes registers that are programmed through a service port. Service registers are selected from the registers to define an address range so that all cache lines within the address range can be flushed automatically using a control signal sent to a control register.

Abstract: A method to store a data value onto a cache of a storage hierarchy. A range of a collection of values that resides on a first tier of the hierarchy is initialized. The range is partitioned into disjointed range partitions; a first subset of which is designated as cached; a second subset is designated as uncached. The collection is partitioned into a subset of uncached data and cached data and placed into respective partitions. The range partition to which the data value belongs (i.e. the target range partition) is identified as being cached. If the cache is full all cached range partitions that do not contain the data value are designated as uncached. All values that lie in the cached range partitions designated as uncached are evicted. The data value is then inserted into the target range partition, and copied to the first tier.

Abstract: A plurality of computing devices are communicatively coupled to each other via a network, and each of the plurality of computing devices is operably coupled to one or more of a plurality of storage devices. A plurality of failure resilient address spaces are distributed across the plurality of storage devices such that each of the plurality of failure resilient address spaces spans a plurality of the storage devices. The plurality of computing devices maintains metadata that maps each failure resilient address space to one of the plurality of computing devices. The metadata is grouped into buckets. Each bucket is stored in a group of computing devices. However, only the leader of the group is able to directly access a particular bucket at any given time.

Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory system is disclosed. The memory system includes volatile memory configured as a cache. The cache stores first data at first storage locations. Backing storage media couples to the cache. The backing storage media stores second data in second storage locations corresponding to the first data. Logic uses a presence or status of first data in the first storage locations to cease maintenance operations to the stored second data in the second storage locations.

Abstract: Packet-processing circuitry including one or more flow caches whose contents are managed using a cache-entry replacement policy that is implemented based on one or more updatable counters maintained for each of the cache entries. In an example embodiment, the implemented policy enables the flow cache to effectively catch and keep elephant flows by giving to the caught elephant flows appropriate preference in terms of the cache dwell time, which can beneficially improve the overall cache-hit ratio and/or packet-processing throughput. Some embodiments can be used to implement an Open Virtual Switch (OVS). Some embodiments are advantageously capable of implementing the cache-entry replacement policy with very limited additional memory allocation.

Abstract: [Problem] Change the distribution logic flexibly. [Solution] A control apparatus includes a communication unit (NIC20) configured to receive a packet from a network, a plurality of first control units (3a, 3b, 3c, 3d) configured to function as a plurality of virtual control units (VM1a, 1b, 1c, . . . ), a distribution circuit (Balancer 10a) configured to distribute the received packet to a plurality of dispatchers, a plurality of second control units (Dispatcher 4a, 4b, 4c, and 4d) configured to distribute the packet distributed by the distribution circuit to the plurality of virtual control units (VM1a, 1b, 1c, . . . ), in which the distribution circuit is configured by a PLD.

Abstract: Systems, apparatuses, and methods for implementing a memory fetch granule for real-time agents are described. A computing system includes a plurality of real-time agents coupled to memory via an interconnect fabric and a memory controller. The efficiency of the memory controller is determined by the number of bank groups in the memory devices coupled to the memory controller. A memory fetch granule is defined for the memory controller based on the amount of data that can be accessed in parallel on the memory device in back-to-back access cycles. Each real-time agent accumulates memory requests for sequential physical addresses until the amount of data referenced by the requests reaches the size of the memory fetch granule. Once the memory fetch granule is reached, the real-time agent sends the requests to the memory controller via the fabric. This helps to ensure that the requests will arrive at the memory controller near enough to each other to get grouped together.

Abstract: Methods, systems, and devices for methods for supporting mismatched transaction granularities are described. A memory system may include a host device the performs data transactions according to a first code word size that is different than a second code word size associated with a storage component within the memory system. A cache may be configured to receive, from the host device, a first code word associated of the first code word size and associated with a first address of the storage component. The cache may store the first code word. When the first code word is evicted from the cache, the memory system may generate a third code word of the second size based on the first code word and a second code word stored in the first address of the storage component and store the third code word at the first address of the storage component.

Abstract: In one embodiment, a microprocessor, comprising: a first data cache; and a second data cache configured to process both a miss in the first data cache resulting from a first load or store operation and an eviction from the first data cache to accommodate the first load or store operation, the second data cache configured to indicate to the first data cache that the eviction is complete before the eviction is actually complete based on a first state corresponding to the eviction.

Abstract: A process for wear-leveling in a memory subsystem where references to invalidated chunks and a write count for each of the invalidated chunks of a memory subsystem are received by a wear-leveling manager. The wear-leveling manager orders the received references to the invalidated chunks of the memory subsystem in a tracking structure based on the write count of each of the invalidated chunks, and provides a reference to at least one of the invalidated chunks based on the ordering from the tracking structure to a write scheduler to service a write request, wherein the memory subsystem is wear-leveled by biasing the order of the invalidated chunks to prioritize low write count chunks.

Abstract: The present disclosure relates to transmitting data between multiple processes. An example method includes: establishing, in response to receiving a request to transmit data between a client terminal process and a server process in a computing device, a communication connection between the client terminal process and the server process, allocating shared storage blocks to the communication connection in response to determining that available shared storage blocks exist in the computing device, and transmitting data between the client terminal process and the server process using the shared storage blocks. Corresponding devices and program products are also described. Beneficially, shared storage blocks can provide higher bandwidth for inter-process data transmission, thereby improving the performance of data transmission.

Abstract: A cache memory subsystem includes a virtually-indexed virtually-tagged first-level data cache (L1D) and a physically-indexed physically-tagged second-level set-associative cache (L2). Each L2 entry is uniquely identified by a set index and a way number. The cache memory subsystem has an inclusive allocation policy. When a snoop request that specifies a physical memory line address hits in an entry in the L2, the cache memory subsystem forwards the snoop request to the L1D but substitutes a physical address proxy (PAP) for the physical memory line address. The PAP specifies the way number and the set index of the hit entry in the L2. To process the forwarded snoop request, the L1D uses N bits of the PAP to select S sets and uses the remaining PAP bits (diminutive PAP) for comparison with a diminutive PAP stored in each valid entry of the S selected sets.

Abstract: Disclosed are systems, computer-readable mediums, and methods for receiving a start replication message to replicate a source volume to a replicated volume. A source system forwards I/O requests to the replica server. A data structure associated with the replicated volume is initialized. A write request is received from the source system. The write data is written to the replicated volume and the data structure is updated. Source metadata associated with the source volume is received. The source metadata is compared with prior metadata associated with a prior point-in-time image of the source volume to determine blocks of data that have changed since the prior point-in-time image of the source volume. A first block is determined to not be retrieved based upon the data structure. A second block is determined to be retrieved based upon the data structure. The second block is received and written to the replicated volume.

Abstract: Hierarchical acceleration structures to be used for intersection testing in a ray tracing system are generated. Nodes of the hierarchical acceleration structure represent regions in a scene, and are linked to form the hierarchical acceleration structure. Data is stored representing the hierarchical acceleration structure defining the regions represented by a plurality of the nodes of the hierarchical acceleration structure. At least one node of the hierarchical acceleration structure is an implicitly represented node, wherein data defining a region represented by an implicitly represented node is not explicitly included as part of the stored data but can be inferred from said stored data. Ray tracing systems and computer-implemented methods perform intersection testing in the ray tracing system in which, based on conditions in the ray tracing system, a determination is made as to whether testing of one or more rays for intersection with a region represented by a particular node of a sub-tree is to be skipped.

Abstract: A method for indexing dirty data in a storage system page includes: obtaining a point quantity of storage points in the storage page and dirty data distribution information; creating a bitmap based on the point quantity and dirty data distribution information; creating an extended segment set based on the dirty data distribution information, and obtaining the number of current extended segments in the extended segment set; obtaining, according to the point quantity, a first storage cost for indexing dirty data using the bitmap in the target storage page; obtaining, according to the number of current extended segments and the segment capacity, a second storage cost for indexing dirty data using the extended segments in the target storage page; and determine, according to the first storage cost and the second storage cost, to index the dirty data in the target storage page by means of the bitmap or the extended segments.

Abstract: Provided is a method for operating a measurement system including an evaluation module and several measuring elements. The evaluation module and the measuring elements are connected via a communication line. The method includes detecting measurement data via the several measuring elements. At least two of the measuring elements detect the measurement data at least partially at the same time. The method further includes: buffering the detected measurement data in the respective measuring element; and reading out the measurement data buffered in the measuring elements with the evaluation module via the communication line.

Abstract: An analysis device configured to be connected to an information processing apparatus configured to mount a first memory and a low-speed second memory, the low-speed second memory being cheaper and having lower performance than the first memory and being used for memory capacity expansion, the analysis device being configured to perform program instructions including: causing the information processing apparatus to execute a plurality of types of performance evaluation application programs and acquire memory performance characteristic information regarding each performance evaluation application program from the information processing apparatus; determining a recommended memory configuration according to the performance evaluation application program corresponding to the application to be evaluated program among the plurality of types of performance evaluation application programs by using a collection result of the memory performance characteristic information; and outputting recommended memory configuration

Abstract: Techniques perform data writing. Such techniques involve: in response to receiving a first write request, searching a cache for a target address associated with the first write request; in response to missing of the target address in the cache, determining a page usage rate in the cache; and in response to determining that the page usage rate exceeds an upper threshold, performing the first write request with a first available page in the cache. The first available page is reclaimed, independent of a refresh cycle of the cache, in response to completing the performing of the first write request.

Abstract: An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store requests to the L2 cache memory. The arbitration mechanism includes control logic that enables a load request to interrupt a store request that the L2 cache memory is currently servicing. When the L2 cache memory finishes servicing the interrupting load request, the L2 cache memory may return to servicing the interrupted store request at the point of interruption.

Abstract: A computer-implemented method for maintaining a storage volume in a virtual tape system includes writing one or more logical volumes associated with a first category and one or more logical volumes associated with a second category to a primary storage in a virtual tape system. The computer-implemented method further includes performing a first automatic removal process in order to free up space on the primary storage, wherein the first automatic removal process removes logical volumes associated with the first category in priority to logical volumes associated with the second category. The computer-implemented method further includes performing a second automatic removal process, wherein the second automatic removal process dynamically alters the priority of the first automatic removal process such that one or more virtual volumes associated with the second category are removed in priority to one or more virtual volumes associated with the first category.

Abstract: Utilizing physical cache address comparison for maintaining coherency. Operations are performed on data in lines of a cache of the computing system and virtual addresses are loaded into a cache controller. The virtual addresses correspond with lines associated with performing the operations. A physical address of a line is determined in response to having performed a first cache directory lookup of the line. The physical address from the first operation is compared with other physical addresses associated with other operations to determine whether the other operations utilize the same physical address as the first operation. In response to matching physical locations, determinations are made as to whether a conflict exists in the data at the physical addresses that match. Thus, the coherency maintenance is free from looking up virtual addresses to determine whether the line of the cache includes incoherent data.

Abstract: A method for execution by one or more processing modules of one or more computing devices of a dispersed storage network (DSN), the method begins by receiving a dispersed storage network (DSN) access request and determining an endpoint address from which the DSN access request is originating. The method continues by determining a first geographic location based on the endpoint address. The method continues by determining a target bucket and object the DSN access request is associated with and determining a second geographic location of the target bucket. For differing first and second geographic locations, the method continues by creating a mirror bucket in the first geographic location and configuring an access layer to route future DSN access requests to the mirror bucket based on TTL needs.

Abstract: A two-level main memory that includes a persistent memory and a cache is provided. Locations of dirty cache lines in the cache are tracked through the use a dirty cache line tracker. The dirty cache line tracker is stored in the cache and can be cached in a memory controller for the persistent memory. The dirty cache line tracker can be used to bypass cache lookup, perform efficient dirty cache line scrubbing and to decouple battery power and capacity of the cache in the two-level main memory.

Abstract: According to one embodiment, an information processing apparatus includes a memory includes a buffer area, a first storage, a second storage and a driver. The buffer area is reserved in order to transfer data between the driver and a host system that requests for data writing and data reading. The driver is configured to write data into the second storage and read data from the second storage in units of predetermined blocks using the first storage as a cache for the second storage. The driver is further configured to reserve a cache area in the memory, between the buffer area and the first external storage, and between the buffer area and the second storage. The driver is further configured to manage the cache area in units of the predetermined blocks.