Abstract: Table of contents (TOC) pointer cache entry having a pointer for a range of addresses. An address of a called routine and a pointer value of a pointer to a reference data structure to be entered into a reference data structure pointer cache are obtained. The reference data structure pointer cache includes a plurality of entries, and an entry of the plurality of entries includes a stored pointer value for an address range. A determination is made, based on the pointer value, whether an existing entry exists in the reference data structure pointer cache for the pointer value. Based on determining the existing entry exists, one of an address_from field of the existing entry or an address_to field of the existing entry is updated using the address of the called routine. The stored pointer value of the existing entry is usable to access the reference data structure for the address range defined by the address_from field and the address_to field.

Abstract: Systems, apparatuses, and methods related to storage device operation orchestration are described. A plurality of computing devices (or “tiles”) can be coupled to a controller (e.g., an “orchestration controller”) and an interface. The controller can control operation of the computing devices. For instance, the controller can include circuitry to request a block of data from a memory device coupled to the apparatus, cause a processing unit of at least one computing device of the plurality of computing devices to perform an operation on the block of data in which at least some of the data is ordered, reordered, removed, or discarded, and cause, after some of the data is ordered, reordered, removed, or discarded, the block of data to be transferred to the interface coupled to the plurality of computing devices.

Abstract: A distributed search framework with virtual indexing is disclosed. According to some embodiments, a virtual index that includes a first physical index is created, where the first physical index includes a first number of shards. A request to index a document is received. In response to the request, whether the first physical index has reached a capacity threshold is determined. In response to determining that the first physical index has reached the capacity threshold, a second physical index is automatically created and added to the virtual index, where the second physical index includes a second number of shards. The document is added into the second physical index.

Abstract: A Basic Input/Output System (BIOS) agent on a Self-Service Terminal (SST) coordinates with a BIOS credential manager that determines when to communicate a BIOS credential for the SST and when to re-generate and re-set a new BIOS credential for the SST.

Abstract: A storage device includes a storage region in which first data is stored and that is accessed using a first virtual address, and a memory controller configured to control stored data stored in the storage region. The memory controller predicts second data to be accessed using a second virtual address based on the first virtual address, prefetches the second data into an external device, and modifies a physical address mapped to the second virtual address so that the prefetched second data is accessible by a host in communication with the storage device.

Abstract: A determination is made that a source group of data management units of a memory component satisfies a threshold wear condition. A wear leveling operation is performed by copying data from a first data management unit of the source group of data management units to a second data management unit of a destination group of data management units of the memory component. A logical address of the first data management unit is determined. Indicators in a mapping data structure are moved from entries associated with the first data management unit to another entries in the mapping data structure that are subsequent to the entries associated with the first data management unit. The indicators are used to access data requested by a host system at the source group of data management units or at the destination group of data management units.

Abstract: A sink device is configured to establish a Bluetooth connection with a source device. The sink device receives a transmission from the source device that includes a plurality of data blocks, an item of check information, and a plurality of parity blocks during a transmission time duration. The sink device determines, prior to receiving an entirety of the transmission, whether at least one of received data blocks includes an error based on at least the item of check information and, when the at least one of the received data blocks includes the error and prior to receiving all of the plurality of parity blocks, the sink device performs an error correction operation on a first one of the received data blocks based on a first one of the parity blocks.

Abstract: Minimizing traversal of a processor reorder buffer (ROB) for register rename map table (RMT) state recovery for interrupted instruction recovery in a processor. Instructions may execute out of order in a processor. Information about the logical register-to-physical register mapping resulting from each instruction is stored in entries in program order in the ROB. When the pipeline is interrupted by an instruction that fails to execute, changing program flow, all instructions following the interrupting instruction may be flushed from the processor pipeline. It is important to return the state of the RMT to the state that existed when the interrupting instruction entered the pipeline. To recover the RMT state in response to an interrupting instruction, register mapping information in the ROB entries is traversed to either undo the younger instructions that entered the pipeline after the interrupting instruction or replay the older instructions that entered the pipeline before the interrupting instruction.

Abstract: Systems, apparatuses and methods may provide for technology that reads a lower page, one or more intermediate pages and a last page from a set of multi-level non-volatile memory (NVM) cells, wherein one or more of a lower read time associated with the lower page or a last read time associated with the last page is substantially similar to an intermediate read time associated with the one or more intermediate pages.

Abstract: Abstraction programming models of enclave security platforms are described, including receiving a request from an enclave client according to a client abstraction protocol, converting the request into a native enclave protocol, and sending the converted request to a native platform. The request may be, for example: a request to instantiate an enclave, verify an attestation report of an enclave, a request to call into an enclave, or a request to allocate memory that is shared with both the enclave and the enclave client.

Abstract: A data writing method is provided. The method includes receiving a first write command and first data corresponding to the first write command from a host system, wherein the first write command instructs to store the first data into a first logical address; copying the first data into a register, responding to the host system that the first write command is completed, and starting to execute a first program operation to program the first data into a first physical page; and in response to determining that the first program operation is failed, reading the first data from the register according to a logical to physical addresses mapping table and mandatorily programming the first data into a second physical page.

Abstract: Memory address translation apparatus comprises page table access circuitry to access page table data to retrieve translation data defining an address translation between an initial memory address in an initial memory address space, and a corresponding output memory address in an output address space; a translation data buffer to store, for a subset of the virtual address space, one or more instances of the translation data; and control circuitry, responsive to an input initial memory address to be translated, to request retrieval of translation data for the input initial memory address from the translation data buffer and, before completion of processing of the request for retrieval from the translation data buffer, to initiate retrieval of translation data for the input initial memory address by the page table access circuitry.

Abstract: An input data may be received. Memory pages may be identified where each of the memory pages includes one or more cache lines. A first index table that includes cache lines may be generated from the memory pages based on the input data. Subsequently, an output data may be provided based on a particular cache line from the cache lines of the first index table.

Abstract: A marking capability is used to provide an indication of whether a block of memory is backing an address translation structure of a control program being managed by a virtual machine manager. By providing the marking, the virtual machine manager may check the indication prior to making paging decisions. With this information, a hint may be provided to the hardware to be used in decisions relating to purging associated address translation structures, such as translation look-aside buffer (TLB) entries.

Abstract: In one embodiment, a method includes creating, by an operating system executed by a computing device an inter process communication (IPC) channel and a port for a process executed in a user space of the operating system. The IPC channel is associated with a key, and the port comprises a port buffer mapped to a first virtual address space of a kernel of the operating system and to a second virtual address space of the process. A message for the process is written in a message buffer associated with the IPC channel. The kernel determines whether the process is actively consuming messages in the message buffer. Responsive to determining that the process is not actively consuming messages, a notification packet is written in the port buffer. The packet includes an action type and the key and causes the process to consume the message based on the action type and key.

Abstract: A memory includes a memory array comprising a plurality of pages, a page buffer, and search logic. The page buffer includes first registers, second registers, compare logic, and third registers. The first registers store data read from a page of the memory array. The second registers store a user pattern. The compare logic compares the data stored in the first registers to the user pattern stored in the second registers. The third registers store the comparison results. The search logic is configured to identify addresses of the memory array where the comparison results stored in the third registers indicate a match between the data read from the page and column of the memory array and the user pattern. The first registers are loaded with data from a following page of the memory array concurrently with the search logic identifying addresses indicating a match in a previous page of the memory array.

Abstract: A method for accessing data by a solid state disk is provided, which includes steps of: configuring at least one NAND die to be dedicated for writing random data and other NAND dies to be dedicated for writing sequential data; configuring one of the NAND dies dedicated for writing the sequential data to include memory cells each of which is allowed to be used for storing a data stream having the maximum number of bits; configuring one of the NAND dies dedicated for writing the random data to include memory cells each of which is used for storing a data stream having the number of bits that is smaller the maximum number of the bits; and determining the total number of the bits of one of the data streams of the random data written by the NAND dies and accordingly reconfiguring the NAND dies.

Abstract: Systems and methods are provided to reduce the number of redundant copy operations performed as part of a live migration of a virtual machine executing a guest. A hypervisor can queue the copy operations in a processing engine. While pre-copying for the live migration of the VM, the guest may continue to write to the pages. In one embodiment, the processing engine may clear a dirty page just before performing the copy operation of the modified page to a target device, thus extending the window of time to capture any future writes to that page.

Abstract: System and method for conversion of virtual machine files without requiring copying of the virtual machine payload (data) from one location to another location. By eliminating this step, applicant's invention significantly enhances the efficiency of the conversion process. In one embodiment, a file system or storage system provides indirections to locations of data elements stored on a persistent storage media. A source virtual machine file includes hypervisor metadata (HM) data elements in one hypervisor file format, and virtual machine payload (VMP) data elements.

Abstract: Table of contents (TOC) pointer cache entry having a pointer for a range of addresses. An address of a called routine and a pointer value of a pointer to a reference data structure to be entered into a reference data structure pointer cache are obtained. The reference data structure pointer cache includes a plurality of entries, and an entry of the plurality of entries includes a stored pointer value for an address range. A determination is made, based on the pointer value, whether an existing entry exists in the reference data structure pointer cache for the pointer value. Based on determining the existing entry exists, one of an address_from field of the existing entry or an address_to field of the existing entry is updated using the address of the called routine. The stored pointer value of the existing entry is usable to access the reference data structure for the address range defined by the address_from field and the address_to field.

Abstract: Implementations are provided herein for using relative generation numbers for deduplicating kernel events modification events. The process can identify multiple modification events that take place on the same inode within a configurable relative amount of time and deduplicate the events against one another. A hash table can be used to store a global list of events associated with inodes, and thus only the hash table need be deduplicated. Filter buffer(s) setup when an Server Message Block (“SMB”) client requests a change notifications on a file and/or directory can then use the data from the hash table(s) to notify clients of change notify events.

Abstract: Described are examples for securing stream data received from a stream source. A secure mode can be enabled, based on a request from an application, for storing the stream data captured from the stream source in a secured buffer. The secured buffer can be allocated in a secure memory based at least in part on enabling the secure mode. A secured buffer identifier of the secured buffer can be provided to a driver of a device providing the stream source for storing the stream data captured from the stream source in the secured buffer. The secured buffer identifier of the secured buffer can also be provided to the application for accessing the stream data stored in the secured buffer.

Abstract: Embodiments are provided for implementing a transparent conversion of common virtual storage requests to storage with limited access. Embodiments include providing a storage manager configured to perform address translation for requests, providing a data address translation (DAT) structure configured to connect a higher-level DAT table to a lower-level DAT table, and creating the DAT structure based on a request from a process. Embodiments also include responsive to receiving a storage request, performing a DAT fault process based on validating user credentials associated with an entry of the higher-level DAT table corresponding to the storage request, and responsive to the validation, updating the higher-level DAT table entry to allow access to the restricted-use portion of the common virtual storage, and otherwise, returning a DAT fault for the higher-level DAT table entry.

Abstract: A system and method for a function-as-a-service platform that includes creating a set of distinct webservices within a webservice hosting platform, which involves receiving a webservice resource definition, processing the webservice resource definition, and instantiating a webservice of the webservice resource definition within the webservice hosting platform; and invoking a webservice instantiated in the webservice hosting platform for a client device, which involves: receiving a webservice function call request, executing the webservice function call request on a webservice instance, and responding to the webservice function call request with a result of the webservice.

Abstract: Table of contents (TOC) pointer cache entry having a pointer for a range of addresses. An address of a called routine and a pointer value of a pointer to a reference data structure to be entered into a reference data structure pointer cache are obtained. The reference data structure pointer cache includes a plurality of entries, and an entry of the plurality of entries includes a stored pointer value for an address range. A determination is made, based on the pointer value, whether an existing entry exists in the reference data structure pointer cache for the pointer value. Based on determining the existing entry exists, one of an address_from field of the existing entry or an address_to field of the existing entry is updated using the address of the called routine. The stored pointer value of the existing entry is usable to access the reference data structure for the address range defined by the address_from field and the address_to field.

Abstract: The described embodiments include an input-output memory management unit (IOMMU) with two or more memory elements and a controller. The controller is configured to select, based on one or more factors, one or more selected memory elements from among the two or more memory elements for performing virtual address to physical address translations in the IOMMU. The controller then performs the virtual address to physical address translations using the one or more selected memory elements.

Abstract: A method of distributed file deletion, performed by a storage system, is provided. The method includes receiving, at the storage system, a request to delete a directory and contents of the directory and adding the directory to a first set, listed in a memory in the storage system. The method includes operating on the first set, by examining each directory in the first set to identify subdirectories, adding each identified subdirectory to the first set as a directory, and adding each examined directory to a second set listed in the memory. The method includes deleting in a distributed manner across the storage system without concern for order, contents of directories, and the directories, listed in the second set.

Abstract: The presently disclosed subject matter includes various inventive aspects, which are directed to direct read access of a host computer device to a share storage space in a data storage system, as well as control of the direct read of the host computer device by a control computer device in the data storage system.

Abstract: A computerized method for enabling a client device seamless access to a plurality of remote storage devices connected to the client device via a communication network. The method comprises receiving a plurality of physical addresses by a controller communicatively coupled to the client device and to a plurality of storage servers, each of the plurality of storage servers communicatively coupled to at least one storage device, the plurality of physical addresses enabling access by the controller to the remote storage devices. A single virtual storage device having a logical address space is generated on the device, wherein each of the plurality of physical addresses is mapped by the controller to a unique logical address of the virtual storage device.

Abstract: A computer-implemented method, according to one embodiment, includes: determining that a data storage drive in a first array has failed, determining a location to rebuild the failed data storage drive, instructing performance of a rebuild operation at the determined location, determining one or more data storage drives in one or more arrays having a combined amount of available space that is sufficient to mirror data and/or parity information of the first array, instructing mirroring of the data and/or parity information of the first array in parallel with performing the rebuild operation, instructing deletion of the mirrored data and/or parity information of the first array from the one or more data storage drives in response to the rebuild operation being completed, and instructing reallocation of the space in the one or more data storage drives used to mirror the data and/or parity information of the first array as available space.

Abstract: In example implementations, mapping fields and respective operation fields may be stored in a translation lookaside buffer (TLB) of a central processing unit (CPU) that is communicatively coupled to a storage volume. The operation fields may be populated based on processes, running on the CPU, corresponding to the respective mapping fields. In response to a storage volume access request generated by one of the processes, and based on contents of one of the mapping fields that matches the storage volume access request, a memory address corresponding to a memory location in the storage volume may be identified. A translated address based on the identified memory address, and contents of the respective operation field, may be transmitted to a media controller communicatively coupled to the CPU and the storage volume.

Abstract: The present subject matter relates to migrating a virtual machine (VM) from a source server to a destination server. The migration involves computation of a suitability score for each particular server in the plurality of candidate servers. The suitability score for a server indicates the suitability of the server to host the VM. In an example implementation, the suitability score for a server is computed based on satisfaction of at least one criterion for operation of the VM by the server.

Abstract: The present disclosure discloses a read/write path determining method and apparatus. The method is used by a physical host. The method includes: obtaining, by the host, a first read/write request of the virtual machine, where the first read/write request includes a first virtual address, searching for the first virtual address in an address translation information set, and determining to process the first read/write request by using the block device or the virtual block device according to the address translation information set and the first virtual address. According to the method and apparatus, an appropriate read/write path is determined according to a read/write request and an address translation information set, so that both storage performance and a storage function can be considered.

Abstract: Various embodiments are generally directed to techniques for compiler sheltered nonvolatile memory (NVM) stores, such as based on demarcated atomic persistence regions in source code, for instance. Some embodiments are particularly related to a compiler that effectively shelters updates to NVM-based variables in a compiler implemented register, or register file, until the compiler has recorded undo values into a temporary but nonvolatile log range.

Abstract: Technologies are provided in embodiments for using compiling techniques to harden software programs from branching exploits. One example includes program instructions for execution to obtain a first encoded instruction of a software program, the first encoded instruction including a first opcode in a first field to be performed when the first encoded instruction is executed, identify a vulnerable value in a second field within the first encoded instruction, where the vulnerable value includes a second opcode, determine that the first encoded instruction can be replaced with one or more alternative encoded instructions that do not contain the vulnerable value, and replace the first encoded instruction with the one or more alternative encoded instructions.

Abstract: An I/O control method and system for respectively achieving both acceleration of I/O processing and redundantization of data. The present invention is based upon an I/O control method of performing control related to an I/O request from a virtual machine operated in a computer provided with an I/O device that executes I/O processing, and the I/O control method includes a first step in which an I/O analysis unit determines whether or not data redundantization processing related to the I/O request is executed on the basis of the I/O request from the virtual machine and setting information for enabling identifying whether or not the data redundantization processing is executed and a second step in which a control unit transmits an I/O command related to the I/O request to a data redundantization mechanism that executes the data redundantization processing on the basis of a determination result in the first step.

Abstract: A computer-implemented method according to one embodiment includes identifying a data write to a specific position within a virtual address space, determining an entry within a metadata structure that corresponds to the specific position within the virtual address space, and adding state information associated with the data write to the entry within the metadata structure, the state information including a size of the data write within the virtual address space and an alignment of the data write within the virtual address space.

Abstract: A virtual-to-virtual page table maps a main surface containing the actual data and a metadata or auxiliary surface that gives information about compression of the main surface. In order to access the metadata that corresponds to main surface, an additional virtual-to-virtual table may be used ahead of the regular page table mapping to avoid the need to pass the metadata base address and x, y coordinates across a pipeline which may result in multiple memory writes.

Abstract: A display controller for a data processing system includes a memory read sub-system operable to read data of input surfaces to be used as input layers to be processed by the display controller. The memory read sub-system is operable to request in advance the loading of memory address translation data into a memory address translation data cache for memory pages storing data relating to an input surface. The memory read sub-system selects the memory pages that it requests the advance loading of address translation data for based on information relating to the data for the input surface that will be required by the display controller to generate the output surface, such as the vertical and horizontal size of the input layer that the input surface will be used for, an indication of any flipping or rotation of the input surface, etc.

Abstract: A computing device that handles address translations is described. The computing device includes a hardware table walker and a memory that stores a reverse map table and a plurality of pages of memory. The table walker is configured to use validated indicators in entries in the reverse map table to determine if page accesses are made to pages for which entries are validated. The table walker is further configured to use virtual machine permissions levels information in entries in the reverse map table determine if page accesses for specified operation types are permitted.

Abstract: Disclosed herein are a memory device and a method of operating the memory device. The memory device may include a memory cell array, a peripheral circuit, and a control logic. The memory cell may a plurality of main memory blocks and a plurality of sub-memory blocks included in each of the main memory blocks. The peripheral circuit may perform a program operation on the main memory blocks or the sub-memory blocks, detect an amount of data loaded for the program operation, and output data amount information. The control logic may control the peripheral circuits so that, during the program operation, at least one memory block is selected from the main memory blocks or from the sub-memory blocks according to the data amount information and the program operation is performed on the selected memory block.

Abstract: A memory system having multiple memory layers includes a first memory layer comprising a volatile memory, a second memory layer comprising a first sub-memory and a second sub-memory. In response to a reference failure that occurred in the first memory layer, to which a read reference failed data and a write reference failed data are respectively loaded from a lower level memory layer.

Abstract: An example method of provisioning a virtual appliance to a virtualized computing system, comprising: deploying the virtual appliance to the virtualized computing system, the virtual appliance including a system partition, one or more disk images, and configuration data, the configuration data defining a virtual machine executable on each of a plurality of processor architectures, the system partition configured to boot on any one of the plurality of processor architectures; and booting the virtual appliance from the system partition.

Abstract: Agencies issue recording devices to personnel for administrating and monitoring controlled calls during the course of their duties. To provide flexible capabilities to agencies, a virtual number is provisioned and configured to enable an operator to administrate controlled calls without dedicated recording devices. Using the virtual number, the operator may setup a controlled call between a victim and a baddie. The victim is contacted via the virtual number by the operator and optionally informed about the controlled call process. In turn, the baddie is contacted using number information of the victim's phone and connected with the victim. Call audio between the victim and baddie is transmitted to the operator. When necessary, the operator may terminate the call remotely from the telephonic device the operator used to setup the call.

Abstract: Various approaches are described herein for, among other things, detecting and/or neutralizing attacks by malicious code. For example, instance(s) of a protected process are modified upon loading by injecting a runtime protector that creates a copy of each of the process' imported libraries and maps the copy into a random address inside the process' address space to form a “randomized” shadow library. The libraries loaded at the original address are modified into a stub library. Shadow and stub libraries are also created for libraries that are loaded after the process creation is finalized. Consequently, when malicious code attempts to retrieve the address of a given procedure, it receives the address of the stub procedure, thereby neutralizing the malicious code. When the original program's code (e.g., the non-malicious code) attempts to retrieve the address of a procedure, it receives the correct address of the requested procedure (located in the shadow library).

Abstract: Various embodiments are generally directed to an apparatus, method and other techniques to receive a request from a core, the request associated with a memory operation to read or write data, and the request comprising a first address and an offset, the first address to identify a memory location of a memory. Embodiments include performing a first iteration of a memory indirection operation comprising reading the memory at the memory location to determine a second address based on the first address, and determining a memory resource based on the second address and the offset, the memory resource to perform the memory operation for the computing resource or perform a second iteration of the memory indirection operation.

Abstract: Methods, systems, and apparatus for receiving a request to access, from a main memory, data contained in a first portion of a first page of data, the first page of data having a first page size; initiating a page fault based on determining that the first page of data is not stored in the main memory; allocating a portion of the main memory equivalent to the first page size; transferring the first portion of the first page of data from the secondary memory to the allocated portion of the main memory without transferring the entire first page of data; and updating a first page table entry associated with the first portion of the first page of data to point to a location of the allocated portion of the main memory to which the first portion of the first page of data is transferred.

Abstract: Systems and methods that enable user space processing threads to handle hardware events (e.g., page faults) for another processing thread in a security-enhanced manner. An example method may comprise: associating, by a processing device executing a kernel, a first processing thread with a storage unit of a second processing thread; detecting, by a processing device, a hardware event corresponding to an address of the storage unit; determining a storage object comprising data of the storage unit; translating the address of the storage unit to an offset of the storage object; and transmitting, by the kernel, a notification of the hardware event to the first processing thread, wherein the notification comprises the offset.

Abstract: Apparatuses, methods and storage medium associated with application execution enclave cache management, are disclosed herein. In embodiments, an apparatus may include one or more processors with supports for application execution enclaves; cache memory coupled with the one or more processors to be organized into a plurality of cache pages; and an exception handler to be operated by the one or more processors to handle cache page fault exceptions, wherein to handle cache page fault exceptions includes to handle a cache page fault triggered to request additional allocation of one or more cache pages to an execution enclave of an application. Other embodiments may be described and/or claimed.

Abstract: A first data storage device may be connected to first and second entities as part of a distributed network with each entity having direct block level access to logical block addresses of the first data storage device. The first data storage device can consist of a provisioning module and a staging buffer with the provisioning module configured to store and acknowledge non-volatile write data in the staging buffer in response to a write request to any logical block address of a range of logical block addresses in the first data storage device. The provisioning module may return previously committed data resident in the range of logical block addresses instead of the write data resident in the staging buffer until a commit signal is received from at least one entity for the write data.