Abstract: Provided are techniques for allocating logical memory corresponding to a logical partition in a computing system; generating a S/W PFT data structure corresponding to a first page of the logical memory, wherein the S/W PFT data structure comprises a field indicating that the corresponding first page of logical memory is a klock page; transmitting a request for a page of physical memory and the corresponding S/W PFT data structure to a hypervisor; allocating physical memory corresponding to the request; and, in response to a pageout request, paging out available logical memory corresponding to the logical partition that does not indicate that the corresponding page is a klock page prior to paging out the first page.

Abstract: Provided are techniques for allocating logical memory corresponding to a logical partition in a computing system; generating, a S/W PFT data structure corresponding to a first page of the logical memory, wherein the S/W PFT data structure comprises a field indicating that the corresponding first page of logical memory is a klock page; transmitting a request for a page of physical memory and the corresponding S/W PFT data structure to hypervisor, allocating physical memory corresponding to the request; and, in response to a pageout request, paging out available logical memory corresponding to the logical partition that does not indicate that the corresponding page is a klock page prior to paging out the first page.

Abstract: A system configures page tables to cause an operating system to copy original page data in a data store when any one of the application processes makes a first write request for the original page data. The system detects a page fault from a memory management unit receiving a first write request from one of the application processes and creates the copy in physical memory to allow the application process to modify the page data copy. The other application processes have read access to the original page data. The system replaces the original page data in the data store with the page data copy in response to receiving a first synchronization request from the application process and updates a page table for one of the other application processes to configure access to the replaced page data in response to receiving a second synchronization request from the one other application process.

Abstract: A system and method for maintaining a mapping table in a data storage subsystem. A data storage subsystem supports multiple mapping tables including a plurality of entries. Each of the entries comprise a tuple including a key. A data storage controller is configured to encode each tuple in the mapping table using a variable length encoding. Additionally, the mapping table may be organized as a plurality of time ordered levels, with each level including one or more mapping table entries. Further, a particular encoding of a plurality of encodings for a given tuple may be selected based at least in part on a size of the given tuple as unencoded, a size of the given tuple as encoded, and a time to encode the given tuple.

Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.

Abstract: Various embodiments disclosed herein including systems and methods for improving allocation of computing resources in a virtual machine (VM) environment. Embodiments maintain data relating to how VM image data is stored in storage devices and loaded into volatile memory such as random access memory (RAM). The data is then used to identify common content in the volatile memory that can be shared across VM instances. In some embodiments, multiple VM instances can share at least a portion of a single common VM image loaded into a shared volatile memory.

Abstract: A system includes a device coupleable to a first memory. The device includes a second memory to cache data from the first memory. The second memory is to store a set of compressed pages of the first memory and a set of page descriptors. Each compressed page includes a set of compressed data blocks. Each page descriptor represents a corresponding page and includes a set of location identifiers that identify the locations of the compressed data blocks of the corresponding page in the second memory. The device further includes compression logic to compress data blocks of a page to be stored to the second memory and decompression logic to decompress compressed data blocks of a page accessed from the second memory.

Abstract: A data storage system is disclosed that utilizes a high performance caching architecture. In one embodiment, the caching architecture utilizes a cache table, such as a lookup table, for referencing or storing host data units that are cached or are candidates for being cached in the solid-state memory. Further, the caching architecture maintains a segment control list that specifies associations between particular cache table entries and particular data segments. Such separation of activities related to the implementation of a caching policy from activities related to storing cached data and candidate data provides robustness and scalability while improving performance.

Abstract: A system and method for maintaining a mapping table in a data storage subsystem. A data storage subsystem supports multiple mapping tables including a plurality of entries. Each of the entries comprise a tuple including a key. A data storage controller is configured to encode each tuple in the mapping table using a variable length encoding. Additionally, the mapping table may be organized as a plurality of time ordered levels, with each level including one or more mapping table entries. Further, a particular encoding of a plurality of encodings for a given tuple may be selected based at least in part on a size of the given tuple as unencoded, a size of the given tuple as encoded, and a time to encode the given tuple.

Abstract: A system and method for efficiently performing user storage virtualization for data stored in a storage system including a plurality of solid-state storage devices. A data storage subsystem supports multiple mapping tables. Records within a mapping table are arranged in multiple levels. Each level stores pairs of a key value and a pointer value. The levels are sorted by time. New records are inserted in a created newest (youngest) level. No edits are performed in-place. All levels other than the youngest may be read only. The system may further include an overlay table which identifies those keys within the mapping table that are invalid.

Abstract: An embodiment of the present invention is a technique to enhance address translation performance. A register stores capability indicators to indicate capability supported by a circuit in a chipset for address translation of a guest physical address to a host physical address. A plurality of multi-level page tables is used for page walking in the address translation. Each of the page tables has page table entries. Each of the page table entries has at least an entry specifier corresponding to the capability indicated by the capability indicators.

Abstract: In a computing system including a processor and virtualization software including a guest operating system (OS) that utilizes a guest domain access control register (DACR) containing domain access information and guest page tables including first level page tables (L1 page tables) and second level page tables (L2 page tables), which guest page tables contain: (a) domain identifiers used to obtain domain access information from the guest DACR and (b) access permission information, wherein the domain access information and the access permission information are combined to provide an effective guest access permission, in accordance with one embodiment, a method for providing shadow page tables and processor DACR settings that virtualize processor memory protection includes: the virtualization software providing a shadow page table wherein: (a) domain identifiers in the shadow page table are used to identify domain access information in the processor DACR that are mapped from the domain access information in the

Abstract: Host page management assist functions are employed to manage storage of a pageable mode virtual environment. These functions enable storage to be managed by a processor of the environment absent intervention of a host of the environment. The functions include a resolve host page function; a pin function; and unpin functions.

Abstract: A hash table system having a first hash table and a second hash table is provided. The first hash table may be in-memory and the second hash table may be on-disk. Inserting an entry to the hash table system comprises inserting the entry into the first hash table, and, when the first hash table reaches a threshold load factor, flushing entries into the second hash table. Flushing the first hash table into the second hash table may comprise sequentially flushing the first hash table segments into corresponding second hash table segments. When looking up a key/value pair corresponding to a selected key in the hash table system, the system checks both the first and second hash tables for values corresponding to the selected key. The first and second hash tables may be divided into hash table segments and collision policies may be implemented within the hash table segments.

Abstract: A method for managing a memory apparatus including at least one non-volatile (NV) memory element includes: recording valid/invalid page position information of at least one block; and moving valid data contained in at least a valid page of the block according to the valid/invalid page position information; where the block is an erasing unit. For example, the valid/invalid page position information may contain relative position information of the valid data in the block. More particularly, the valid/invalid page position information may contain a plurality of bits, the ranking of each bit may represent a page address offset of each page within the block, and each bit may respectively indicate whether each page in the block is valid or invalid.

Abstract: A system for identifying an exiting process and removing traces and shadow page table pages corresponding to the process' page table pages. An accessed minimum virtual address is maintained corresponding to an address space. In one embodiment, whenever a page table entry corresponding to the accessed minimum virtual address changes from present to not present, the process is determined to be exiting and removal of corresponding trace and shadow page table pages is begun. In a second embodiment, consecutive present to not-present PTE transitions are tracked for guest page tables on a per address space basis. When at least two guest page tables each has at least four consecutive present to not-present PTE transitions, a next present to not-present PTE transition event in the address space leads to the corresponding guest page table trace being dropped and the shadow page table page being removed.

Abstract: A method for writing and reading data memory cells, comprising: defining in a first memory zone erasable data pages and programmable data blocks; and, in response to write commands of data, writing data in erased blocks of the first memory zone, and writing, in a second memory zone, metadata structures associated with data pages and comprising, for each data page, a wear counter containing a value representative of the number of times that the page has been erased.

Abstract: A method for managing utilization of a memory including a physical address space comprises mapping logical addresses of data objects to locations within the physical address space, and defining a plurality of address segments in the space as an active window. The method comprises allowing writes of data objects having logical addresses mapped to locations within the plurality of address segments in the active window. The method comprises, upon detection of a request to write a data object having a logical address mapped to a location outside the active window, updating the mapping so that the logical address maps to a selected location within the active window, and then allowing the write to the selected location. The method comprises maintaining access data indicating utilization of the plurality of address segments in the active window, and adding and removing address segments from the active window in response to the access data.

Abstract: Systems and methods are provided that utilize non-shared page tables to allow an accelerator device to share physical memory of a computer system that is managed by and operates under control of an operating system. The computer system can include a multi-core central processor unit. The accelerator device can be, for example, an isolated core processor device of the multi-core central processor unit that is sequestered for use independently of the operating system, or an external device that is communicatively coupled to the computer system.

Abstract: Various embodiments disclosed herein including systems and methods for improving allocation of computing resources in a virtual machine (VM) environment. Embodiments maintain data relating to how VM image data is stored in storage devices and loaded into volatile memory such as random access memory (RAM). The data is then used to identify common content in the volatile memory that can be shared across VM instances. In some embodiments, multiple VM instances can share at least a portion of a single common VM image loaded into a shared volatile memory.

Abstract: An arithmetic processing apparatus includes: a plurality of TLBs holding as entries a portion of a conversion table for conversion of virtual addresses into physical addresses that has been placed in a main memory unit; an entry registration determining unit that, while registering an entry output from the main memory unit in any one of a plurality of TLBs, determines whether an entry has already been registered in an area of a TLB as registration destination; and a relocation control unit that, when the entry registration determining unit determines that an entry has already been registered in the area of the TLB as registration destination, evicts the entry that has already been registered and registers evicted entry in other TLB.

Abstract: A storage system comprises a storage apparatus which includes a processor, storage disks, and a memory storing a page mapping table, a page mapping program, and a page-filename mapping program. A file system manages a file tree of files with filenames. The page mapping table specifies a relationship between data volumes in the storage apparatus and the storage disks and the file system, the data volumes each including pages, each page including segments, each segment including sectors. The file tree has for each storage apparatus a hierarchy of directories and files based on relationships among the data volumes, the pages, and the segments. The page mapping program and the page-filename mapping program are executable by the processor to specify, by page, a location of data contained in the I/O request by referring to the page mapping table and the file tree.

Abstract: A system and method for efficiently performing user storage virtualization for data stored in a storage system including a plurality of solid-state storage devices. A data storage subsystem supports multiple mapping tables. Records within a mapping table are arranged in multiple levels. Each level stores pairs of a key value and a pointer value. The levels are sorted by time. New records are inserted in a created newest (youngest) level. No edits are performed in-place. All levels other than the youngest may be read only. The system may further include an overlay table which identifies those keys within the mapping table that are invalid.

Abstract: The method of the present inventive concept is configured to utilize Operating System data structures related to memory-mapped binaries to reconstruct processes. These structures provide a system configured to facilitate the acquisition of data that traditional memory analysis tools fail to identify, including by providing a system configured to traverse a virtual address descriptor, determine a pointer to a control area, traverse a PPTE array, copy binary data identified in the PPTE array, generate markers to determine whether the binary data is compromised, and utilize the binary data to reconstruct a process.

Abstract: A dispersed storage network utilizes a virtual address space to store data. The dispersed storage network includes a dispersed storage device for receiving a request relating to a data object stored in the dispersed storage network and determining a virtual memory address assigned to the data object. The virtual memory address is within a virtual memory address range of the virtual address space that is allocated to a vault associated with a user of the data object. The virtual memory address is further assigned to a data slice of a plurality of data slices of the data object. The dispersed storage device uses the virtual memory address to determine an identifier of a storage unit within the dispersed storage network that has the data slice stored therein.

Abstract: One embodiment of the present invention sets forth a technique for performing a memory access request to compressed data within a virtually mapped memory system comprising an arbitrary number of partitions. A virtual address is mapped to a linear physical address, specified by a page table entry (PTE). The PTE is configured to store compression attributes, which are used to locate compression status for a corresponding physical memory page within a compression status bit cache. The compression status bit cache operates in conjunction with a compression status bit backing store. If compression status is available from the compression status bit cache, then the memory access request proceeds using the compression status. If the compression status bit cache misses, then the miss triggers a fill operation from the backing store. After the fill completes, memory access proceeds using the newly filled compression status information.

Abstract: According to one embodiment, upon request from an information processor, a semiconductor storage controller writes pieces of data in predetermined units into storage locations in which no data has been written in erased areas within a semiconductor chip's storage area. A third table and a second table which is a subset thereof include physical addresses each indicating a storage location of each of pieces of the data within the semiconductor chip. The first table includes either information specifying a second table entry or information specifying a third table entry. The semiconductor storage controller records the first and the second tables into a volatile memory or records the first table into a volatile memory and the third table into a nonvolatile memory.

Abstract: A translation lookaside buffer (TLB) is disclosed formed using RAM and synthesisable logic circuits. The TLB provides logic within the synthesisable logic for pairing down a number of memory locations that must be searched to find a translation to a physical address from a received virtual address. The logic provides a hashing circuit for hashing the received virtual address and uses the hashed virtual address to index the RAM to locate a line within the RAM that provides the translation.

Abstract: To reduce power consumption of a computer or the like, a nonvolatile memory divided into a plurality of segments is applied to main memory used for virtual storage management. Thus, power supply even to a segment having a physical address that is being used can be stopped. As a result, power consumption of the computer or the like performing virtual storage management can be reduced.

Abstract: According to an aspect of an embodiment, a system of using an extensible language to represent storage metadata includes a computer-readable storage medium and a processing device. The computer-readable storage medium may have stored thereon storage metadata. The processing device may be configured to write the storage metadata to the computer-readable storage medium in an extensible language format. The processing device may also be configured to manipulate the storage metadata in the extensible language format. The processing device may also be configured to transfer the storage metadata in the extensible language format.

Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.

Abstract: A memory access technique, in accordance with one embodiment of the present invention, includes coalescing mappings between virtual memory and physical memory when a contiguous plurality of virtual pages map to a contiguous plurality of physical pages. Any of the coalesced page table entries are sufficient to map all pages within the coalesced region. Accordingly, a memory subsystem can redirect one or more pending page table entry fetch requests to an appropriate coalesced page table entry.

Abstract: Some of the embodiments of the present disclosure provide a method for predicting, for a first virtual address, a first descriptor based at least in part on the one or more past descriptors associated with one or more past virtual addresses; and determining, for the first virtual address, a first physical address based at least in part on the predicted first descriptor. Other embodiments are also described and claimed.

Abstract: A method for writing and reading data memory cells, comprising: defining in a first memory zone erasable data pages and programmable data blocks; and, in response to write commands of data, writing data in erased blocks of the first memory zone, and writing, in a second memory zone, metadata structures associated with data pages and comprising, for each data page, a wear counter containing a value representative of the number of times that the page has been erased.

Abstract: Embodiments of the invention relate to hybrid address translation. An aspect of the invention includes receiving a first address, the first address referencing a location in a first address space. The computer searches a segment lookaside buffer (SLB) for a SLB entry corresponding to the first address; the SLB entry comprising a type field and an address field and determines whether a value of the type field in the SLB entry indicates a hashed page table (HPT) search or a radix tree search. Based on determining that the value of the type field indicates the HPT search, a HPT is searched to determine a second address, the second address comprising a translation of the first address into a second address space; and based on determining that the value of the type field indicates the radix tree search, a radix tree is searched to determine the second address.

Abstract: A method for writing and reading data in memory cells, comprises the steps of: defining a virtual memory, defining write commands and read commands of data (DT) in the virtual memory, providing a first nonvolatile physical memory zone (A1), providing a second nonvolatile physical memory zone (A2), and, in response to a write command of an initial data, searching for a first erased location in the first memory zone, writing the initial data (DT1a) in the first location (PB1(DPP0)), and writing, in the metadata (DSC0) an information (DS(PB1)) allowing the first location to be found and an information (LPA, DS(PB1)) forming a link between the first location and the location of the data in the virtual memory.

Abstract: Memory page management in a tiered memory system including a system that includes at least one page table for storing a plurality of entries, each entry associated with a page of memory and each entry including an address of the page and a memory tier of the page. The system also includes a control program configured for allocating pages associated with the entries to a software module, the allocated pages from at least two different memory tiers. The system further includes an agent of the control program capable of operating independently of the control program, the agent configured for receiving an authorization key to the allocated pages, and for migrating the allocated pages between the different memory tiers responsive to the authorization key.

Abstract: A system and method to manage a translation lookaside buffer (TLB) is disclosed. In a particular embodiment, a method of managing a first TLB includes in response to starting execution of a memory instruction, setting a first field associated with an entry of the first TLB to indicate use of the entry. The method also includes setting a second field to indicate that the entry in the first TLB matches a corresponding entry in a second TLB.

Abstract: A memory card system and related write method are disclosed. The method includes receiving a write request for a predetermined page; performing a write operation on a first log block that corresponds to a first data block including the page; receiving an update request for the page; and performing a write operation on a second log block that corresponds to the first data block. The memory card system includes: at least one non-volatile memory including a data block and a log block for updating the data block; and a memory controller controlling an operation of the non-volatile memory. During a write operation for a predetermined page, the controller controls writing of a first log block corresponding to a first data block including the predetermined page, and controls writing of a second log block during an update operation of the predetermined page.

Abstract: Systems and methods disclosed herein uniquely define each type of Fortran type descriptor within an executable file or shared library to allow for a rapid determination of how the dynamic type of one object (e.g., a first polymorphic entity) relates to that of another object (e.g., a second polymorphic entity) while allowing for the lazy loading of shared libraries. In one aspect, type descriptor definitions are instantiated (e.g., during compile-time) in each object file in which polymorphic entities are defined, each type descriptor definition is marked with a singleton attribute, and each group of common type descriptor definitions is associated with a COMDAT group to ensure that only a single copy of each type descriptor is defined in a corresponding executable file at a particular address in memory to which polymorphic entities can reference. Type descriptor addresses can be compared to determine dynamic type relations between polymorphic entities.

Abstract: A hash table system having a first hash table and a second hash table is provided. The first hash table may be in-memory and the second hash table may be on-disk. Inserting an entry to the hash table system comprises inserting the entry into the first hash table, and, when the first hash table reaches a threshold load factor, flushing entries into the second hash table. Flushing the first hash table into the second hash table may comprise sequentially flushing the first hash table segments into corresponding second hash table segments. When looking up a key/value pair corresponding to a selected key in the hash table system, the system checks both the first and second hash tables for values corresponding to the selected key. The first and second hash tables may be divided into hash table segments and collision policies may be implemented within the hash table segments.

Abstract: One embodiment of the present invention provides a system that accesses memory locations in an object-addressed memory system. During a memory access in the object-addressed memory system, the system receives an object identifier and an address. The system then uses the object identifier to identify a paged memory object associated with the memory access. Next, the system uses the address and a page table associated with the paged memory object to identify a memory page associated with the memory access. After determining the memory page, the system uses the address to access a memory location in the memory page.

Abstract: In accordance with one embodiment, additions to the standard computer microprocessor architecture hardware are disclosed comprising novel page table entry fields 015 062, special registers 021 022, instructions for modifying these fields 120 122 and registers 124 126, and hardware-implemented 038 runtime checks and operations involving these fields and registers. More specifically, in the above embodiment of a Hard Object system, there is additional meta-data 061 in each page table entry beyond what it commonly holds, and each time a data load or store is issued from the CPU, and the virtual address 032 translated to the physical address 034, the Hard Object system uses its additional PTE meta-data 061 to perform memory access checks additional to those done in current systems. Together with changes to software, these access checks can be arranged carefully to provide more fine-grain access control for data than do current systems.

Abstract: A memory protection unit (MPU) is configured to store a plurality of region descriptor entries, each region descriptor entry defining an address region of a memory, an attribute corresponding to the region, and an attribute override control corresponding to the attribute. A memory access request to a memory address is received and determined to be within a first address region defined by a first region descriptor entry and within a second address region defined by a second region descriptor entry. When the attribute override control of the first region descriptor entry indicates that override is to be performed, the value of the attribute of the first region descriptor entry is applied for the memory access. When the attribute override control of the second region descriptor entry indicates that override is to be performed, the value of the attribute of the second region descriptor entry is applied for the memory access.

Abstract: Disclosed is a computer implemented method to resume a process at an arrival machine that is in an identical state to a frozen process on a departure machine. The arrival machine receives checkpoint data for the process from the departure machine. It creates the process. It updates a page table, wherein the page table comprises a segment, page number, and offset corresponding to a page of the process available from a remote paging device, wherein the remote paging device is remote from the arrival machine. It resumes the process and responsively generates a page fault for the page. It looks up the page in the page table, responsive to the page fault. It determines whether the page is absent in the arrival machine. It transmits a page-in request to the departure machine, responsive to a determination that the page is absent. It receives the page from the departure machine.

Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.

Abstract: Provided are a program, a control method, and a control device by which an activation time can be shortened. In a computer system which is equipped with a Memory Management Unit (MMU), with respect to a table of the MMU, page table entries are rewritten so that page faults occur at each page necessary for operation of software. At the time of activating, stored memory images are read page by page for the page faults which occurred in the RAM to be accessed. By reading as described above, reading of unnecessary pages is not performed, and thus, the activation time can be shortened. The present invention can be applied to a personal computer and an electronic device provided with an embedded computer.

Abstract: A storage system comprises a storage apparatus which includes a processor, storage disks, and a memory storing a page mapping table, a page mapping program, and a page-filename mapping program. A file system manages a file tree of files with filenames. The page mapping table specifies a relationship between data volumes in the storage apparatus and the storage disks and the file system, the data volumes each including pages, each page including segments, each segment including sectors. The file tree has for each storage apparatus a hierarchy of directories and files based on relationships among the data volumes, the pages, and the segments. The page mapping program and the page-filename mapping program are executable by the processor to specify, by page, a location of data contained in the I/O request by referring to the page mapping table and the file tree.

Abstract: A logical page identity for a logical page containing data storage application data can be mapped to a physical storage page location in a storage where the data of the logical page are stored. The mapping as well as additional page data can be retained within a persistence layer accessible to the data storage application. The additional page data can include at least one of a size of the page and a next page linkage indicating a second page that follows the page in a page sequence of related pages. The retained mapping and additional page data can be retrieved from the persistence layer to initiate a page operation on the related pages, and the page operation can be executed on the related pages based on the retrieved mapping and additional page data. Related methods, systems, and articles of manufacture are also disclosed.

Abstract: A 3D object is represented by a descriptor, wherein a model of the 3D object is a 3D point cloud. A local support for each point p in the 3D point cloud is located, and reference x, y, and z axes are generated for the local support. A polar grid is applied according to the references x, y, and z axes a along an azimuth and a radial directions on an xy plane centered on the point p such that each patch on the grid is a bin for a 2D histogram, wherein the 2D histogram is a 2D matrix F on the grid and each coefficient of the 2D matrix F corresponds to the patch on the grid. For each grid location (k, l), an elevation value F(k, l) is estimated by interpolating the elevation values of the 3D points within the patches to produce the descriptor for the point p.