Abstract: The invention relates to a reproduction apparatus having a buffer for reducing the mean access time to an information carrier which has for example a discontinuous data structure or a relatively long access time. For writing sectors to the buffer and for finding sectors in the buffer, a control table with a number of place holders and three variables is provided, the place holders in each case pointing with an index to a subsequent place holder in an endless chain of place holders which is divided into three regions, in which a predetermined sector in the order in the respective region is identified by one of the variables. Even though only one row of place holders is provided, multiple access to a plurality of sectors written to the buffer is made possible with a low outlay by means of the control table, so that the number of slower accesses to the information carrier is reduced and the mean access time is shortened.

Abstract: Data is stored by utilizing a first operating mode and a second operating mode. In one embodiment, in the first operating mode, a continuous replication method is utilized to store data on a primary storage system and to generate a backup version of the data on a backup storage system. While data is being stored in accordance with the first operating mode, one or more activities performed by the data storage system(s) are monitored. As long as the monitored activity or activities display a first status, the first operating mode is maintained. If the monitored activity or activities display a change in status, the first operating mode is suspended, and data is stored pursuant to the second operating mode. In one embodiment, in the second operating mode, a delta replication method is utilized to store data on the primary storage system and to back up the data on the backup storage system.

Abstract: In certain embodiments, a plurality of nodes of a hierarchical data structure are generated, wherein each node of the hierarchical data structure represents a set of at least one locked logical block. A request is received to exclusively access a set of at least one logical block. A determination is made, by traversing at least one node of the hierarchical data structure, whether the set of at least one logical block overlaps sets of at least one locked logical block represented by the plurality of nodes of the hierarchical data structure.

Abstract: A sharing mechanism is herein disclosed for multiple logical processors using a translation lookaside buffer (TLB) to translate virtual addresses, for example into physical addresses. The mechanism supports sharing of TLB entries among logical processors, which may access address spaces in common. The mechanism further supports private TLB entries among logical processors, which for example, may each access a different physical address through identical virtual addresses. The sharing mechanism provides for installation and updating of TLB entries as private entries or as shared entries transparently, without requiring special operating system support or modifications. Through use of the disclosed sharing mechanism, fast and efficient virtual address translation is provided without requiring more expensive functional redundancy.

Abstract: An address translation unit generates a physical address for access to a memory from a virtual address using either a translation lookaside buffer or a segmentation buffer. If the virtual address falls within a predetermined range, the address translation unit will use the segmentation buffer to generate the physical address. Upon generation of the physical address, the memory will either receive data from or provide data to a processor in accordance with the instructions being processed by the processor.

Abstract: A sharing mechanism is herein disclosed for multiple logical processors using a translation lookaside buffer (TLB) to translate virtual addresses into physical addresses. The mechanism supports sharing of TLB entries among logical processors, which may access address spaces in common. The mechanism further supports private TLB entries among logical processors, which may each access a different physical address through identical virtual addresses. The sharing mechanism provides for installation and updating of TLB entries as private entries or as shared entries transparently, without requiring special operating system support or modifications. Sharability of virtual address translations by logical processors may be determined by comparing page table physical base addresses of the logic processors. Using the disclosed sharing mechanism, fast and efficient virtual address translation is provided without requiring more expensive functional redundancy.

Abstract: A method and apparatus for efficiently storing an effective address (EA) in an effective to real address translation (ERAT) table supporting multiple page sizes by adding PSI fields, based on the number of unique page sizes supported, to each ERAT entry and using one ERAT entry to store an EA for a memory page, regardless of page size, by setting the PSI fields to indicate the page size.

Abstract: A predetermined number of erasable blocks positioned at a start of a volume area in a semiconductor memory card are provided so as to include volume management information. A user area following the volume management information includes a plurality of clusters. A data length NOM of an area from a master boot record & partition table sector to a partition boot sector is determined so that the plurality of clusters in the user area are not arranged so as to straddle erasable block boundaries. Since cluster boundaries and erasable block boundaries in the user area are aligned, there is no need to perform wasteful processing in which two erasable blocks are erased to rewrite one cluster.

Abstract: A data processing system includes at least one system processor, chipset core logic, main memory to store computer software and data including operating system software, and a graphics address remapping table (GART). The chipset logic operates on first-sized real memory pages, while the operating system operates on larger, second-sized virtual memory pages. In an embodiment GART driver software maps each virtual page to Z continuous or non-contiguous real pages by filling up the GART with Z entries per virtual page, where Z is the rounded integer number of first-sized pages per second-sized page. In another embodiment, an address translation function converts a target address, corresponding to an address within a virtual page, issuing from a processor into a second address, corresponding to a base address of a real page in main memory. Also described are an integrated circuit and a computer-readable medium to map memory pages of disparate sizes.

Abstract: In a computer system, an architecture is disclosed for optimizing aspects of data movement operations by performing functions such as memory allocation and notification on hardware rather than software. In this environment, the claimed invention is a method and apparatus for ensuring the integrity of data movement operations from virtual memory. The invention monitors and detects Translation Lookaside Buffer (“TLB”) purges, a hardware-based operation whose occurrence signals that virtual-to-physical mapping has changed. Responsive to detection of a TLB purge during the set up or execution of a data movement operation, the claimed invention aborts the operation, and then enqueues corresponding completion status information to notify processors of the event.

Abstract: A new memory tuple is described that creates both a handle as well as a reference to an item within the handle. The reference is created using an offset value that defines the physical offset of the data within the memory block. Thereafter, if references are passed in terms of their offset value, this value will be the same in any copy of the handle regardless of the machine. In a distributed computing environment, equivalence between handles is established in a single transaction between two communicating machines. Thereafter, the two machines can communicate about specific handle contents simply by using offsets.

Abstract: One embodiment of the present invention provides a method of memory management. Within the present embodiment, a page register along with supporting logic allows a mode to be selected by a processor at the same time it specifies a particular memory page. The selected mode defines what the subsequent use of the specified memory page will be. For example, this method may decrease overhead when moving between different memory pages by providing a mode that automatically returns to a previous page after a specified page has been accessed.

Abstract: One or more mapping data structures are maintained containing mappings of logical flash memory addresses to physical flash memory addresses. Each mapping data structure has a predetermined capacity of mappings. A master data structure is also maintained containing a pointer to each of the one or more mapping data structures. Additional mapping data structures are allocated as needed to provide capacity for additional mappings. Each time a mapping data structure is allocated or de-allocated the pointers in the master data structure are changed accordingly.

Abstract: A system, method and apparatus for providing and utilizing a storage cache descriptor by a storage controller are disclosed which provide the ability to effectively balance the size of storage controller cache blocks and the amount of data transferred in anticipation of requests, such as requests by a host. The apparatus may include a storage device, a storage controller and a cache. The storage controller stores electronic data in the cache by including a cache descriptor that defines data contained in a cache block, the cache descriptor including at least one field describing a device block of the cache block. The at least one field may include, by way of example, at least one of a present field, modified field, pinned field and write-in progress field.

Abstract: An address translation manager creates a set of chained tables that may be allocated in non-contiguous physical memory, and that may be dynamically resized as needed. The chained tables comprise one or more tables that each correspond to a logical partition, with each table including a pointer to a table corresponding to a virtual connection in the logical partition. The chained tables are managed by the address translation manager, which uses the system memory manager to dynamically allocate and free memory for a chained table as needed.

Abstract: A sharing mechanism is herein disclosed for multiple logical processors using a translation lookaside buffer (TLB) to translate virtual addresses, for example into physical addresses. The mechanism supports sharing of TLB entries among logical processors, which may access address spaces in common. The mechanism further supports private TLB entries among logical processors, which for example, may each access a different physical address through identical virtual addresses. The sharing mechanism provides for installation and updating of TLB entries as private entries or as shared entries transparently, without requiring special operating system support or modifications. Through use of the disclosed sharing mechanism, fast and efficient virtual address translation is provided without requiring more expensive functional redundancy.

Abstract: A logical partition (LPAR) computer system for managing partition configuration data is disclosed, which includes a nonvolatile memory, and a plurality of logical partitions, each running independently from the other logical partitions. The system also includes a console coupled to the computer system for accepting logical partition configuration data input by an operator. The configuration data entered by the operator specifies the processors, I/O, and memory allocated to each logical partition defined for the system. The system further includes a set of tables maintained in the nonvolatile memory for storing the logical partition configuration data, such that the logical partition configuration data is persistent across system power cycles.

Abstract: Systems and methods for providing on-demand memory management. In response to a mapping request from a device driver or other program, a first portion of the memory is mapped to one or more virtual addresses in a first region of a virtual memory space so that it can be directly accessed by the CPU. In response to an unmapping request the first portion of the memory is unmapped. Mapping and unmapping requests may be made at any time.

Abstract: A translation look-aside buffer (TLB) capable of reducing power consumption and improving performance of a memory is provided. The fully-associative TLB which converts a virtual address into a physical address, comprises a first TLB having a plurality of banks; a second TLB having a plurality of entries, each of which having one virtual page number and 2N physical page numbers, wherein N is a natural number; and a selection circuit for outputting an output signal of the first TLB to the second TLB in response to a selection signal, wherein each bank of the first TLB has a plurality of entries, each of which has one virtual page number and one physical page number. The size of a page indicated by a virtual page number of the first TLB is different from the size of a page indicated by a virtual page number of the second TLB.

Abstract: A method, apparatus and computer program product are provided for dynamically minimizing translation lookaside buffer (TLB) entries across contiguous memory. A page table with page table entries (PTEs) is provided for mapping multiple sized pages from a virtual address space to a physical address space. Each of the multiple sized pages is a multiple of a base page size. A region of memory having a starting address and a length is divided into a minimum number of natural blocks for the memory region. Once the region of memory is divided into the natural blocks, page table entries (PTEs) are assigned to map each natural block. Multiple identical PTEs are required to map each natural block greater than a base page size. Only one TLB entry is used to map each natural block.

Abstract: Memory and processing required for managing virtual memory segments is reduced by overloading the existing page table entries in a virtual memory page table to encode virtual memory segmentation data. Therefore, no additional data structures are required for virtual memory segment management. Virtual memory segmentation information is stored in the actual page table entries, using bits that are reserved as unused for the given computer architecture to identify the virtual memory segment management information.

Abstract: A virtual mode virtual memory manager method and apparatus are provided. Mechanisms are provided for allowing a virtual memory manager to operate in virtual mode utilizing virtual addresses for all of its own data structures, allowing for physical discontinuity of the physical memory backing those data structures. First order virtual memory manager metadata is included for resolving system wide virtual memory page faults. Second order virtual memory manager metadata is provided to resolve faults on the first order virtual memory manager metadata. The second order virtual memory manager metadata is associated with pinned entries in a page table and thus, faults on the second order virtual memory manager metadata cannot occur.

Abstract: A data processing system includes at least one system processor, chipset core logic, main memory to store computer software and data including operating system software, and a graphics address remapping table (GART). The chipset logic operates on first-sized real memory pages, while the operating system operates on larger, second-sized virtual memory pages. In an embodiment GART driver software maps each virtual page to Z continuous or non-contiguous real pages by filling up the GART with Z entries per virtual page, where Z is the rounded integer number of first-sized pages per second-sized page. In another embodiment, an address translation function converts a target address, corresponding to an address within a virtual page, issuing from a processor into a second address, corresponding to a base address of a real page in main memory. Also described are an integrated circuit and a computer-readable medium to map memory pages of disparate sizes.

Abstract: A method and apparatus for managing a dynamic alias page table are provided. With the apparatus and method, alias page table entries are added to an alias page table dynamically by determining if the alias page table has space for the entry and, if so, the entry describing the virtual address to physical address mapping is added to the alias page table and a successful completion is returned to the virtual memory manager. If the alias page table does not have space for the entry, a new page is used to map the next virtual page of the alias page table. This page must be marked as a fixed page if it not so marked already. This page is pinned in the software page frame table, and the hardware page table entry for this page is also pinned.

Abstract: A memory device with a nonvolatile memory and RAM for accessing the nonvolatile memory is generally provided with a table to convert a logical address to a physical address, however, in the invention, the table is divided to a first table on RAM and a second table on the nonvolatile memory. The first table converts specific bits of the logical address to a first physical address indicating a location of the second table. The second table converts the other bits of the logical address to a physical address of a representative page of pages contained in a storage area corresponding to the logical address. A unit operable to access data (a writing unit operable to, a reading unit operable to, and an erasing unit operable to) reaches a target physical address based on the logical address. Such configuration can reduce the capacity of each conversion table.

Abstract: One embodiment of the present invention provides a system that facilitates avoiding collisions between cache lines containing objects and cache lines containing corresponding object table entries. During operation, the system receives an object identifier for an object, wherein the object identifier is used to address the object in an object-addressed memory hierarchy. The system then applies a mapping function to the object identifier to compute an address for a corresponding object table entry associated with the object, wherein the mapping function ensures that a cache line containing the object table entry does not collide with a cache line containing the object.

Abstract: A method and apparatus for an apparatus and method for reduction of power consumption in OS that use flat segmentation memory model are described. In one embodiment, the method includes monitoring a segment register to detect a segment register update operation. Once the segment register update operation is detected, a code/data segment contained within the segment register is identified as one of a segmented code/data segment and a flat code/data segment. Once detected, the segment register is updated according to whether the segment is flat or segmented. Accordingly, when a segment register read is performed, one or more updated bits within the segment register are used to identify the code/data read from the segment register as either flat or segmented.

Abstract: A processor having a limited amount of local memory for storing code and/or data utilizes a program stored in external memory. The program stored in external memory is configured into blocks which can be loaded individually into the local memory for execution. Queuing the individual blocks of code allows the program to be executed by the processor and also facilitates loading of the subsequent code to be executed. A semaphore system can be utilized to indicate which blocks of local memory are available/unavailable. The system can support the interaction of multiple independent programs in external memory.

Abstract: A data processing device is used with peripheral devices having addressees and differing communication response periods. The data processing device includes a digital processor adapted for selecting different ones of the peripheral devices by asserting addresses of each selected peripheral device. Addressable programmable registers hold wait state values representative of distinct numbers of wait states corresponding to different address ranges. Circuitry responsive to an asserted address to the peripheral devices asserted by the digital processor generates the number of wait states represented by the value held in one of the addressable programmable registers corresponding to the one of the address ranges in which the asserted address occurs, thereby accommodating the differing communication response periods of the peripheral devices.

Abstract: A method and system for attached processing units accessing a shared memory in an SMT system. In one embodiment, a system comprises a shared memory. The system further comprises a plurality of processing elements coupled to the shared memory. Each of the plurality of processing elements comprises a processing unit, a direct memory access controller and a plurality of attached processing units. Each direct memory access controller comprises an address translation mechanism thereby enabling each associated attached processing unit to access the shared memory in a restricted manner without an address translation mechanism. Each attached processing unit is configured to issue a request to an associated direct memory access controller to access the shared memory specifying a range of addresses to be accessed as virtual addresses. The associated direct memory access controller is configured to translate the range of virtual addresses into an associated range of physical addresses.

Abstract: A data structure and method implemented in accordance with the invention enable reading a cache to get a type information corresponding to an address of interest more reliably than with volatile read operations and faster than scanning tables or walking along linked lists. Reliably reading the cache enabled by the invention does not require locks, although, the type information and the address together require more bits than those present in one machine word.

Abstract: A processor is configured to operate in a modes which utilize segmentation and which do not utilize segmentation. The processor includes circuitry which is configured to detect and respond to mode and state changes. The circuitry is configured to determine whether a segmentation state of the processor changes in response to execution of a control transfer operation. If the segmentation state does not change as a result of the transfer instruction, execution of instructions may continue sequentially and a corresponding first check performed. However, if the segmentation state does change as a result of the transfer instruction, a flush of the pipeline is initiated prior to performing a corresponding second check. When a first mode of operation is detected a limit check may be performed, while a canonical check may performed when a second mode of operation is detected. A special register is defined which is configured to indicate changes in segmentation state subsequent to a control transfer operations.

Abstract: A method and apparatus for input/output virtual address translation and validation assigns a range of memory to a device driver for its exclusive use. The device driver invokes system functionality for receiving a logical address and outputting a physical address having a length greater than the logical address. Another feature of the invention is a computer system providing input/output virtual address translation and validation for at least one peripheral device. In one embodiment, the computer system includes a scatter-gather table, an input/output virtual address cache memory associated with at least one peripheral device, and at least one device driver. In a further embodiment, the input/output virtual address cache memory includes an address validation cache and an address translation cache.

Abstract: A computer has a hardware memory arranged into portions that are separately addressable using first identifiers, which are represented using a first number of address bits. A subsystem that is able to address a second space of the hardware memory using second identifiers initiates I/O requests directed to a device that is able to address a different, first memory space using first identifiers, which are represented using a second number of address bits. The second identifiers are initially mapped into the second memory space, but for any I/O request that meets a remapping criterion, the corresponding second identifier is remapped to one of the first identifiers that identifies a portion of the memory in the first memory space. The second space is different from the first space and the second number of address bits is greater less than the first number of address bits.

Abstract: A behavioral memory mechanism for performing address mappings within a data processing system is disclosed. The data processing system includes a processor, a real memory, a address converter, and an address translator. The real memory has multiple real address locations, and each of the real address locations is associated with a corresponding one of many virtual address locations. The virtual address locations are divided into two non-overlapping regions, namely, an architecturally visible virtual memory region and a behavioral virtual memory region. The address converter converts an effective address to an architecturally visible virtual address and a behavioral virtual address. The architecturally visible virtual address is utilized to access the architecturally visible virtual memory region of the virtual memory and the behavioral virtual address is utilized to access the behavioral virtual memory region of the virtual memory.

Abstract: A data processing system providing high performance two-dimensional and three-dimensional graphics includes at least one system processor, chipset core logic, a graphics processor, main memory storing computer software and data including operating system software, and a graphics address remapping table (GART). The chipset logic operates on first-sized memory pages, while the operating system operates on larger, second-sized memory pages. In one embodiment GART driver software maps each second-sized page to Z first-sized pages by filling up the GART with Z entries per second-sized page, where Z is the rounded integer number of first-sized pages per second-sized page. In another embodiment, an address translation function converts a first page number, corresponding to a first-sized page, issuing from a system processor into a second page number, corresponding to a second-sized page, and a page offset within the second-sized page.

Abstract: A coherency resolution technique enables efficient resolution of data coherency for packet data associated with a service queue of an intermediate network node. The packet data is enqueued on a write buffer prior to being stored on an external packet memory of a packet memory system. The packet data may be interspersed among other packets of data from different service queues, wherein the packets are of differing sizes. In response to a read request for the packet data, a coherency operation is performed by coherency resolution logic on the data in the write buffer to determine if any of its enqueued data can be used to service the request.

Abstract: A method and apparatus for breaking complex X86 segment operations and segmented memory addressing into explicit sub-operations so that they may be exposed to compiler or translator-based optimizations. A method includes providing a first segment selector for deriving a linear address of a segment descriptor in a first descriptor table and providing a second segment selector for deriving a linear address of a segment descriptor in a second descriptor table. The method also includes attempting an access of the first descriptor table to derive a segment descriptor, and if the access of the first descriptor table fails, attempting an access of the second descriptor table to derive a segment descriptor. The method also includes storing a derived segment descriptor from a successful attempted access in a descriptor register.

Abstract: A predetermined number of erasable blocks positioned at a start of a volume area in a semiconductor memory card are provided so as to include volume management information. A user area following the volume management information includes a plurality of clusters. A data length NOM of an area from a master boot record & partition table sector to a partition boot sector is determined so that the plurality of clusters in the user area are not arranged so as to straddle erasable block boundaries. Since cluster boundaries and erasable block boundaries in the user area are aligned, there is no need to perform wasteful processing in which two erasable blocks are erased to rewrite one cluster.

Abstract: A predetermined number of erasable blocks positioned at a start of a volume area in a semiconductor memory card are provided so as to include volume management information. A user area following the volume management information includes a plurality of clusters. A data length NOM of an area from a master boot record & partition table sector to a partition boot sector is determined so that the plurality of clusters in the user area are not arranged so as to straddle erasable block boundaries. Since cluster boundaries and erasable block boundaries in the user area are aligned, there is no need to perform wasteful processing in which two erasable blocks are erased to rewrite one cluster.

Abstract: A predetermined number of erasable blocks positioned at a start of a volume area in a semiconductor memory card are provided so as to include volume management information. A user area following the volume management information includes a plurality of clusters. A data length NOM of an area from a master boot record & partition table sector to a partition boot sector is determined so that the plurality of clusters in the user area are not arranged so as to straddle erasable block boundaries. Since cluster boundaries and erasable block boundaries in the user area are aligned, there is no need to perform wasteful processing in which two erasable blocks are erased to rewrite one cluster.

Abstract: A method is provided to allow a system administrator of a utility storage server to provision virtual volumes several times larger than the amount of physical storage within the storage server. A virtual volume is a virtual representation of multiple disks as a single large volume to a host or an application. In one embodiment, a virtual volume comprises an exception list containing the set of differences from dummy base volume consisting of all zeros. This exception list can be made up of address tables that map virtual volume pages to logical disk pages. As storage demand grows, additional storage is allocated for the address tables and the data pages from separate pools of storage. If any of the pools runs low, more logical disk regions are allocated to that pool.

Abstract: A predetermined number of erasable blocks positioned at a start of a volume area in a semiconductor memory card are provided so as to include volume management information. A user area following the volume management information includes a plurality of clusters. A data length NOM of an area from a master boot record & partition table sector to a partition boot sector is determined so that the plurality of clusters in the user area are not arranged so as to straddle erasable block boundaries. Since cluster boundaries and erasable block boundaries in the user area are aligned, there is no need to perform wasteful processing in which two erasable blocks are erased to rewrite one cluster.

Abstract: Disclosed is a disk system for controlling divided areas of a cache memory. Identification information that denotes whether data to be accessed is user data or meta data is added to each I/O command issued from a CPU. A disk controller, when receiving such an I/O command, selects a target virtual area from among a plurality of virtual areas set in the cache memory according to the identification information. When new data is to be stored in the cache memory upon the execution of the I/O command, the disk controller records the number of the selected virtual area in the cache memory in correspondence with the new data. A cache data replacement is executed independently for each cache area, thereby a predetermined upper limit size of each cache memory area can be kept.

Abstract: A method and apparatus for managing shared virtual storage in an information handling system in which each of a plurality of processes managed by an operating system has a virtual address space comprising a range of virtual addresses that are mapped to a corresponding set of real addresses representing addresses in real storage. The virtual address spaces are 64-bit address spaces requiring up to five levels of dynamic address translation (DAT) tables to map their virtual addresses to real addresses. One or more shared ranges of virtual addresses are defined that are mapped for each of a plurality of virtual address spaces to a common set of real addresses. The operating system manages these shared ranges using a system-level DAT table that reference a shared set of DAT tables used by the sharing address spaces for address translation, but is not attached to the hardware address translation facilities or used for address translation.

Abstract: A processor supports several operating modes. In at least one of the operating modes, a segmented address space is used. In at least one other operating mode, an unsegmented address space is used. In the unsegmented address space, a canonical check applies to addresses. In the segmented address space, a segment limit check applies. In some cases, both a segment limit check and a canonical check applies dependent on the segment used (e.g. either user or table segments). An exception circuit selects one or more of the canonical check result(s) and the segment limit check result to generate an exception indication. The selection is dependent on the operating mode and the segment of the data reference. The processor may also perform selective truncation of addresses based on the operating mode and the segment.

Abstract: A processor, apparatus and method for storing segment descriptors of different sizes in a segment descriptor table are disclosed. Smaller segment descriptors may be segment descriptors similar to the x86 architecture definition, and larger segment descriptors may be used to provide virtual addresses (e.g. base addresses or offsets) having more the 32 bits. By providing a segment descriptor table that stores different sized segment descriptors, maintaining multiple segment descriptor tables for different operating modes may be avoidable while providing support for segment descriptors having addresses greater than 32 bits. In one embodiment, the larger segment descriptors may be twice the size of the smaller segment descriptors. The segment descriptor table may comprise entries, each capable of storing the smaller segment descriptor, and a larger segment descriptor may occupy two entries of the table.

Abstract: A method of accessing a plurality of memories and a plurality of input/output modules includes providing at least one map table, including a plurality of entries. Each entry includes an entry type identifier and a plurality of entry items. A first logical address including a plurality of address bits is received. An entry in the at least one map table is identified based on a first set of the address bits. A type of the identified entry is determined based on the entry type identifier of the identified entry. An entry item in the identified entry is identified based on a second set of the address bits if the entry type identifier indicates an input/output type entry. An entry item in the identified entry is identified based on a third set of the address bits if the entry type identifier indicates a memory type entry.

Abstract: A system for optimizing data storage and retrieval by an audio/video system using a number of different tables is disclosed. According to one aspect of the system, the system includes two different types of hierarchical file allocation tables (HFATs), a contiguous space table, a track table and a list table. The two different types of HFATs are a 0th order HFAT and a 1st order HFAT. Each of the two types of HFATs contains a number of entries. Each 0th order HFAT entry corresponds to a specific disk block and each 1st order HFAT entry corresponds to a specific subdivision within a subdivided disk block. A 0th order HFAT entry and an 1st order HFAT entry is linkable to one another to allow disk blocks and subdivisions which make up a file to be identified. The contiguous space table is used to store information relating to the location and availability of contiguous spaces or disk blocks. The track table contains a number of records. Each record, in turn, contains various track, HMSF and descriptor information.

Abstract: Memory is managed by controlling the expansion of memory contents, especially in those computing environments in which the memory contents are compressed. Control is provided by imposing some restrictions to memory references outside a specified subset of the memory contents, and by controlling the transfer of items into the subset. In one example, the transfer of items into the subset is based on a function of parameters, including an estimate of the amount of free space in the memory.