Resolving Conflict, Coherency, Or Synonym Problem Patents (Class 711/210)
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Patent number: 7073047Abstract: A control chip and operating method for accelerating memory access that can be applied to a memory system whose memory read command actual address is read from a system bus in a number of synchronous transmissions. On receiving a first section read address, the control chip operates to compare the first section read address with an identical bit portion of the write address of the memory-write commands inside a memory-write command queue. If the comparison indicates some difference, permission for executing the memory read command is granted. If the comparison indicates the presence of identical bits, a second section read address is received and compared with an identical bit portion of the write address of the memory-write commands inside a memory-write command queue. If the comparison indicates some difference, permission for executing the memory read command is granted.Type: GrantFiled: July 17, 2002Date of Patent: July 4, 2006Assignee: VIA Technologies, Inc.Inventors: Kuang-Kai Kuo, Kuo-Ping Liu
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Patent number: 7020761Abstract: Processing restrictions of a computing environment are filtered and blocked, in certain circumstances, such that processing continues despite the restrictions. One restriction includes an indication that address translation is prohibited, in response to a buffer miss. When a processing unit of the computing environment is met with this restriction, it performs a comparison of page indices, which indicates whether the address translation can continue. If address translation can continue, the restriction is ignored. The processing unit includes a processor or a pageable entity, as examples.Type: GrantFiled: May 12, 2003Date of Patent: March 28, 2006Assignee: International Business Machines CorporationInventors: Timothy J. Siegel, Bruce A. Wagar, Ute Gaertner, Lisa C. Heller, Erwin F. Pfeffer
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Patent number: 6993638Abstract: If a base register value, an index register value and a displacement value are given in the case of operand access, these values are inputted to an arithmetic unit to generate a correctly calculated logical address. Simultaneously, a logical address predicting unit predicts a logical address. An absolute address is predicted based on the predicted logical address by using an absolute address history table. Access to a cache memory (LBS) based on an absolute address is made using the predicted absolute address to obtain cache data. Then, the arithmetic unit calculates a correct absolute address using the correctly calculated address using a TLB and checks if the correct absolute address coincides with the predicted absolute address so as to perform result confirmation of the cache data read from the LBS. In the case of instruction fetch, similar processing is carried out except that the calculation of a logical address is not performed.Type: GrantFiled: June 7, 2002Date of Patent: January 31, 2006Assignee: Fujitsu LimitedInventors: Masaki Ukai, Aiichiro Inoue
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Patent number: 6983347Abstract: A method and system are disclosed for managing stored soft state information, such as the contents of cache memory and address translation information that are non-critical for executing a process within a processor. The soft states of idle processes are stored in system memory in virtual caches. Cache coherency of the soft states is maintained by snooping kill-type operations against the virtual caches in system memory.Type: GrantFiled: December 5, 2002Date of Patent: January 3, 2006Assignee: International Business Machines CorporationInventors: Ravi Kumar Arimilli, Robert Alan Cargnoni, Guy Lynn Guthrie, William John Starke
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Patent number: 6976129Abstract: A method and apparatus for a mechanism for handling i/o transactions with known transaction length to coherent memory in a cache coherent multi-node architecture is described. In one embodiment, the invention is a method. The method includes receiving a request for a current copy of a data line. The method further includes finding the data line within a cache-coherent multi-node system. The method also includes copying the data line without disturbing a state associated with the data line. The method also includes providing a copy of the data line in response to the request. The method also includes determining if the data line is a last data line of a transaction based on a known transaction length of the transaction.Type: GrantFiled: September 30, 2002Date of Patent: December 13, 2005Assignee: Intel CorporationInventors: Kenneth C. Creta, Manoj Khare, Lily P. Looi, Akhilesh Kumar
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Patent number: 6963964Abstract: In a computer processor, multiple partially translated real addresses for a pipelined operation are compared with the real addresses of one or more other operations in the pipeline to detect an address conflict, without waiting for the address translation mechanism to fully translate the real address. Preferably, if a match is found, it is assumed that an address conflict exists, and the pipeline is stalled one or more cycles to maintain data integrity in the event of an actual address conflict. Preferably, the CPU has caches which are addressed using real addresses, and an N-way translation lookaside buffer (TLB) for determining the high-order portion of a real address. Each of the N real address portions in the TLB is compared with other operations in the pipeline, before determining which is the correct real address portion.Type: GrantFiled: March 14, 2002Date of Patent: November 8, 2005Assignee: International Business Machines CorporationInventor: David Arnold Luick
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Patent number: 6963823Abstract: Design spaces for systems, including hierarchical systems, are programmatically validity filtered and quality filtered to produce validity sets and quality sets, reducing the number of designs to be evaluated in selecting a system design for a particular application. Validity filters and quality filters are applied to both system designs and component designs. Component validity sets are combined as Cartesian products to form system validity sets that can be further validity filtered. Validity filters are defined by validity predicates that are functions of discrete system parameters and that evaluate as TRUE for potentially valid systems. For some hierarchical systems, the system validity predicate is a product of component validity predicates. Quality filters use an evaluation metric produced by an evaluation function that permits comparing designs and preparing a quality set of selected designs. In some cases, the quality set is a Pareto set or an approximation thereof.Type: GrantFiled: February 10, 2000Date of Patent: November 8, 2005Assignee: Hewlett-Packard Development Company, L.P.Inventors: Santosh G. Abraham, Robert S. Schreiber, B. Ramakrishna Rau
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Patent number: 6963962Abstract: A memory system for operation with a processor, such as a digital signal processor, includes a high speed pipelined memory, a store buffer for holding store access requests from the processor, a load buffer for holding load access requests from the processor, and a memory control unit for processing access requests from the processor, from the store buffer and from the load buffer. The memory control unit may include prioritization logic for selecting access requests in accordance with a priority scheme and bank conflict logic for detecting and handling conflicts between access requests. The pipelined memory may be configured to output two load results per clock cycle at very high speed.Type: GrantFiled: April 11, 2002Date of Patent: November 8, 2005Assignee: Analog Devices, Inc.Inventors: Hebbalalu S. Ramagopal, Murali S. Chinnakonda, Thang M. Tran
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Patent number: 6934827Abstract: One embodiment of the present invention provides a system that facilitates avoiding collisions between cache lines containing objects and cache lines containing corresponding object table entries. During operation, the system receives an object identifier for an object, wherein the object identifier is used to address the object in an object-addressed memory hierarchy. The system then applies a mapping function to the object identifier to compute an address for a corresponding object table entry associated with the object, wherein the mapping function ensures that a cache line containing the object table entry does not collide with a cache line containing the object.Type: GrantFiled: March 13, 2003Date of Patent: August 23, 2005Assignee: Sun Microsystems, Inc.Inventors: Gregory M. Wright, Mario I. Wolczko, Matthew L. Seidl
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Patent number: 6925464Abstract: A method and system for performing inserts and lookups in fully associative sections of memory is provided. The system includes a differentiating register to store information that differentiates entries in a section of a memory, logic coupled to the register to determine which entry is most likely to match a search key, and a comparator to compare the search key to the entry determined most likely to match. For each pair of entries in the section of memory, a differentiating bit position, reference value, and pointer are determined and stored to differentiate the entries. A search key can be compared to the differentiating values to determine which entry is most likely to match. Then, the entry determined most likely to match is retrieved from memory and compared to the search key.Type: GrantFiled: June 13, 2002Date of Patent: August 2, 2005Assignee: Intel CorporationInventor: Sreenath Kurupati
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Patent number: 6925636Abstract: A method, apparatus and article of manufacture for performing alias refinement is disclosed. Initially, a determination is made as to whether a load of an address exists for a variable in an intermediate representation of the source code. If a load of the address exists for the variable, a further determination is made whether each use of the address is for an indirect reference of the variable. If a particular use of the address is for an indirect reference of the variable, the indirect reference is replaced with a direct reference in the intermediate representation. If all uses of the address are for an indirect reference of the variable, the variable is removed from an alias set used with the intermediate representation.Type: GrantFiled: March 20, 2001Date of Patent: August 2, 2005Assignee: International Business Machines CorporationInventors: Patrick Todd Haugen, Tim Clayton Muehe
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Patent number: 6907505Abstract: A hybrid LUN copy operation that ultimately produces a full LUN copy, but involves a transient snapshot-copy-like intermediate stage. In one embodiment, a statically pre-allocated copy LUN is initialized with references pointing back to the primary LUN. Over time, the sectors, blocks, or other data-storage units of the primary LUN are copied to the copy LUN, so that, in the end, a full copy LUN in completed. In a second, alternative embodiment, both the primary LUN and copy LUN are READ and WRITE accessible immediately following the nearly instantaneous initialization of the copy LUN. In both embodiments, the copy LUN may be statically allocated. The immediate-full-LUN-copy operations provided by the present invention further enable rotatable copy-LUN groups, each copy LUN within a copy-LUN group representing a full, robust copy LUN.Type: GrantFiled: July 31, 2002Date of Patent: June 14, 2005Assignee: Hewlett-Packard Development Company, L.P.Inventors: Robert A. Cochran, Titus E. Davis
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Patent number: 6895492Abstract: A higher TLB that stores TLB data required for translating a virtual address into a physical address. A higher address translator performs address translation based on the TLB data according to an access. If address translation is not possible, the higher address translator requests a lower address translator to carry out the address translation. The lower address translator performs address translation based on a lower TLB. A shift register outputs a write prohibit signal to prohibit writing of the TLB data to the higher TLB, when write data that is the same as the write data has already been written in the higher TLB.Type: GrantFiled: December 30, 2002Date of Patent: May 17, 2005Assignee: Fujitsu LimitedInventor: Takuma Chiba
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Patent number: 6854048Abstract: Mechanisms and techniques operate in a computerized device to enable or disable speculative execution of instructions such as load instructions on one or more processors in the computerized device. The mechanisms and techniques can execute a set of instructions on a processor in the computerized device and can detect a value of a speculation indicator. If the value of the speculation indicator indicates that speculative execution of load instructions is allowed in the computerized device, the mechanisms and techniques allow speculative execution of load instructions in the processor, whereas if the value of the speculation indicator indicates that speculative execution of load instructions is not allowed in the computerized device, the mechanisms and techniques do not allow speculative execution of load instructions in the processor.Type: GrantFiled: August 8, 2001Date of Patent: February 8, 2005Assignee: Sun MicrosystemsInventor: David Dice
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Patent number: 6823434Abstract: The present invention relates to a system and method for establishing an illegal system state for a table which is preferably fully associative to disable matching of prospective entries (entries to be written to the table) with entries already resident in the table. Preferably, disabling the matching of prospective and table entries forces a system for updating the fully associative table or array to employ a pointer system for writing prospective entries into the fully associative table. The illegal system may be invoked automatically upon powering up the system for updating the fully associative array or may be associated with a machine specific state effected upon issuing a specific command during program execution.Type: GrantFiled: February 21, 2000Date of Patent: November 23, 2004Assignee: Hewlett-Packard Development Company, L.P.Inventors: David P Hannum, Rohit Bhatia
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Publication number: 20040221132Abstract: The invention generally relates to mapping of signal elements to a limited range of identifiers. The idea according to the invention is to emulate a “virtual” space of identifiers that is larger than the real space of identifiers. The larger virtual identifier space is generally implemented by an intermediate memory (40), which provides storage of identifiers assigned from the real space of identifiers. For each signal element to be mapped to an identifier, the intermediate memory (40) is addressed by means of a hash value (X) calculated from at least part of the signal element, thus allowing access to an identifier. The larger virtual space gives a better distribution of signal elements to the identifiers, and is a key feature for reducing the probability of different signal elements being mapped to the same identifier (clashing).Type: ApplicationFiled: November 20, 2003Publication date: November 4, 2004Inventors: Kjell Torkelsson, Lars-Orjan Kling, Hakan Otto Ahl, Johan Ditmar
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Publication number: 20040210736Abstract: A method and apparatus for the allocation of memory identifiers is generally described. In accordance with one example embodiment of the invention, a method of allocating identifiers comprising generating a hash value associated with a proposed identifier and allocating the identifier only if the hash value has not yet been used in association with another identifier.Type: ApplicationFiled: April 18, 2003Publication date: October 21, 2004Inventors: Linden Minnick, Miles J. Penner
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Publication number: 20040205320Abstract: A method, apparatus and article of manufacture for performing alias refinement is disclosed. Initially, a determination is made as to whether a load of an address exists for a variable in an intermediate representation of the source code. If a load of the address exists for the variable, a further determination is made whether each use of the address is for an indirect reference of the variable. If a particular use of the address is for an indirect reference of the variable, the indirect reference is replaced with a direct reference in the intermediate representation. If all uses of the address are for an indirect reference of the variable, the variable is removed from an alias set used with the intermediate representation.Type: ApplicationFiled: March 20, 2001Publication date: October 14, 2004Applicant: International Business Machines CorporationInventors: Patrick Todd Haugen, Tim Clayton Muehe
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Patent number: 6804759Abstract: In a computer processor, a low-order portion of a virtual address for a pipelined operation is compared directly with the corresponding low-order portions of addresses of operations below it in the pipeline to detect an address conflict, without first translating the address. Preferably, if a match is found, it is assumed that an address conflict exists, and the pipeline is stalled one or more cycles to maintain data integrity in the event of an actual address conflict. Preferably, the CPU has caches which are addressed using real addresses, and a translation lookaside buffer (TLB) for determining the high-order portion of a real address. The comparison of low-order address portions provides conflict detection before the TLB can translate a real address of an instruction.Type: GrantFiled: March 14, 2002Date of Patent: October 12, 2004Assignee: International Business Machines CorporationInventor: David Arnold Luick
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Publication number: 20040181645Abstract: One embodiment of the present invention provides a system that facilitates avoiding collisions between cache lines containing objects and cache lines containing corresponding object table entries. During operation, the system receives an object identifier for an object, wherein the object identifier is used to address the object in an object-addressed memory hierarchy. The system then applies a mapping function to the object identifier to compute an address for a corresponding object table entry associated with the object, wherein the mapping function ensures that a cache line containing the object table entry does not collide with a cache line containing the object.Type: ApplicationFiled: March 13, 2003Publication date: September 16, 2004Inventors: Gregory M. Wright, Mario I. Wolczko, Matthew L. Seidl
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Publication number: 20040153611Abstract: Methods and apparatus to detect memory address conflicts are disclosed. When a new cache line is allocated, the cache places the location where the cache line will be placed in a “pending” state until the cache line is retrieved. If a subsequent memory request is looking for an address in the pending cache line, that request is held back (e.g., delayed or replayed), until the cache line fill is complete and the “pending” status is removed. In this manner, the “pending” state, typically used to reserve cache locations, is also used to detect address conflicts.Type: ApplicationFiled: February 4, 2003Publication date: August 5, 2004Inventors: Sujat Jamil, Hang Nguyen, Quinn Merrell, Samantha J. Edirisooriya, David E. Miner, R. Frank O'Bleness, Steven J. Tu
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Publication number: 20040133761Abstract: Processes are monitored as components are loaded into memory. Relocation of a component to an alternate base address instead of its preferred base address, causes an alternate component to be created corresponding to the relocated component. The alternate component is a copy of the relocated component, but the preferred base address of the alternate component is reset to be the alternate base address of the relocated component. Additional alternate components may be created for each relocated component, with each additional alternate component being optimized in a different manner. Alternate components may be implemented as alternate data stream of the corresponding relocated components. In response to subsequent requests to load a selected component into memory, it is determined whether the selected component has at least one corresponding alternate component. If so, one of the corresponding alternate components is loaded into memory instead of the selected component.Type: ApplicationFiled: November 21, 2003Publication date: July 8, 2004Applicant: RTO SoftwareInventor: Kevin Goodman
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Patent number: 6754798Abstract: A method and apparatus to dynamically order features and manage features, especially aggregators, during creation of a logical volume is provided. The method and apparatus make use of a partition/aggregate list to identify partitions and/or aggregates that make up a logical volume that is to be created. In addition, the partition/aggregate list identifies features to be applied to the partitions and/or aggregates as well as the order in which these features are to be applied. The order in which these features are to be applied is designated by a current feature indicator (CFI). Based on a current CFI count of an entry in the partition/aggregate list, application of a feature corresponding to the current CFI count is attempted. If successful, the current CFI count is incremented and the process returns to a first entry in the partition/aggregate list. If unsuccessful, the current CFI count is not incremented and the process continues on to the next entry in the partition/aggregate list.Type: GrantFiled: October 26, 2000Date of Patent: June 22, 2004Assignee: International Business Machines CorporationInventors: Mark A. Peloquin, Benedict Michael Rafanello, Cuong Huu Tran, Cristi Nesbitt Ullmann
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Patent number: 6751720Abstract: L1 cache synonyms in a two-level cache system are detected and resolved by logic in the L2 cache. Duplicate copies of the L1 cache tags and state (“Dtags”) are maintained in the L2 cache. After a miss occurs in the L1 cache, the Dtags in the second-level cache that correspond to all possible synonym locations in the L1 cache are searched for synonyms. If a synonym is found, the L2 cache notifies the L1 cache where the requested cache line can be found in the L1 cache. The L1 cache then copies the cache line from the location where the synonym was found to the location where the miss occurred, and it invalidates the cache line at the original location. The Dtags in the second-level cache are updated to reflect the changes made in the L1 cache.Type: GrantFiled: January 7, 2002Date of Patent: June 15, 2004Assignee: Hewlett-Packard Development Company, L.P.Inventors: Luiz André Barroso, Kourosh Gharachorloo, Andreas Nowatzyk, Robert J. Stets, Jr., Mosur Kumaraswamy Ravishankar
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Patent number: 6751719Abstract: A method and apparatus to dynamically order features and resolve conflicts in a logical volume management environment is provided. The method and apparatus classifies features of a logical volume into partition level, aggregate level and volume level classes. Based on these classes and the attributes associated with each feature, ordering of the features in a feature stack is performed and conflicts between features identified for conflict resolution. In addition, the apparatus and method provides a mechanism by which a default ordering of features selected by a user may be generated for a logical volume. The user may accept this default ordering or edit the ordering as long as the user does not generate any conflicts. Any conflicts generated will be reported to the user and the attempted ordering will not be allowed.Type: GrantFiled: October 26, 2000Date of Patent: June 15, 2004Assignee: International Business Machines CorporationInventors: Mark A. Peloquin, Benedict Michael Rafanello, Cuong Huu Tran, Cristi Nesbitt Ullmann
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Patent number: 6751700Abstract: A data processor and storage system which comprises a data processor, a cache memory and a main memory is arranged so that the addressing of the main memory produces a multiplicity of spaced aliases, the multiplicity being greater than the set-associativity of the cache memory. The cache memory may be a multiple way set associative cache memory with the system including a round robin allocator for controlling the storing of successive data items in the different ways of the set associative cache. The cache may also be a direct mapped cache having single way set-associativity so that the round robin allocator is not required. The system may also include a direct memory access (DMA) device for copying data items into the memory. The memory may be a buffer memory which is divided into a plurality of packet buffers.Type: GrantFiled: April 2, 2001Date of Patent: June 15, 2004Assignee: 3Com CorporationInventors: Bryan J Donoghue, Lee C Harrison, Edward Turner, Tin Lam, Victoria A Griffiths
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Publication number: 20040098560Abstract: Paging scheme for a microcontroller for extending available register space. A method for paging at least a portion of an address space in a processing system is disclosed. A plurality of addressable memory locations are provided arranged in pages. Each of the addressable memory locations in each of the pages occupies at least a portion of the address space of the processing system and has an associated address in the address space of the processing system. A page pointer is stored in a storage location to define the desired page and then an address is generated in the at least a portion of the address space of the processing system. At least one of the addressable memory locations in at least two of the pages with the same address has identical information stored therein.Type: ApplicationFiled: November 15, 2002Publication date: May 20, 2004Inventors: Alvin C. Storvik, Kenneth W. Fernald, Paul Highley, Brent Wilson
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Publication number: 20040078546Abstract: A processor includes a tagging buffer for storing information that advises the processor of potential memory collisions caused by program instruction pairs that refer to the same memory address. In one method for avoiding memory collisions, a program having tagging code identifying program instruction pairs of the program that refer to a same memory address is compiled. The program instruction pairs in the compiled program code are processed while verifying an order in which the program instruction pairs are to be executed using the compiled tagging code, which is loaded into a tagging buffer. In another method, a program that does not include tagging code is compiled. When a trap occurs in the processing of a program instruction pair, program counters that cause the instructions to be executed in a desired order are added to a tagging buffer. A computer system including the processor also is described.Type: ApplicationFiled: October 18, 2002Publication date: April 22, 2004Applicant: SUN MICROSYSTEMS, INC.Inventor: Jan Civlin
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Publication number: 20040068633Abstract: A method and a circuit for avoiding memory access collisions during asynchronous read-write access to a single-port RAM (SPRAM) are described. Serial write access by means of a serial interface and read access with a read strobe from an independent read device are generated asynchronously. Prerequisites for the implementation are: firstly, use of a serial interface providing a serial clock signal; secondly, write access to SPRAM has to occur at the end of serial transmission; thirdly, a write strobe impulse has to be short compared to the original read strobe. Energy saving is achieved by guaranteeing only one regular read strobe, even when multiple write accesses occur during one read access. The read strobe signal can therefore be used also for control of an LCD backplane counter.Type: ApplicationFiled: October 21, 2002Publication date: April 8, 2004Applicant: Dialog Semiconductor GmbHInventor: Markus Engelahardt
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Publication number: 20040064655Abstract: A method of generating physical memory access statistics for a computer system having a non-uniform memory access architecture which includes a plurality of processors located on a respective plurality of boards. The method includes monitoring when a memory trap occurs, determining a physical memory access location when the memory trap occurs, determining a frequency of physical memory accesses by the plurality of processors based upon the physical memory access locations, and generating physical memory statistics showing the frequency of physical memory accesses by the plurality of processors for each board of the computer system.Type: ApplicationFiled: September 27, 2002Publication date: April 1, 2004Inventor: Dominic Paulraj
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Publication number: 20040064673Abstract: A system, method, and computer program product are disclosed for migrating real pages. A real page of data is established. Virtual addresses that are associated with the real addresses that are included within the real page are generated. A mapping table is established that includes mappings of the virtual addresses to these real addresses. A routine is executed that accesses the mapping table to obtain the mappings of virtual addresses to real addresses. The routine utilizes the virtual addresses to access the data that is stored in the real page. While the routine is executing, the data is migrated from the real page to a new real page. The mapping table is then updated while the routine is executing so that the routine utilizes the same virtual addresses to access the data that is now stored in the new real page. Execution of the routine continues while the mapping table is being updated.Type: ApplicationFiled: September 30, 2002Publication date: April 1, 2004Applicant: International Business Machines CorporationInventors: Mark Douglass Rogers, Randal Craig Swanberg
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Patent number: 6684315Abstract: A method and system for purging translation lookaside buffers (TLB) of a computer system are described. Directed write transactions can be used to avoid deadlock and avoid the need for additional bridge buffers. Broadcast emulation can be achieved by linking the nodes in a doubly-linked list and having neighboring nodes notify each other of changes in TLB entries.Type: GrantFiled: January 22, 2002Date of Patent: January 27, 2004Assignee: Apple Computer, Inc.Inventors: David V. James, Donald N. North
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Patent number: 6675282Abstract: A system and method for storing only one copy of a data block that is shared by two or more processes is described. In one embodiment, a global/non-global predictor predicts whether a data block, specified by a linear address, is shared or not shared by two or more processes. If the data block is predicted to be non-shared, then a portion of the linear address referencing the data block is combined with a process identifier that is unique to form a global/non-global linear address. If the data block is predicted to be shared, then the global/non-global linear address is the linear address itself. If the prediction as to whether or not the data block is shared is incorrect, then the actual value of whether or not the data block is shared is used in computing a corrected global/non-global linear address.Type: GrantFiled: February 12, 2003Date of Patent: January 6, 2004Assignee: Intel CorporationInventors: Herbert H. J. Hum, Stephan J. Jourdan, Deborrah Marr, Per H. Hammarlund
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Patent number: 6658547Abstract: A method for asserting an address alignment of an address for a memory-mapped device in a logic design is disclosed. An align primitive comprising an alignment size port, an input address port and an output address port is used. The alignment size port has data indicating a desired address boundary. The input address port is used for an address to be verified against the desired address boundary. The output address port is used to provide an address that is on the desired address boundary. The address to be verified against the desired address boundary is provided at the output address port when that address meets the desired address boundary. Another method for specifying an offset address for a memory-mapped device in a logic design is disclosed. An offset primitive is used to assert an address for the memory-mapped device. The offset primitive comprises an incoming address port, an outgoing address port and an offset value port. The offset value port has a data value indicating a desired address offset.Type: GrantFiled: August 23, 2000Date of Patent: December 2, 2003Assignee: Triscend CorporationInventors: Bart Reynolds, Sridhar Krishnamurthy, Damon McCormick, Kai Zhu
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Patent number: 6654818Abstract: A method, data processing system, and I/O subsystem suitable for authorizing DMA accesses requested by a 64-bit I/O adapter are disclosed. The system includes one or more processors that have access to a system memory. A host bridge is connected between the processor(s) and an I/O bus. A first I/O adapter, which generates 32-bit addresses, is coupled to the host bridge. A second I/O adapter coupled to the host bridge is enabled to generate an address with a width greater than 32-bits (such as a 64-bit address). The system may include a Translation Control Entry (TCE) table, that is configured with information needed to translate an address generated by the 32-bit adapter to a wider address (such as a 64-bit address). In addition, the TCE may determine whether DMA access to the translated address by the requesting adapter is authorized. The system further includes an Access Control Table (ACT). The ACT determines whether DMA access to the address generated by the 64-bit I/O adapter is authorized.Type: GrantFiled: June 22, 2000Date of Patent: November 25, 2003Assignee: International Business Machines CorporationInventor: Steven Mark Thurber
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Publication number: 20030204689Abstract: A non-volatile semiconductor memory device according to the invention includes a copy area latch circuit for latching information therein, a copy source address latch circuit for latching therein information read from a copy source, and write control means for comparing the information latched in the copy area latch circuit and the information latched in the copy source address latch circuit with each other, and automatically copying data latched in a source area of the copy source to a destination area of a copy destination, the destination area corresponding to the source area, until the information latched in the copy area latch circuit and the information latched in the copy source address latch circuit become coincide with each other following implementation of a newly provided copy command when data is copied from external storage means as a copy source to a non-volatile memory.Type: ApplicationFiled: April 18, 2003Publication date: October 30, 2003Applicant: NEC Electronics CorporationInventor: Hiroshi Shimoda
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Patent number: 6640293Abstract: A data processing system including a processor having a load/store unit and method for utilizing alias hit signals to detect errors within the read address tag arrays. Within a load store unit, implemented within a processor, a real address tag array is utilized to indicate when effective address aliasing occurs in a primary cache array. If aliasing occurs, Alias Hit signals are then used to clear any aliased entries. These Alias Hit signals can also be utilized to determine if there has been some type of failure within the real address tag array.Type: GrantFiled: July 24, 2000Date of Patent: October 28, 2003Assignee: International Business Machines CorporationInventors: Jose Angel Paredes, Bruce Joseph Ronchetti, Binta Minesh Patel, George McNeil Lattimore
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Patent number: 6633967Abstract: The invention is a coherent translation look-aside buffer (TLB) for use in an input/output (I/O) bridge of a symmetrical multiprocessing (SMP) system. The contents of the TLBs may be kept in one of two possible states: exclusive or invalid. When the I/O bridge receives a TLB entry for storage in its TLB, the state of that entry is exclusive. Specifically, the TLB is considered the exclusive owner of the respective TLB entry. The exclusively owned TLB entry may be used by the TLB to translate I/O addresses to system addresses. If some other agent or entity of the SMP system seeks access to the TLB entry (e.g., for purposes of executing a read or write operation), the TLB is notified and the state of the TLB entry transitions to invalid. With the TLB entry in the invalid state, the TLB can no longer use the TLB entry for translating I/O addresses to system addresses.Type: GrantFiled: August 31, 2000Date of Patent: October 14, 2003Assignee: Hewlett-Packard Development Company, L.P.Inventor: Samuel H. Duncan
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Publication number: 20030177334Abstract: In a first aspect and in a computer system that runs more than one operating system, a scheme for mapping memory locations in a data storage device is provided. A range of logical memory addresses at a low end of a logical memory address space is duplicated, and each duplicate range is assigned to a respective operating system, and mapped to a respective range of the storage device's physical memory address space, thereby reserving respective portions of the physical memory address space for writing of each operating system's configuration data.Type: ApplicationFiled: March 14, 2002Publication date: September 18, 2003Applicant: International Business Machines CorporationInventors: Brian James King, Timothy Jerry Schimke
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Publication number: 20030177335Abstract: In a computer processor, multiple partially translated real addresses for a pipelined operation are compared with the real addresses of one or more other operations in the pipeline to detect an address conflict, without waiting for the address translation mechanism to fully translate the real address. Preferably, if a match is found, it is assumed that an address conflict exists, and the pipeline is stalled one or more cycles to maintain data integrity in the event of an actual address conflict. Preferably, the CPU has caches which are addressed using real addresses, and an N-way translation lookaside buffer (TLB) for determining the high-order portion of a real address. Each of the N real address portions in the TLB is compared with other operations in the pipeline, before determining which is the correct real address portion.Type: ApplicationFiled: March 14, 2002Publication date: September 18, 2003Applicant: International Business Machines CorporationInventor: David Arnold Luick
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Patent number: 6622209Abstract: In one embodiment of the invention, data values which are provided to a non-tagged, n-way cache are written into the cache in a non-count form. Whereas a counter tends to quickly saturate to one extreme or the other (e.g., all zeros or all ones), or briefly take on a value which approaches an extreme, a non-count data value (e.g., branch prediction history bits) tends to assume a wider variety of values.Type: GrantFiled: September 30, 2002Date of Patent: September 16, 2003Assignee: Hewlett-Packard Development Company, L.P.Inventor: James E McCormick, Jr.
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Publication number: 20030167386Abstract: A control chip and operating method for accelerating memory access that can be applied to a memory system whose memory read command actual address is read from a system bus in a number of synchronous transmissions. On receiving a first section read address, the control chip operates to compare the first section read address with an identical bit portion of the write address of the memory-write commands inside a memory-write command queue. If the comparison indicates some difference, permission for executing the memory read command is granted. If the comparison indicates the presence of identical bits, a second section read address is received and compared with an identical bit portion of the write address of the memory-write commands inside a memory-write command queue. If the comparison indicates some difference, permission for executing the memory read command is granted.Type: ApplicationFiled: July 17, 2002Publication date: September 4, 2003Inventors: Kuang-Kai Kuo, Kuo-Ping Liu
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Publication number: 20030163643Abstract: A system and method are disclosed which enable resolution of conflicts between memory access requests in a manner that allows for efficient usage of cache memory. In one embodiment, a circuit comprises a cache memory structure comprising multiple banks, and a plurality of access ports communicatively coupled to such cache memory structure. The circuit further comprises circuitry operable to determine a bank conflict for pending access requests for the cache memory structure, and circuitry operable to issue at least one access request to the cache memory structure out of the order in which it was requested, responsive to determination of a bank conflict.Type: ApplicationFiled: February 22, 2002Publication date: August 28, 2003Inventors: Reid James Riedlinger, Dean A. Mulla, Tom Grutkowski
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Patent number: 6594750Abstract: A method and apparatus for handling an accessed bit in a page table entry is provided. When a page table entry is not present in a translation lookaside buffer (TLB), an electrical circuit causes a TLB miss exception and branching to a first software exception handler. The first software exception handler fetches the page table entry from main memory. The first software exception handler places the page table entry in the TLB. An electrical circuit determines whether an accessed bit of the page table entry has not been asserted. If the accessed bit is not asserted, an electrical circuit causes an accessed bit exception and branches execution to a second software exception handler. The second software exception handler asserts the accessed bit in the page table entry in main memory. The second software exception handler returns control back to the original memory access, causing execution to resume where it had left off prior to the TLB miss exception.Type: GrantFiled: December 8, 1999Date of Patent: July 15, 2003Assignee: ATI International SrLInventor: Paul Campbell
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Publication number: 20030126357Abstract: In a memory device with a bank of N memory blocks, an address is generated for a first and a second one of the blocks. The first and second addresses include addresses for current first and second possible “refresh blocks”. If its memory block does not contend with the current first possible refresh block, an externally generated access to one of the N memory blocks is permitted and at least a portion of the refresh block is refreshed during a certain interval. In another aspect, the externally generated access is permitted and at least a portion of the current second possible refresh block is refreshed during the same certain interval if: i) the memory block of the externally generated access contends with the current first possible refresh block and ii) the current first and second possible refresh blocks are different ones of the N memory blocks.Type: ApplicationFiled: December 31, 2001Publication date: July 3, 2003Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chuan-Yu Wu, Jia-Ming Yang, Chris Huang
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Patent number: 6584556Abstract: A two-stage, pipelined modulo address generator (MAG) (30′) for generating from a current pointer into a circular buffer of size L, a next pointer into the buffer, is comprised of a pointer generation stage (32′) and a modulo correction and pointer selection stage (34′), each adapted to operate in a selected one of two modes. In the first operating mode: the pointer generation stage (32′) generates a sequential pointer which is a selected offset from the current pointer; and the modulo correction and pointer selection stage (34′) generates, modulo L, a modulo corrected sequential pointer, and provides as the next pointer the sequential pointer, if it is in the buffer, and the modulo corrected sequential pointer, otherwise.Type: GrantFiled: March 28, 2000Date of Patent: June 24, 2003Assignee: Analog Devices, Inc.Inventor: David B. Witt
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Patent number: 6571319Abstract: Instruction combining logic combines data from a plurality of write transactions before the data is written into main memory. In one embodiment, the instruction combining logic receives write transactions generated from store pair instructions, stores data from the write transactions in a buffer, and combines the data in the buffer. The combined data is subsequently written to memory in a single write transaction. The instruction combining logic may determine whether the data from the transactions are in the same cache line before combining them. A programmable timer may be used to measure the amount of time that has elapsed after the instruction combining logic receives the first write transaction. If the elapsed time exceeds a predetermined limit before another write instruction is received, the instruction combining logic combines the data in the buffer and writes it to memory in a single write transaction.Type: GrantFiled: June 4, 1999Date of Patent: May 27, 2003Assignee: Sun Microsystems, Inc.Inventors: Marc Tremblay, Shrinath Keskar
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Publication number: 20030093644Abstract: A method for a cache line replacement policy enhancement to avoid memory page thrashing. The method of one embodiment comprises comparing a memory request address with cache tags to determine if any cache entry in set ‘n’ can match the address. The address is masked to determine if a thrash condition exists. Allocation to set ‘n’ is discouraged if a thrash condition is present.Type: ApplicationFiled: December 13, 2002Publication date: May 15, 2003Inventor: Blaise B. Fanning
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Patent number: 6560690Abstract: A system and method for storing only one copy of a data block that is shared by two or more processes is described. In one embodiment, a global/non-global predictor predicts whether a data block, specified by a linear address, is shared or not shared by two or more processes. If the data block is predicted to be non-shared, then a portion of the linear address referencing the data block is combined with a process identifier that is unique to form a global/non-global linear address. If the data block is predicted to be shared, then the global/non-global linear address is the linear address itself. If the prediction as to whether or not the data block is shared is incorrect, then the actual value of whether or not the data block is shared is used in computing a corrected global/non-global linear address.Type: GrantFiled: December 29, 2000Date of Patent: May 6, 2003Assignee: Intel CorporationInventors: Herbert H. J. Hum, Stephan J. Jourdan, Deborrah Marr, Per H. Hammarlund
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Patent number: 6553460Abstract: Methods of managing a cache memory system in a data processing system are disclosed. The data processing system executes instructions and stores and receives data from a memory having locations in a memory space. The entries of the cache memory are in locations in a register space separate from the memory space. A first instruction that operates only on locations in a register space but not on locations in memory space may be executed to obtain address information from at least one entry of the cache memory. The obtained address information be compared with target address information. If the comparison between the obtained address information and the target address information results in a correspondence, then a first operation may be performed on the entry of the cache memory. If the comparison between the obtained address information and the target address information does not result in a correspondence, then the fit first operations not performed on the entry of the cache memory.Type: GrantFiled: October 1, 1999Date of Patent: April 22, 2003Assignee: Hitachi, Ltd.Inventors: Rajesh Chopra, Shinichi Yoshioka, Mark Debbage