Abstract: In executing indivisible operations to be executed without being interrupted, pseudo-store instructions PST which do not perform data writing are used to perform a check for the presence or absence in a memory of pages necessary for execution of the indivisible operations. In the event of absence of the necessary pages, the necessary pages are pre-stored in the memory. This prevents the generation of page fault interruptions during the execution of an indivisible operation, thereby enabling the indivisible operation to be implemented on a software basis. A disable interrupt instruction is executed prior to the execution of the indivisible operation as required, and data indicating an address of the disable interrupt instruction is preserved in order to return to the disable interrupt instruction.

Abstract: A cache system in accordance with the present invention consists of one or more cache components and a set of one or more consistency-replacement functions. A cache component caches one or more items in its one or more cache entries. Items that hit in the cache can result in corresponding cache entries being read or written. Any valid entry in a cache component includes status information reflecting whether the entry has been accessed and whether it has been modified, and is linked to a consistency-action matrix that, in correspondence with the entry's status information and access type (i.e. read or write), determines what consistency action has to be executed in conjunction with the current entry access. consistency actions and the consistency-action matrix are the inventive mechanisms for implementing cache-coherency and cache-replacement policies. Any valid entry in a cache is linked to a consistency-replacement function that implements one or more consistency and/or replacement policies.

Abstract: The inventive mechanism determines whether memory source and destination addresses map to the same or nearly the same cache address. If they map to different addresses, then loads and stores are ordered so that loads to one cache bank are performed on the same clock cycles as the stores to another cache bank. After a group of loads and stores are completed, then load and store operations for each bank are switched. If the source and destination addresses map to nearly the same cache address and if the source address is prior to the destination address, then a group of cache lines is loaded into registers and stored to memory without any interleaving of other loads and stores. If the source and destination addresses map to the same cache location, then an initial load of data into registers is performed. After that, additional loads are interleaved with non-cache conflicting stores to move new values into memory. Thus, loads and stores to matching cache addresses are separated by time.

Abstract: An effective-to-real address translation cache management apparatus and method utilizes an effective-to-real address translation cache segment register latch having a bit corresponding to each of the segment registers. When a segment register is utilized to perform an effective-to-real address translation, which is stored in the effective-to-real address translation cache, the corresponding bit in the effective-to-real address translation cache segment register latch is set. In this way, a record is kept of which segment registers are currently mapped in the effective-to-real address translation cache. When a move to segment register instruction alters the content of a segment register, then the effective-to-real address translation cache segment register latch is examined to determine if that segment register has been mapped in the effective-to-real address translation cache. If so, then an effective-to-real address translation cache invalidation latch is set.

Abstract: A protect circuit of a register which can positively protect the contents of a register in a runaway of a program in a microcomputer or the like. It includes a first register for holding data on a data bus of a microcomputer at a first time instant, a second register for holding the data on the data bus at a second time instant which is later than the first time instant by a predetermined time interval, a timer for counting a time period from the first time instant, the timer overflowing when it counts a predetermined time period longer than the predetermined time interval, and a controller for updating a register to be protected by moving data in the first register into the register to be protected only when the second register holds, before the timer overflows, the same data as that held in the first register.

Abstract: A multi-processor computer system with clustered processing units uses a cache coherency protocol having a "recent" coherency state to indicate that a particular cache block containing a valid copy of a value (instruction or data) was the most recently accessed block out of a group of cache blocks in different caches (but at the same cache level) that share valid copies of the value. The "recent" state can advantageously be used to implement optimized memory operations such as intervention, by sourcing the value from the cache block in the "recent" state, as opposed to sourcing the value from system memory (RAM), which would be a slower operation. In an exemplary implementation, the hierarchy has two cache levels supporting a given processing unit cluster; the "recent" state can be applied to a plurality of caches at the first level (each associated with a different processing unit cluster), and the "recent" state can further be applied to one of the caches at the second level.

Abstract: A method and mechanism for converting a non-contiguous subset of values in a large range, such as selected Unicode code points, into a contiguous or mostly contiguous smaller range with a perfect hash. The large range is organized into a two-dimensional bitmap matrix of pages and offsets into the pages. The bits in the matrix equal one if the value is in the subset, and zero if not. The pages are then overlaid on one another into a one-dimensional bitmap by shifting each page as necessary to avoid conflicts with values on other pages. The shift amount is recorded and used in a hash computation, wherein a value of the large range is first separated into its page number and its offset into the page. The values are then hashed into the value of the dense subset range by looking up the shift amount for the page and adding the shift amount to the offset into the page.

Abstract: A circuit for transferring a logic value from a content addressable memory (CAM) having a plurality of match lines to a random access memory (RAM) having a plurality of word lines. A first logic gate has an input coupled to a first match line of the plurality of match lines, and a second logic gate has an input coupled to a second match line of the plurality of match lines. A first switch is coupled between an output of the first logic gate and a first word line, and a second switch is coupled between an output of the second logic gate and a second word line. The first switch is controlled by the output of the second logic gate such that the first switch is opened when the second match line has a second logic value and closed when the second match line has a first logic value. The second switch is controlled by the output of the first logic gate such that the second switch is opened when the first match line has the second logic value and closed when the first match line has the first logic value.

Abstract: A separate cacheable-in-virtual-cache attribute bit (CV) is maintained for each page of memory in the translation table maintained by the operating system. The CV bit indicates whether the memory addresses on the page to which the translation table entry refers are cacheable in virtually indexed caches. According to a first embodiment, when there are two or more aliases which are not offset by multiples of the virtual cache size, all of the aliases are made non-cacheable in virtually indexed caches by deasserting the CV bits for all aliases. With regards to the contents of the translation lookaside buffer (TLB), the translations for all aliases may simultaneously coexist in the TLB because no software intervention is required to insure data coherency between the aliases. According to second and third embodiments of the present invention, when there are two or more aliases which are not offset by multiples of the virtual cache size, only one of those aliases may remain cacheable in virtual caches.

Abstract: A multiplexed computer system allows memory accessing by a processor, a peripheral equipment or a like apparatus even during execution of memory copying to improve the processing performance during on-line maintenance. To this end, the multiplexed computer system includes a plurality of processing units which carry out the same operation in synchronism with each other.

Abstract: A database management system (DBMS) is modified to provide improved concurrent usage of database objects, particularly when the system is executing long lived transactions. A subset of the transactions access database objects using parameterized read and parameterized write access modes. Each transaction using a parameterized write mode of access for a database object specifies a write access mode, and a write access mode parameter, where the parameter indicates a data reliability classification. Each transaction using a parameterized read mode of access for a database object specifies a read access mode, and a read access mode parameter, where the parameter indicates one or more reliability classifications that are acceptable to the transaction. Whenever a transaction requests access to a specified database object, the DBMS generates a corresponding lock request for the object. If the lock request is a parameterized lock request, a corresponding parameterized lock request is generated.

Abstract: A network interface circuit including an address translation unit and a flush check circuit, and a method for checking for an invalid address translation within of the address translation unit, are disclosed. A flush check circuit, in communication with the address translation unit, is implemented to determine, prior to loading an address translation into the internal memory, whether one of the plurality of entries already contains a virtual address utilized by the address translation. If so, an error has occurred with the flushing operations of the address translation unit because the address translation should have already been removed. In response, the flush check circuit signals logic to perform error handling techniques such as issuing an error signal, storing the invalid address translation unit, or transmitting the virtual address of the address translation without loading that address translation.

Abstract: In a computer system comprising a CPU, a cache memory and a main memory wherein the cache memory is virtually addressed, and some of the virtual addresses are alias address to each other, a cache memory controller comprising a cache control logic, a cache tag array, a memory management unit, and an alias detection logic is provided. The cache control logic skips flushing of a cache line if the cache line is corresponding to a memory block in a non-cacheable physical memory page, thereby avoiding unnecessary flushes and allowing the CPU to update the cache memory and the main memory using an improved write through and no write allocate approach that reduces cache flushes.

Abstract: Microkernel memory references, traditionally required to refer to memory by exact physical address, are transformed so as to be able to map the references to addresses in multiple memory nodes. As a result, each node's address space may be compiled to by multiple microkernels. Reverse mapping responsive to coherency requests facilitates cache coherency.

Abstract: In a virtually addressed and physically indexed cache memory, the allocation of a color of a cache entry can be changed for a color allocation of the virtual and physical pages by assigning a color information to each cache entry, by which a second cache address operation is executed after an unsuccessful first cache address operation. Should there still be no cache hit, another cache addressing is attempted by means of a color correction, i.e. an indexing of the cache memory using, among others, the physical color. Should this cache address operation also fail to produce a cache hit, there is a cache miss.

Abstract: An interleaved data cache array which is divided into two sub arrays is provided for utilization within a data processing system. Each subarray includes a plurality of cache lines wherein each cache line includes a selected block of data, a parity field, a first content addressable field containing a portion of an effective address for the selected block of data, a second content addressable field contains a portion of the real address for the selected block of data and a data status field. By utilizing two separate content addresssable fields for the effective address and real address offset and alias problems may be efficiently resolved. A virtual address aliasing condition is identified by searching each cache line for a match between a portion of a desired effective address and the content of the first content addressable field.

Abstract: A method and apparatus for generating a qualify bit and detecting matching addresses in the completion unit register file, or annex, of a processor. A qualify bit is appended to each entry in the annex. Overlapping register windows are represented by a window pointer and a register index. Annex entries addressed to the same window or addressed to GLOBAL registers always qualify. Annex entries addressed to OUT registers only qualify if the instruction address is one of the IN registers of the next window. Annex entries addressed to IN registers only qualify if the instruction address is one of the OUT registers of the previous window. A pseudo-address bit is appended to each annex entry. For IN and OUT registers, the indexes for the aliases differ by one bit. The pseudo-address bit normally takes on the value of the most significant bit of the annex entry's index.

Abstract: A self-directed distributed system provides a method for mutual exclusion of asynchronously interacting processors. The system comprises a system for control of access to a shared resource in a multi-processing computing environment, comprising at least two processors; an interconnection system interconnecting the processors, whereby each processor can communicate with all other processors; a resource for shared access by the processors; communication means within each processor for sending an interest signal to all other processors for signalling the interest of the processor in acquiring the resource; receiving means within each processor for receiving the interest signal of every other processor; interest vector means within each processor for storing the received interest signal of every other processor; and means within each processor for interrogating the interest vector means in the processor to determine the availability of the resource.

Abstract: An apparatus for facilitating the sharing of memory blocks, which has local physical addresses at a computer node, between the computer node and an external device. The apparatus includes snooping logic configured for coupling with a common bus of the computer node. The snooping logic is configured to monitor, when coupled to the common bus, memory access requests on the common bus. There is also included a snoop tag array coupled to the snooping logic. The snoop tag array includes tags for tracking all copies of a first plurality of memory blocks of the memory blocks cached by the external device. Further, there is included a protocol transformer logic coupled to the snooping logic for enabling the apparatus, when coupled to the external device, to communicate with the external device using a protocol suitable for communicating with the external device.

Abstract: A coherence transformer for allowing a computer node and one or more external devices to share memory blocks having local physical addresses at a memory module of the computer node. The coherence transformer includes logic for ascertaining whether a memory access request from the external device for a memory block should be responded to using a snoop-only approach or an Mtag-only approach. The snoop-only approach requires a tag in a snoop tag array of the coherence transformer be available to track the memory block for an entire duration that the memory block is cached by the external device. The Mtag-only approach only temporarily stores the memory block until a global state associated with the memory block can be written back into the memory module of the computer node. The snoop tag array allows the coherence transformer to snoop the bus of the computer node to intervene and respond to memory access requests pertaining to a memory block externally cached and tracked by the snoop tag array.

Abstract: An integrated processor is provided that includes a cache controller which keeps track of a physical address in the system memory which corresponds to each entry within the cache memory. The address tag and state logic circuit further contains state information consisting of a dirty bit allocated for each doubleword (or word) within each line as well as a valid bit for each line. The dirty bit allocated for each doubleword indicates whether that doubleword is dirty or clean, and the valid bit for each line indicates whether the line is valid or invalid. The cache controller further includes a snoop write-back control circuit which monitors the local bus to determine whether a memory cycle has been executed by an alternate bus master on the local bus. During such a memory cycle of an alternate bus mater, a comparator circuit determines whether a cache hit has occurred.

Abstract: An interface between a memory that has "n" address bit inputs and a processor which has "p" address bit outputs (where p<n) and "q" programmable data bit outputs (where q.gtoreq.n-p). The interface includes a logic circuit connected to a byte select bit output, to a memory read-write command bit output and to an appropriately programmed one of the "q" programmable bit outputs of the processor. The logic circuit produces a least significant bit address bit input AI0 defined by the equation AI0=R/W & byte-s OR R/W & I/O0. The interface connects the remaining "p" address bit inputs of the memory succeeding to the "p" address bit outputs of the processor, in order, and connects the remaining "n-p-1" most significant address bit inputs of the memory to the same number of appropriately programmed programmable bit outputs of the processor.

Abstract: A multiprocessor computer system and method for maintaining coherency between virtual-to-physical memory translations of multiple requestors in the system. A poison bit is associated with a memory block in the system. The poison bit is set to indicate that a virtual-to-physical memory translation for the memory block is stale. An exception is generated in response to an access by one of the requestors to the memory block if the poison bit is set, thereby indicating to the requestor that the virtual-to-physical memory translation entry for the memory block is stale. The virtual-to-physical memory translation for the memory block is then updated with a virtual memory translation corresponding to a new physical location for the memory block. In an embodiment having a cache-based multiprocessor system, the method further comprises the step of invalidating all cached copies of the memory block. In this case, the invalidating step and the setting step must be performed as an atomic operation.

Abstract: Methods and apparatus for using a store allocate policy to eliminate the stale data problem in a direct mapped, write-through virtual data cache. A hardware mechanism provided by the present invention, ensures that a single cache location associated with more than one virtual address does not become stale with respect to the main memory. By using a store allocate policy along with a write-through virtual cache, each time a store miss occurs, the data cache location for which the store miss occurred will be updated with new data brought back from the main memory along with a new cache tag. The store allocate policy for a write-through virtual data cache is implemented by a data cache controller. Thus, using this cache policy, the cache is updated along with the main memory even after a store miss.

Abstract: When an input/output request of a channel adapter causes a mishit on a cache and a staging amount by a device adapter reaches a predetermined amount, the cache is set into a hit status and the channel adapter is reactivated. By receiving a hit response, the reactivated channel adapter executes an input and an output for the cache and the staging of the channel adapter in parallel. A defective/alternating track management table which corresponds to track data stored in a cache memory and has each of addresses of a defective track and an alternating track and flag information showing a link state between both of the defective track and the alternating track is provided for an input/output controller. For a retrieving request in which the defective track address is designated, the defective/alternating track management table is retrieved and the corresponding alternating track address is obtained, thereby judging the presence or absence of a registration of a hash table.

Abstract: A method and system for providing cache coherence despite unordered interconnect transport. In a computer system of multiple memory devices or memory units having shared memory and an interconnect characterized by unordered transport, the method comprises sending a request packet over the interconnect from a first memory device to a second memory device requiring that an action be carried out on shared memory held by the second memory device. If the second memory device determines that the shared memory is in a transient state, the second memory device returns the request packet to the first memory device; otherwise, the request is carried out by the second memory device. The first memory device will continue to resend the request packet each time that the request packet is returned.

Abstract: A miss tracking system optimizes the bandwidth to a main memory that is associated with a processor that utilizes a data cache and that executes instructions out of order. The miss tracking system includes the processor, the main memory in communication with the processor, and a data cache (DCACHE) associated with the processor. The processor has a memory queue (MQUEUE) for receiving and executing instructions that are directed to memory accesses to the DCACHE or the main memory. The MQUEUE includes a plurality of instruction processing mechanisms for receiving and executing respective memory instructions out of order. Each instruction processing mechanism includes an instruction register for storing an instruction and an address reorder buffer slot (ARBSLOT) for storing the data address of the instruction execution results.

Abstract: A cache memory for a computer uses content-addressable tag-compare arrays (CAM) to determine if a match occurs. The cache memory is partitioned in four subarrays, i.e., interleaved, providing a wide cache line (word lines) but shallow depth (bit lines). The cache can be accessed by multiple addresses, producing multiple data outputs in a given cycle. Two effective addresses and one real address are applied at one time, and if addresses are matched in different subarrays, or two on the same line in a single subarray, then multiple access is permitted. The two content-addressable memories, or CAMs, are used to select a cache line, and in parallel with this, arbitration logic in each subarray selects a word line (cache line).

Abstract: A networking system is disclosed that has an improved address resolution protocol. The network system, which includes a table or cache, has a plurality of nodes, each node having a unique address. The protocol establishes in the table an address mapping for each of the nodes in the network system being used. The protocol generates a target address for an addressing request. When an address mapping needs to be reresolved/refreshed, the protocol then sends the request to the node associated with the address currently in the table. The protocol allows for a certain amount of time for the node to accept the request and then updates the address mapping table based upon a reply received within that limited time. If the node fails to reply within a given time, the protocol then broadcasts the request throughout the networking system until a response is received. Once a response is received, the system then updates the table of address mapping.

Abstract: A two-level virtual/real cache system, and a method for detecting and resolving synonyms in the two-level virtual/real cache system, are described. Lines of a first level virtual cache are tagged with a virtual address and a real pointer which points to a corresponding line in a second level real cache. Lines in the second level real cache are tagged with a real address and a virtual pointer which points to a corresponding line in the first level virtual cache, if one exists. A translation-lookaside buffer (TLB) is used for translating virtual to real addresses for accessing the second level real cache. Synonym detection is performed at the second level real cache. An inclusion bit I is set in a directory of the second level real cache to indicate that a particular line is included in the first level virtual cache. Another bit, called a buffer bit B, is set whenever a line in the first level virtual cache is placed in a first level virtual cache writeback buffer for updating main memory.