Addressing Or Allocation; Relocation (epo) Patents (Class 711/E12.002)
  • Publication number: 20140082318
    Abstract: A method for allocating resources of a storage system including at least a first and second group of storage devices. The method identifies a first set of resources to be reserved for use by the first group of storage devices, identifies a second set of resources to be reserved for use by the second group of storage devices, and identifies a third set of resources The method then allocates resources from the third set of resources to the first group of storage devices or the second group of storage device according to an allocation algorithm, and restricts use of the first set of resources to the first group of devices and use of the second set of resources to the second group of devices.
    Type: Application
    Filed: September 14, 2012
    Publication date: March 20, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael T. Benhase, Matthew J. Kalos, Karl A. Nielsen
  • Publication number: 20140082316
    Abstract: Provided are a computer program product, system, and method for selecting pages implementing leaf nodes and internal nodes of a data set index for reuse in memory. Pages in the memory are allocated to internal nodes and leaf nodes of a tree data structure representing all or a portion of a data set index for the data set, wherein the leaf nodes include information on members of the data set. The internal nodes include one or more keys used to traverse the tree data structure to reach the leaf nodes to access the members of the data set. At least one page allocated to the leaf nodes and the internal nodes is selected based on durations during which the allocated pages have not been used. Pages allocated to the leaf nodes are selected for reuse at a higher rate than the pages allocated to the internal nodes.
    Type: Application
    Filed: September 14, 2012
    Publication date: March 20, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Derek L. Erdmann, David C. Reed, Thomas C. Reed, Max D. Smith
  • Publication number: 20140082315
    Abstract: Managing memory allocations in a computer system may include tagging a class of data structures with a tag that identities a longer memory-allocation time for objects that correspond to the class. In response to a memory-allocation request for an object, whether or not the object is associated with the tag can be determined through the class. If the object is not associated with the tag, memory can be allocated for the object from a first memory-allocation area that corresponds to a shorter memory-allocation time, and if the object is associated with the tag, memory can be allocated for the object from a second memory-allocation area that corresponds to the longer memory-allocation time.
    Type: Application
    Filed: September 14, 2012
    Publication date: March 20, 2014
    Applicant: SAP AG
    Inventor: Martin Moser
  • Publication number: 20140074960
    Abstract: A method, system, and computer program product for compacting a non-biased results multiset are provided in the illustrative embodiments. A set of references and a multiset of values are identified. The multiset includes a first and a second set of values, each set including a first value. A first reference in the set of references refers to the first set of values and a second reference in the set of references refers to the second set of values. The values in the first and second set of values are re-arranged to form permuted first and second sets of values. The multiset is compacted by overlaying the permuted first and second sets of values in a portion such that the permuted first set of values and the permuted second set of values share a single instance of the first value in a portion of the compacted multiset.
    Type: Application
    Filed: September 11, 2012
    Publication date: March 13, 2014
    Applicant: International Business Machines Corporation
    Inventors: John Bruce Carter, Colin Kimm Dixon, Wesley Michael Felter, Brent Edward Stephens, James Xenidis
  • Publication number: 20140075139
    Abstract: Provided are a computer program product, system, and method for modifying memory space allocation for inactive tasks. Information is maintained on computational resources consumed by tasks running in the computer system allocated memory space in the memory. The information on the computational resources consumed by the tasks is used to determine inactive tasks of the tasks. The allocation of the memory space allocated to at least one of the determined inactive tasks is modified.
    Type: Application
    Filed: September 13, 2012
    Publication date: March 13, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David C. Reed, Michael R. Scott, Max D. Smith, Ryan J. Wisniewski
  • Publication number: 20140075142
    Abstract: A computer system includes memory and a processor configured to manage memory allocation. The processor is configured to execute a memory allocation request to allocate a portion of the memory to an application by determining whether a size of the memory allocation request is less than a first pre-defined size. The processor searches virtual memory for a free allocated memory area corresponding at least to the size of the memory allocation request based on determining that the size of the memory allocation request is less than the first pre-defined size.
    Type: Application
    Filed: September 13, 2012
    Publication date: March 13, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David Hom, James H. Mulder, Mariama Ndoye, Michael G. Spiegel, Elpida Tzortzatos
  • Publication number: 20140075122
    Abstract: A system for conducting memory transactions includes a non-volatile main memory and a memory buffer including a plurality of cache lines. Each of the cache lines includes content and one or more bits signifying whether a memory transaction corresponding to the content of the cache line has been performed to completion and whether the content of the cache line matches content of a corresponding location of the non-volatile main memory. When the one or more bits of a cache line of the plurality of cache lines signifies that the transaction has been performed to completion and the content of the cache line does not match the content of the corresponding location of the non-volatile memory, access to modify the content of the cache line is restricted until the content of the cache line is written to the corresponding location of the non-volatile main memory.
    Type: Application
    Filed: September 13, 2012
    Publication date: March 13, 2014
    Applicant: International Business Machines Corporation
    Inventors: Mohammad Banikazemi, John Alan Bivens
  • Patent number: 8671263
    Abstract: A method for Dynamic Storage Tiering (DST) may include identifying a first storage tier with a performance characteristic. The method may include monitoring the utilization of the first storage tier to detect the placement of a hot spot. The method may include logically dividing a continuous range of a plurality of logical addresses into at least a first segment and a second segment so the first segment includes a proportionally larger amount of the hot spot. The method may include moving the first segment into a second storage tier or moving the second segment into the second storage tier. The method may include determining an amount of utilization of the first storage tier by hot spots. The method may include recommending a change in an amount of storage space in the first storage tier based upon the amount of utilization of the first storage tier by the hot spots.
    Type: Grant
    Filed: February 3, 2011
    Date of Patent: March 11, 2014
    Assignee: LSI Corporation
    Inventor: Martin Jess
  • Patent number: 8671265
    Abstract: An access request including a client address for data is received. A metadata server determines a mapping between the client address and storage unit identifiers for the data. Each of the one or more storage unit identifiers uniquely identifies content of a storage unit and the metadata server stores mappings on storage unit identifiers that are referenced by client addresses. The one or more storage unit identifiers are sent to one or more block servers. The one or more block servers service the request using the one or more storage unit identifiers where the one or more block servers store information on where a storage unit is stored on a block server for a storage unit identifier. Also, multiple client addresses associated with a storage unit with a same storage unit identifier are mapped to a single storage unit stored in a storage medium for a block server.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: March 11, 2014
    Assignee: SolidFire, Inc.
    Inventor: David D. Wright
  • Publication number: 20140068220
    Abstract: A hardware based memory allocation system in a computer includes: a memory module formatted with memory blocks; an input controller, in communications with the memory module and receiving a transfer request from a requestor, for transferring data from a source to the memory module; an output controller, in communications with the memory module and the input controller, for transferring data from the memory module to a destination; and a block allocator, in communications the input controller and the output controller, for maintaining a Block Descriptor Index (BDI) of Free List (FL) Addresses, each FL address pointing to a Block Descriptor Page (BDP) having a plurality of Memory Block (MB) addresses, each MB address pointing to a free memory block in the memory module.
    Type: Application
    Filed: September 6, 2012
    Publication date: March 6, 2014
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Michael J. Osborn, David E. Mayhew, Mark D. Hummel
  • Patent number: 8667245
    Abstract: Provided are techniques for migrating a first extent, determining a spatial distance between the first extent and a second extent, determining a ratio of a profiling score of the second extent to the spatial distance, and, in response to determining that the ratio exceeds a threshold, migrating the second extent.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: March 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Pui Fun Lau, David Montgomery, Karl A. Nielsen, Richard B. Stelmach
  • Patent number: 8667244
    Abstract: In one implementation, a data set including a plurality of data values having an order is stored at a memory having a plurality of memory locations. Each data value from the data set stored a current memory location of that data value from the plurality of memory locations. Each data value from the data set is periodically moved from the current memory location of that data value from the plurality of memory locations to a next memory location of that data value from the plurality of memory locations. The next memory location of each data value from the plurality of memory locations is the current memory location of that data value from the plurality of memory locations after the moving. The plurality of data values is then provided in the order to a client in response to a request for the data set.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: March 4, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Ted A Hadley, Susan K Langford
  • Publication number: 20140059284
    Abstract: Embodiments of the present invention provide a system, method and computer program products for memory space management for storage class memory. One embodiment comprises a method for information storage in an information technology environment. The method comprises storing data in a storage class memory (SCM) space, and storing storage management metadata corresponding to said data, in the SCM in a first data structure. The method further includes buffering storage management metadata corresponding to said data, in a main memory in a second data structure.
    Type: Application
    Filed: August 24, 2012
    Publication date: February 27, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ru Fang, Bin He, Hui-I Hsiao, Chandrasekaran Mohan
  • Patent number: 8661222
    Abstract: Systems and methods for identifying objects generated during program execution are provided. In one embodiment, the method comprises examining one or more data structures that include information about allocation of memory space to one or more objects; determining address space allocated to at least one of said objects based on examining said data structure; populating a reverse object map based on the examining of the one or more data structures and the determining of the address space allocated to said objects, such that one or more addresses in memory are associated with an object instantiated during program execution; and determining identity of a target object accessed during program execution in association with a respective address, in response to evaluating the respective address against the reverse object map to find the target object.
    Type: Grant
    Filed: September 13, 2011
    Date of Patent: February 25, 2014
    Assignee: International Business Machines Corporation
    Inventor: Yaakov Yaari
  • Patent number: 8661192
    Abstract: A method and apparatus for refreshing data in a flash memory device is disclosed. A counter is maintained for each memory block. When a memory block is erased, the counter for that erase block is set to zero while the remaining counters are incremented. When a memory block counter reaches a predetermined threshold value, the associated memory block is refreshed.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: February 25, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Shuba Swaminathan
  • Patent number: 8661220
    Abstract: A backup is completed within a backup window designated by a user. When copying data in a first storage area, which is a backup target, to a second storage area, the capacity of a medium serving as a third storage area which is sufficient to complete a backup within the backup window, is calculated based on information about a differential bitmap describing an area in the second storage area to which the relevant data is copied from the first storage area, configuration information about a storage system where the storage areas are stored, and performance information about media constituting the storage areas; and differential data is copied using the second storage area and the third storage area; and the data written to the third storage area is copied to the second storage area.
    Type: Grant
    Filed: April 21, 2010
    Date of Patent: February 25, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Misako Kono, Nobuhiro Maki, Hironori Emaru, Junichi Hara
  • Publication number: 20140052894
    Abstract: A memory controller, system including the memory controller and method of controlling the memory. The memory controller receives requests for memory and content sensitively allocates memory space in a mixed cell memory. The memory controller allocates sufficient space including performance memory storing a single bit per cell and dense memory storing more than one bit per cell. Some or all of the memory may be selectable by the memory controller as either Single Level per Cell (SLC) or Multiple Level per Cell (MLC).
    Type: Application
    Filed: August 17, 2012
    Publication date: February 20, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bing Dai, Chung H. Lam, Jing Li
  • Publication number: 20140052908
    Abstract: Methods and structure are disclosed for normalizing storage performance across a plurality of logical volumes. One embodiment is a storage controller. The storage controller is adapted to couple with a plurality of host systems and a storage device. The storage controller is adapted to receive one or more requests to create logical volumes for the plurality of hose systems, and adapted to identify a plurality of performance zones for storage areas of the storage device. The performance zones exhibit different performance criteria for one or more of: reading data from the storage device and writing data to the storage device. The storage controller is further adapted to allocate storage from each of the plurality of performance zones for each of the plurality of logical volumes such that the performance criteria for accessing the storage device is distributed substantially uniformly across the plurality of logical volumes.
    Type: Application
    Filed: August 15, 2012
    Publication date: February 20, 2014
    Applicant: LSI CORPORATION
    Inventors: Nilesh S. Govande, Jameer Babasaheb Mulani, Brad D. Besmer, Susan Gray
  • Publication number: 20140052901
    Abstract: A memory system, system including the memory system and method of reducing memory system power consumption. The memory system includes multiple memory units allocable to one of a number of processor units, e.g., processors or processor cores. A memory controller receives requests for memory from the processor units and allocates sufficient space from the memory to each requesting processor unit. Allocated memory can include some Single Level per Cell (SLC) memory units storing a single bit per cell and other memory units storing more than one bit per cell. Thus, two processor units may be assigned identical memory space, while half, or fewer, than the number of cells of one are assigned to the other.
    Type: Application
    Filed: September 11, 2012
    Publication date: February 20, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bing Dai, Chung H. Lam, Jing Li
  • Publication number: 20140052907
    Abstract: An apparatus and associated methodology contemplate a data storage system having a removable storage device operably transferring data between the data storage system and another device via execution of a plurality of input/output (I/O) commands. A commonality factoring (CF) module executing computer instructions stored in memory assigns a CF tag to a data pattern in the transferred data. A deduplication module executing computer instructions stored in memory determines if the data pattern corresponding to the CF tag is previously stored in the removable storage device.
    Type: Application
    Filed: August 17, 2012
    Publication date: February 20, 2014
    Applicant: Spectra Logic Corporation
    Inventor: Matthew Thomas Starr
  • Patent number: 8656120
    Abstract: Disclosed is a device, method and computer-readable medium relocating Remote Procedure Call (RPC) data in a heterogeneous multiprocessor System-on-Chip (MPSoC). The method, for example, includes determining a memory where data is to be stored based on a use of a parameter of a function, and data access patterns of a function caller and a function callee, and storing the data in the determined memory.
    Type: Grant
    Filed: September 20, 2010
    Date of Patent: February 18, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung Won Lee, Young Sam Shin, Shi Hwa Lee
  • Patent number: 8656086
    Abstract: A background scheduler is provided that utilizes low-level communications (e.g., communications with a generic or controller-specific solid state, non-volatile memory driver) to control locking, reading, rewriting and unlocking of pages of data in the non-volatile memory. Such low-level communications cause data to be rewritten to the non-volatile memory independent of the file system in an effort to avoid data loss prior to an estimated data retention period.
    Type: Grant
    Filed: December 8, 2010
    Date of Patent: February 18, 2014
    Assignee: Avocent Corporation
    Inventors: Arnaldo Zimmermann, James Imoto, Livio Ceci
  • Publication number: 20140047207
    Abstract: Systems and computer program products are provided for optimizing selection of files for eviction from a first storage pool to free up a predetermined amount of space in the first storage pool. A method includes analyzing an effective space occupied by each file of a plurality of files in the first storage pool, identifying, from the plurality of files, one or more data blocks making up a file to free up the predetermined amount of space based on the analysis of the effective space of each file of the plurality of files, selecting one or more of the plurality of files as one or more candidate files for eviction, based on the identified one or more data blocks, and evicting the one or more candidate files for eviction from the first storage pool to a second storage pool.
    Type: Application
    Filed: August 13, 2012
    Publication date: February 13, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Duane Mark BALDWIN, Sandeep Ramesh PATIL, Riyazahamad Moulasab SHIRAGUPPI, Prashant SODHIYA
  • Publication number: 20140047209
    Abstract: A method and an apparatus to scan a stack for references to a heap used in executing a code via the heap are described. The heap may be allocated with fixed and varied sized slots. Each varied sized slot may be referenced by at most one fixed sized slot. Which slots are live may be identified based on the references in the stack. A fixed slot can be live if referenced by the stack. A fixed or varied slot referenced by a live slot can also be live. Varied sized slots referenced by the stack may be identified as pinned. The heap may be de-fragmented to reclaim fixed sized slots which are not live without moving live fixed sized slots and to reclaim varied sized slots which are neither live nor pinned by moving live varied slots.
    Type: Application
    Filed: August 23, 2012
    Publication date: February 13, 2014
    Inventors: Filip J. Pizlo, Geoffrey Garen, Mark Hahnenberg
  • Patent number: 8650368
    Abstract: This application concerns determining whether a particular subblock of data is present in a reduced-redundancy storage system. One embodiment achieves this by hashing subblocks in the storage system into a bitfilter that contains ‘1’ bit for each position to which at least one subblock hashes. This bitfilter provides a fast way to determine whether a subblock is in the storage system. In another embodiment, index entries for new subblocks may be buffered in a subblock index write buffer to convert a large number of random access read and write operations into a single sequential read and a single sequential write operation. The combination of the bitfilter and the write buffer yields a reduced-redundancy storage system that uses significantly less high speed random access memory than other systems that store the entire subblock index in memory.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: February 11, 2014
    Inventor: Ross Neil Williams
  • Patent number: 8650228
    Abstract: The present invention is directed toward methods and systems for data de-duplication. More particularly, in various embodiments, the present invention provides systems and methods for data de-duplication that may utilize storage reclamation. In various embodiments, data de-duplication may be performed using data storage reclamation by reconciling a list of all active tags against a list of all tags present within the object store itself. Any tags found to be in the object store that have no corresponding active usage may then be deleted. In some embodiments additional steps may be taken to avoid race conditions in deleting tags that are needed by incoming data. In some embodiments the object store may request the lists. In other embodiments, a runtime list, in which each new tag is entered as they are returned from the object store. In another embodiment the object store may maintain this list directly.
    Type: Grant
    Filed: April 14, 2008
    Date of Patent: February 11, 2014
    Inventors: Roderick B. Wideman, Stephen Philip Lord, Jeffrey D. Leuschner, Camden John Davis, John Theodore Kline, Douglas Alan Burling, Joshua Fitzsimmons Martin
  • Publication number: 20140040586
    Abstract: A method, system and computer readable medium that identify orphan storage and release the orphaned storage before application or system outages can result. More specifically, in certain embodiments, a method, system and computer readable medium periodically scan through common memory storage and identifies those areas that are no longer associated with a running task or have been allocated for longer than a running task with a matching task address. These areas are then identified as potentially orphaned storage locations.
    Type: Application
    Filed: August 1, 2012
    Publication date: February 6, 2014
    Applicant: International Business Machines Corporation
    Inventors: David B. LeGendre, David C. Reed, Esteban Rios, Max D. Smith
  • Publication number: 20140040554
    Abstract: A system and method for providing very large read-sets for hardware transactional memory with limited hardware support by monitoring meta data such as page table entries. The system and method include a Hardware-based Transactional Memory (HTM) mechanism that tracks meta-data such as page-table entries (PTE) rather than all the data itself. The HTM mechanism protects large regions of memory by providing conflict detection so that regions of memory can be located within a local read or write set.
    Type: Application
    Filed: July 31, 2012
    Publication date: February 6, 2014
    Inventors: Martin T. Pohlack, Stephan Diestelhorst
  • Publication number: 20140040589
    Abstract: One or more embodiments are directed to allocating a page to put non-shared data to the page, setting a transactional property for the page, the transactional property indicating that data in the page does not need tracking by hardware transactional memory (HTM), in response to detecting an access to the page during a transaction, determining whether the transactional property for the page is set, and in response to determining that the transactional property for the page is set, handling data loaded from the page in a cache as non-transactional data.
    Type: Application
    Filed: August 7, 2012
    Publication date: February 6, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Takeshi Ogasawara
  • Publication number: 20140040588
    Abstract: One or more embodiments are directed to allocating a page to put non-shared data to the page, setting a transactional property for the page, the transactional property indicating that data in the page does not need tracking by hardware transactional memory (HTM), in response to detecting an access to the page during a transaction, determining whether the transactional property for the page is set, and in response to determining that the transactional property for the page is set, handling data loaded from the page in a cache as non-transactional data.
    Type: Application
    Filed: August 1, 2012
    Publication date: February 6, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Takeshi Ogasawara
  • Patent number: 8645613
    Abstract: A data writing method for a flash memory and a control circuit and a storage system using the same are provided. The data writing method includes determining whether the size of data to be stored by a host system is smaller than a predetermined value according to a write command received from the host system, when the size of the data is smaller than the predetermined value, the data is written into a corresponding buffer physical block or a corresponding spare buffer physical block. The data writing method further includes combining valid data belonging to the same logical block during the executions of several write commands. Accordingly, the response time during the execution of each write command is shortened, and the problem of timeout is avoided.
    Type: Grant
    Filed: September 4, 2009
    Date of Patent: February 4, 2014
    Assignee: Phison Electronics Corp.
    Inventor: Kheng-Chong Tan
  • Patent number: 8645654
    Abstract: A method is used in selecting physical storage in data storage systems. A request for allocation of a portion of storage area of a data storage system is received from a requesting entity. The data storage system is comprised of a set of storage entities and a set of data buses for transferring data to and from the set of storage entities. The set of storage entities are organized into a set of logical units. Each logical unit of the set of logical units is subdivided into a set of slices. A slice is selected from a logical unit of the set of logical units for allocation for use by the requesting entity in response to receiving the request for allocation. The selection is based on an optimum value indicating physical location of the logical unit within the set of storage entities during access to data to be stored in the data storage system.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: February 4, 2014
    Assignee: EMC Corporation
    Inventors: Charles Christopher Bailey, Dayanand Suldhal
  • Publication number: 20140032837
    Abstract: In tiered storage subsystems in which pages are automatically allocated to appropriate storage media based on the access frequency in page units, since the number of storage media is not simply proportional to the performance, it was difficult to design in advance a tier configuration satisfying the required performance. According to the present invention, a cumulative curve of I/O distribution is created based on a result of measurement of I/O accesses performed to the storage subsystem, and RAID groups (RG) are allocated sequentially in order from RGs belonging to tiers having higher performances to the cumulative curve of I/O distribution. When either a performance limitation value or a capacity of the RG exceeds the cumulative curve of I/O distribution, a subsequent RG is allocated, and the process is repeated so as to compute the optimum tier configuration.
    Type: Application
    Filed: July 24, 2012
    Publication date: January 30, 2014
    Applicant: HITACHI, LTD.
    Inventors: Hideki Nagasaki, Hirokazu Ogasawara, Taro Ishizaki
  • Publication number: 20140032831
    Abstract: A control unit of a least recently used (LRU) mechanism for a ternary content addressable memory (TCAM) stores counts indicating a time sequence with resources in entries of the TCAM. The control unit receives an access request with a mask defining related resources. The TCAM is searched to find partial matches based on the mask. The control unit increases the counts for entries corresponding to partial matches, preserving an order of the counts. If the control unit also finds an exact match, its count is updated to be greater than the other increased counts. After each access request, the control unit searches the TCAM to find the entry having the lowest count, and writes the resource of that entry to an LRU register. In this manner, the system software can instantly identify the LRU entry by reading the value in the LRU register.
    Type: Application
    Filed: July 27, 2012
    Publication date: January 30, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Noriaki Asamoto
  • Publication number: 20140032828
    Abstract: A system, method, and computer program product are provided for copying data between memory locations. In use, a memory copy instruction is implemented. Additionally, data is copied from a first memory location to a second memory location, utilizing the memory copy instruction.
    Type: Application
    Filed: July 27, 2012
    Publication date: January 30, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Brucek Kurdo Khailany, Sean Jeffrey Treichler
  • Patent number: 8639904
    Abstract: A method and system for dynamically allocating memory, the method comprising maintaining a record of allocated memory that should be considered free in a child process, and designating as free any copy of memory identified by the record and created in a forking process.
    Type: Grant
    Filed: October 22, 2009
    Date of Patent: January 28, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Uday Kiran Jonnala, Dileep Prabhakaran Thekkemuriyil
  • Patent number: 8639871
    Abstract: A method of partitioning a data storage device that has a plurality of memory chips includes determining a number memory chips in the data storage device, defining, via a host coupled to the data storage device, a first partition of the data storage device, where the first partition includes a first subset of the plurality of memory chips, defining a second partition of the data storage device via the host where the second partition includes a second subset of the plurality of memory chips, such that the first subset does not include any memory chips of the second subset and wherein the second subset does not include any memory chips of the first subset.
    Type: Grant
    Filed: August 7, 2009
    Date of Patent: January 28, 2014
    Assignee: Google Inc.
    Inventors: Albert T. Borchers, Andrew T. Swing, Robert S. Sprinkle
  • Patent number: 8639892
    Abstract: Circuits, methods, and apparatus that inhibit the collection or updating of page characteristics where such information is not useful. One example inhibits the updating of page usage information for pages that are to be kept resident in memory and not swapped to disk. The pages for which page usage or other characteristic updates are to be suppressed can be identified in a number of ways, including using a set range of addresses, bits in page directory entries, bits in page table entries, one or more address registers, or one or more segments.
    Type: Grant
    Filed: December 15, 2006
    Date of Patent: January 28, 2014
    Assignee: NVIDIA Corporation
    Inventor: Nicholas P. Wilt
  • Publication number: 20140025916
    Abstract: When a plurality of applications operating in a host computer or a storage system uses a same pool, actual data constantly allocated to an upper tier drive satisfying the required response performance will continue to increase. Therefore, when data is migrated by IOPS in page units, the access performance such as the response speed may not be satisfied. Therefore, according to the present invention, multiple virtual volumes used in applications are subjected to grouping. Relocation conditions corresponding to performances required for each group are set in advance, and reallocation of tiers according to the relocation conditions is performed.
    Type: Application
    Filed: July 18, 2012
    Publication date: January 23, 2014
    Applicant: HITACHI, LTD.
    Inventors: Yutaka Oshima, Yutaka Takata, Yoshinori Ohira
  • Patent number: 8635415
    Abstract: A set of default registers of a processor are expanded into metadata registers on the processor of a computer system. The default registers having stored thereon data, while metadata which is related to the data is stored separately on the metadata registers.
    Type: Grant
    Filed: September 30, 2009
    Date of Patent: January 21, 2014
    Assignee: Intel Corporation
    Inventors: Baiju V. Patel, Rajeev Gopalakrishna, Andrew F. Glew, Robert J. Kushlis, Don Alan Van Dyke, Joseph Frank Cihula, Asit K. Mallick, James B. Crossland, Gilbert Neiger, Scott Dion Rodgers, Martin Guy Dixon, Mark Jay Charney, Jacob (Koby) Gottlieb
  • Publication number: 20140019709
    Abstract: Methods and systems are disclosed for distributed storage systems. For example, a device can receive a read request for a first file, where the read request is generated by a host device. The read request is configured to access a file on the host device. The device can access mappings to identify a first mapping. The device can identify a first file on a mobile device based on the first mapping. The device can access the first file, where the accessing uses the first mapping. The device can access the first file by communicating with the mobile device to read the first file. The device can then return the first file.
    Type: Application
    Filed: July 16, 2012
    Publication date: January 16, 2014
    Applicant: Plair Media Inc.
    Inventors: Syed Saadullah Hussain, Todd Steven Wheeler
  • Publication number: 20140019706
    Abstract: A virtual allocation unit is allocated in a virtual address space corresponding to a filesystem, in response to an allocation requirement, related to a logical object in the filesystem. The size of the virtual allocation unit is determined in accordance with the current physical size of the logical object. The size of the virtual allocation unit is substantially larger than a size required with respect to the allocation requirement. Physical block address ranges are allocated in a physical storage space, in response to subsequent write requests, related to the logical object. Each physical block address range is associated with a respective portion of the virtual allocation unit.
    Type: Application
    Filed: July 16, 2012
    Publication date: January 16, 2014
    Applicant: INFINIDAT LTD.
    Inventor: Arnon Kanfi
  • Publication number: 20140019707
    Abstract: A mechanism is provided in a storage device for performing a write operation. The mechanism configures a write buffer memory with a plurality of write buffer portions. Each write buffer portion is dedicated to a predetermined block size category within a plurality of block size categories. For each write operation from an initiator, the mechanism determines a block size category of the write operation. The mechanism performs each write operation by writing to a write buffer portion within the plurality of write buffer portions corresponding to the block size category of the write operation.
    Type: Application
    Filed: July 16, 2012
    Publication date: January 16, 2014
    Applicant: International Business Machines Corporation
    Inventors: Michael T. Benhase, Andrew D. Walls
  • Publication number: 20140019708
    Abstract: Provided are a computer program product, system, and method for granting and revoking supplemental memory allocation requests. Supplemental memory allocations of memory resources are granted to applications following initial memory allocations of the memory resources to the applications. In response to determining that available memory resources have fallen below an availability threshold, determining a weighting factor for each supplemental memory allocation based on at least one of an amount of the memory resources allocated to the supplemental memory allocation and a measured duration during which the memory resources have been allocated. At least one of the supplemental memory allocations is selected to revoke based on the determined weighting factors of the supplemental memory allocations.
    Type: Application
    Filed: July 12, 2012
    Publication date: January 16, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Derek Logan Erdmann, David C. Reed, Thomas C. Reed, Max D. Smith
  • Patent number: 8631221
    Abstract: Methods and apparatus for allocating host memory for use by a host channel adapter (HCA) with insufficient on-board memory are disclosed. In one embodiment, a method includes determining when a host memory arrangement which has a host memory updates a system address map associated with the host memory, and obtaining control from a system basic-input-output-system (BIOS) associated with an operating system (OS) of the host memory arrangement when the system address map is updated. The method also includes allocating a first memory block in the host memory using an add-on device after obtaining control from the host memory arrangement. The system address map is updated by the add-on device to indicate that the first memory block has been allocated to the add-on device. Finally, the method includes returning the control to the system BIOS after updating the system address map.
    Type: Grant
    Filed: February 22, 2008
    Date of Patent: January 14, 2014
    Assignee: Cisco Technology, Inc.
    Inventor: Vetrivelan Krishnan
  • Patent number: 8631051
    Abstract: A method of managing memory, and a system implementing the method, are disclosed herein. In one embodiment according to the invention, the method comprises the step of allocating a first space, a first semi-space and a second semi-space of a memory unit. The first space has a first space size, and the first and second semi-spaces have a semi-space size. The first object is transformed into a plurality of elements and a spine containing pointers to the plurality of elements. The plurality of elements are stored in the first space and the spine in one of the first semi-space and the second semi-space. First memory portions of the first space are reclaimed using a mark-sweep policy and second memory portions of one of the first semi-space and the second semi-space are reclaimed using a moving policy.
    Type: Grant
    Filed: September 22, 2009
    Date of Patent: January 14, 2014
    Inventor: Filip Pizlo
  • Patent number: 8626987
    Abstract: Provided is a flash memory system supporting flash defragmentation. The flash memory system includes a host and a flash storage device. In response to a flash defragmentation command by the host, the flash storage device performs flash defragmentation by grouping fragments stored in fragmented blocks of a flash memory on a flash memory management unit basis. The flash memory management unit may be a memory block or page. The flash storage device performs the flash defragmentation regardless of the arrangement order of fragmented files stored in the flash memory.
    Type: Grant
    Filed: October 27, 2010
    Date of Patent: January 7, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dawoon Jung, Moon Sang Kwon, Dong Jun Shin
  • Patent number: 8627017
    Abstract: A method and apparatus for monitoring memory accesses in hardware to support transactional execution is herein described. Attributes are monitor accesses to data items without regard for detection at physical storage structure granularity, but rather ensuring monitoring at least at data items granularity. As an example, attributes are added to state bits of a cache to enable new cache coherency states. Upon a monitored memory access to a data item, which may be selectively determined, coherency states associated with the data item are updated to a monitored state. As a result, invalidating requests to the data item are detected through combination of the request type and the monitored coherency state of the data item.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: January 7, 2014
    Assignee: Intel Corporation
    Inventors: Gad Sheaffer, Shlomo Raikin, Vadim Bassin, Raanan Sade, Ehud Cohen, Oleg Margulis
  • Publication number: 20140006745
    Abstract: Memory pages are selected for compression based on the population count associated with their datasets. For example, a dataset stored in a memory page of an uncompressed memory is analyzed. Based on the analyzing, a population count associated with the dataset is calculated. The population count is compared to at least one threshold. Based on the comparing, the memory page is selected or rejected for compression.
    Type: Application
    Filed: June 29, 2012
    Publication date: January 2, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Nathan D. FONTENOT, Jeffrey David GEORGE, Ryan P. GRIMM, Joel H. SCHOPP, Michael T. STROSAKER
  • Publication number: 20140006898
    Abstract: A system and method for partitioning data in long term memory of a flash memory device is disclosed. The method may include the steps of identifying a type of data that has been received and routing the data to one of at least two partitions in the long term memory array. One partition of the flash memory device may be optimized for random data while another is optimized for sequential data. The method includes identifying the type of data and routing the data to the appropriate partition. Data may be analyzed and routed upon receipt or initially stored in a default partition and later analyzed and routed to another partition. The partition for random data may be configured for storing data using a first level of ECC protection while the second may be configured for storing data using a second, stronger level of ECC protection.
    Type: Application
    Filed: July 2, 2012
    Publication date: January 2, 2014
    Inventors: Eran Sharon, Idan Alrod