Abstract: An apparatus comprising a controller, one or more host devices and one or more storage devices. The controller may be configured to store and/or retrieve data in response to one or more input/output requests. The one or more host devices may be configured to present the input/output requests. The one or more storage devices may be configured to store and/or retrieve the data. The controller may include a cache memory configured to store the input/output requests. The cache memory may be configured as a memory allocation table to store and/or retrieve a compressed version of a portion of the data in response to one or more network parameters. The compressed version may be retrieved from the memory allocation table instead of the storage devices based on the input/output requests to improve overall storage throughput.

Abstract: A physical storage volume can be partitioned into a plurality of master blocks of an equal master block size. Each master block of the plurality of master blocks can be allocated for storage of a single storage page size of a plurality of predefined storage page sizes provided for storage of data by a data storage application. A received page size can be determined for a storage page designated by the data storage application for storage on the physical storage volume, and the storage page can be stored in a free block of a master block of the plurality of master blocks having the single page size equivalent to the received page size. Related methods, systems, and articles of manufacture are also disclosed.

Abstract: Disclosed are a method and system for measuring the performance of individual logical partitions of a logically partitioned computer system. Preferably, the method and system both hardware and firmware to allow measurement samples to be collected only for user specified zones of interest. In one embodiment, the method comprises the steps of specifying a Zone or Zones of interest (a Zone being a logical partition), collecting measurement samples only from the one or more specified Zones of interest, and measuring the performance of each of these Zones using only the measurement samples collected from said each of the Zones.

Abstract: Embodiments of the present technology are directed toward techniques for enabling different memory partitions to have different memory depths.

Abstract: A plurality of memory devices of mixed type (e.g., DRAMs, SRAMs, MRAMs, and NAND-, NOR-, AND-type Flash memories) are serially interconnected. Each device has device type information on its device type. A specific device type (DT) and a device identifier (ID) contained in a serial input are fed to one device of the serial interconnection configuration. The device determines whether the fed DT matches the DT of the device. In a case of match, a calculator included in the device performs calculation to generate an ID for another device and the fed ID is latched in a register of the device. The generated ID is transferred to another device of the serial interconnection. In a case of no match, the ID generation is skipped and no ID is generated for another device. Such a device type match determination and ID generation or skip are performed in all devices of the serial interconnection.

Abstract: Systems, devices, memory controllers, and methods for initializing memory are described. Initializing memory can include configuring memory devices in parallel. The memory devices can receive a shared enable signal. A unique volume address can be assigned to each of the memory devices.

Abstract: A storage system connected to a computer and a management computer, includes storage devices accessed by the computer, and a control unit for controlling the storage devices. A first-type logical device corresponding to a storage area set in at least one of the storage devices and a second-type logical device that is a virtual storage area are provided. The control unit sets at least two of the first-type logical devices different in a characteristic as storage areas included in a storage pool through mapping. The first-type logical device stores data by allocating a storage area of the second-type logical device to a storage area of the first-type logical device mapped to the storage pool. The characteristic of the second-type logical device can be changed by changing the allocated storage area of the second-type logical device to a storage area of another first-type logical device.

Abstract: A method for expanding memory size is provided in the illustrative embodiments. A desired size of an expanded memory and a first information about a workload in the data processing system are received. A size of a compressed memory pool to use with the memory to make the desired size of the expanded memory available is computed. A representation of the memory is configured, the representation of the memory appearing to be of a size larger than the size of the memory, the representation of the memory being the expanded memory, and the size of the representation being the size of the expanded memory. The expanded memory is made available such that the memory in the data processing system is usable by addressing the expanded memory.

Abstract: A method is presented for using a hard disk drive which contains a non-volatile random access memory (NVRAM) and a computer-usable disk medium. A usage value is maintained for the number of accesses to the computer-usable disk medium, and the usage value is stored within the NVRAM. In a system that is connected to multiple hard disk drives, the usage values for the hard disk drives can be compared to determine a youngest disk drive or a lowest amount of usage amongst the multiple hard disk drives. When data needs to be mirrored or backed-up to one of the hard disk drives, it can be copied to the youngest or least-used hard disk drive. If an operating system installation needs to be performed, the operating system files can be stored on the youngest or least-used hard disk drive.

Abstract: A method for concurrently converting a standard volume to a thin-provisioned volume includes initially establishing metadata for a thin-provisioned volume. The method then updates the metadata for the thin-provisioned volume to point to extents residing in a standard volume. The method then suspends I/O to metadata for the standard volume. Upon suspending the I/O, the method migrates control of the extents in the standard volume from a standard-volume control algorithm to a thin-provisioned-volume control algorithm. The method then resumes the I/O to the metadata for the thin-provisioned volume. Using this technique, standard volumes may be rapidly converted to thin-provisioned volumes while minimally disrupting I/O to the volumes. A corresponding apparatus and computer program product are also disclosed and claimed herein.

Abstract: A method to implement parallel, single-pass compaction in a garbage collector is described. In one embodiment, such a method includes conducting a planning phase for multiple regions to be compacted. During the planning phase, the method determines new locations for data entities in the multiple regions. The method then performs a move phase for the multiple regions to move the data entities to their new locations. During the move phase, the method initiates multiple compaction threads to move the data entities to their new locations. While executing, the compaction threads dynamically build a dependency graph of the regions being compacted. The dependency graph guarantees that no data entity is moved to its new location until all data entities that it overwrites have been moved to their new locations. A corresponding computer program product and apparatus are also disclosed and claimed herein.

Abstract: A memory device includes a plurality of memory modules and a memory management module. A memory module of the plurality of memory modules includes a plurality of memory cells and a memory millimeter wave (MMW) transceiver. The memory management module determines a main memory configuration for at least some of the plurality of memory modules. The memory management module also determines physical addresses for the main memory configuration and determines a MMW communication resource table that includes an allocation mapping of one or more MMW communication resources to one or more of the at least some of the plurality of memory modules.

Abstract: A memory module is coupled to a number of controllers. The memory module is configured to configure each of a number of data input/output ports thereof as at least one of an input and an output in response to a first command from a particular controller of the controllers. The memory module is configured to partition itself into memory partitions in response to a second command from the particular controller so that each memory partition corresponds to a respective one of the controllers. Each of a number of data input/output ports of the controllers is configurable as at least one of an input and an output to correspond to a respective one of the input/output ports of the memory module. The first and second commands may originate from the particular controller, or the controllers may be coupled in parallel to the memory module.

Abstract: A computer-implemented modular planning tool and method are provided which allow a line item (50) to be joined to another line item (50) so that data attributes (54), data structure (56) and data contained in the data structure (56) are shared by both line items (50). This is achieved using a join attribute of a line item (50) to point to another line item (50).

Abstract: A method and a system for configuring mirrors of virtual storage devices in a virtual host includes obtaining a topology connection relationship between the virtual storage devices to be configured with mirrors and the virtual host, where the topology connection relationship is a hierarchical relationship in a tree shape with the virtual host as a root node and the virtual storage devices to be configured with mirrors as leaf nodes, and configuring the mirrors of the virtual storage devices to be configured with mirrors in the virtual host according to the obtained topology connection relationship. The method and the system for configuring mirrors of virtual storage devices in a virtual host can increase reliability.

Abstract: An operating system switching method is provided. The operating system switching method is for a computer system comprising a control unit, a memory unit, and a storage unit, wherein the storage unit comprises a first operating system and a second operating system. The steps of the method include: loading the first operating system and the second operating system into a first memory space and a second memory space of the memory unit, respectively, and setting the first memory space and the second memory space to a working state and a standby state, respectively; and performing a first switching of the operating systems, and setting the first memory space and the second memory space to the standby state and the working state.

Abstract: A RAID storage array having a controller and plurality of disk drives is configured into a plurality of groups. The plurality of disk drives are in a plurality of drive trays. The controller includes a main memory. A set of configuration information is stored on a central nonvolatile memory device. The set of configuration information includes group configuration information corresponding to each group of the plurality of groups with which a corresponding disk drive is associated. The set of configuration information is stored on a plurality of remote nonvolatile memory devices that are each associated with at least one of the plurality of drive trays. A bootware control process is loaded into the main memory. The bootware control process is executed. A plurality of service layer processes are loaded into the main memory. The plurality of service layer processes are executed in parallel under the control of the bootware control process.

Abstract: A memory system is described having a memory, at least one memory area of the memory being able to be configured as data memory or as buffer store as a function of a required memory processing rate.

Abstract: Systems and methods, including computer software stored on a machine-readable medium for performing operations, can be implemented for allocating memory. Multiple channels are defined on a mobile device. Each channel can be adapted to receive a predetermined type of content for access on the mobile device. An amount of memory allocated to each channel for storing data is defined. Data identifying a new amount of memory allocated to one of the channels is received, and the amount of memory allocated to the channel is adjusted based on the data identifying the new amount of memory.

Abstract: Techniques for incrementing counters in an efficient manner. In one set of embodiments, counter logic circuits are provided that can operate at higher frequencies than existing counter logic circuits, while being capable of being implemented in currently available field programmable gate arrays (FPGAs) or fabricated using currently available process technologies. The counter logic circuits of the present invention may be used to increment statistics counters in network devices that support line speeds of 40 Gbps, 100 Gbps, and greater.

Abstract: Systems and methods are disclosed in which a derived table can inherit a growth pattern from a template table. A growth pattern is used to define how memory is allocated to a table as the table grows. The derived table can inherit the growth pattern defined by its template table or it can provide an override growth pattern. Inheritance of the growth pattern can be performed by explicit copying or by reference or link. Growth patterns can be edited, and the edits can be applied universally or locally.

Abstract: A system for controlling access to resources in an apparatus when the apparatus is not active. Emerging technologies may allow information to be accessed in an apparatus memory without the operating system of the apparatus facilitating the access. In such instances, a subsystem in the apparatus may become active upon reception of wireless signals, and may grant direct access to memory. An access control configuration for the subsystem may be implemented in order to control memory access even when other software systems are inactive. The subsystem access control configuration may be configured (e.g., by the user) when the apparatus is active, and may be established (e.g., installed or updated) upon subsystem activation.

Abstract: Methods and structure for automated determination and reconfiguration of the size of a cache memory in a storage system. Features and aspects hereof generate historical information regarding frequency of hits on cache lines in the cache memory. The history maintained is then analyzed to determine a desired cache memory size. The historical information regarding cache memory usage may be communicated to a user who may then direct the storage system to reconfigure its cache memory to a desired cache memory size. In other embodiments, the storage system may automatically determine the desired cache memory size and reconfigure its cache memory. The method may be performed automatically periodically, and/or in response to a user's request, and/or in response to detecting thrashing caused by least recently used (LRU) cache replacement algorithms in the storage system.

Abstract: A method for configuring a large hybrid memory subsystem having a large cache size in a computing system where one or more performance metrics of the computing system are expressed as an explicit function of configuration parameters of the memory subsystem and workload parameters of the memory subsystem. The computing system hosts applications that utilize the memory subsystem, and the performance metrics cover the use of the memory subsystem by the applications. A performance goal containing values for the performance metric is identified for the computing system. These values for the performance metrics are used in the explicit function of performance metrics, configuration parameters and workload parameters to calculate values for the configuration parameters that achieve the identified performance goal. The calculated values of the configuration parameters are implemented in the memory subsystem.

Abstract: A storage device that stores at least one of video data and audio data comprising: a storage medium having a total storage area divided into multiple divided storage areas; a storage processing unit that selects a divided storage area other than a divided storage area that is most recently subjected to storage processing among the multiple divided storage areas, and stores, in a selected divided area, at least one of the video data and the audio data corresponding to a storage period unit; and a divided storage area control unit that performs initialization processing or defragmentation processing to the divided storage area which stores at least one of the video data and the audio data corresponding to the storage period unit.

Abstract: System and method for using flash memory in a memory hierarchy. A computer system includes a processor coupled to a memory hierarchy via a memory controller. The memory hierarchy includes a cache memory, a first memory region of random access memory coupled to the memory controller via a first buffer, and an auxiliary memory region of flash memory coupled to the memory controller via a flash controller. The first buffer and the flash controller are coupled to the memory controller via a single interface. The memory controller receives a request to access a particular page in the first memory region. The processor detects a page fault corresponding to the request and in response, invalidates cache lines in the cache memory that correspond to the particular page, flushes the invalid cache lines, and swaps a page from the auxiliary memory region to the first memory region.

Abstract: An object of the invention is to provide a memory control unit and a memory control method capable of making the operation setting of SDRAM without intentionally stopping access to the SDRAM. A switch signal generation section (18) for generating a switch signal to switch the operation setting of SDRAM (200), a switch control section (16) for switching the operation setting of the SDRAM (200) using a switch setup value (17) as the switch signal is output from the switch signal generation section (18), and an access control section (14) for suppressing acceptance of an access request to the SDRAM (200) in the time period from the switch start time of the operation setting to the switch completion time are provided. Accordingly, when the operation setting of the SDRAM (200) is changed, it is not necessary to intentionally stop access to the SDRAM (200) and it is made possible to change the operation setting of the SDRAM (200) without being affected by the access situation to the SDRAM (200).

Abstract: Managing multiple object areas in a memory heap, comprises allocating a memory heap as a contiguous range of memory, allocating a small object area within the memory heap having an initial start at a first end of the memory heap and allocating a large object area within the memory heap having an initial start at a second end of the memory heap opposite the first end such that the small object area and the large object area grow in opposite directions inward within the memory heap. Further, allocations are performed into the memory heap based upon a predetermined allocation policy such that the large object area is reserved for the allocation of large objects.

Abstract: Methods and systems for mapping data-management requirements to the provisioning of a data storage system to conform to a set of user-defined data-management policies. A conformance engine with storage system awareness translates the set of data-management policies to a corresponding set of storage-provisioning policies and provisions the resources of the storage system thereby to conform the storage system to the data-management policies. A conformance checker continuously and automatically compares the provisioning of the storage system resources to the provisioning required to meet the data-management policies. When nonconformance is detected, the conformance engine automatically re-provisions the available resources of the storage system to conform the storage system to the data management policies.

Abstract: A methodology for a daisy-chained memory topology wherein, in addition to the prediction of the timing of receipt of a response from a memory module (DIMM), the memory controller can effectively predict when a command sent by it will be executed by the addressee DIMM. By programming DIMM-specific command delay in the DIMM's command delay unit, the command delay balancing methodology according to the present disclosure “normalizes” or “synchronizes” the execution of the command signal across all DIMMs in the memory channel. With such ability to predict command execution timing, the memory controller can efficiently control power profile of all the DRAM devices (or memory modules) on a daisy-chained memory channel.

Abstract: A storage tool can determine and provide an abstract view of storage systems in a network of computing system. The storage tool can utilize the abstract view in order to identify the storage systems based on the performance and capabilities of the storage systems without regard to the configuration of the storage system, storage devices in the storage system, or the details of the storage devices.

Abstract: A method for data distribution, including distributing logical addresses among an initial set of devices so as provide balanced access, and transferring the data to the devices in accordance with the logical addresses. If a device is added to the initial set, forming an extended set, the logical addresses are redistributed among the extended set so as to cause some logical addresses to be transferred from the devices in the initial set to the additional device. There is substantially no transfer of the logical addresses among the initial set. If a surplus device is removed from the initial set, forming a depleted set, the logical addresses of the surplus device are redistributed among the depleted set. There is substantially no transfer of the logical addresses among the depleted set. In both cases the balanced access is maintained.

Abstract: There is provided a storage control system and a method in which various controls to a plurality of storage controllers connected to each other can be effectively performed. The storage control system and method controls first and second storage controllers, in which a second storage controller is connected to a first storage controller to which a host system is connected. With reference to a memory in which a table defining correspondence relationships between internal logical volumes and a host logical volume of the second storage controller is stored, a channel adapter of the first storage controller controls power supplies of driving mechanisms of storage devices corresponding to the internal logical volumes.

Abstract: A system and method are provided for pooling storage devices in a virtual library for performing a storage operation. A storage management device determines a storage characteristic of a plurality of storage devices with respect to performing a storage operation. Based on a storage characteristic relating to performing the storage operation, the storage management device associates at least two storage devices in a virtual library. The storage management device may continuously monitor the virtual library and detect a change in storage characteristics of the storage devices. When changes in storage characteristics are detected, the storage management device may change associations of the storage device in the virtual library.

Abstract: This storage apparatus that provides to a host computer a logical device for storing data sent from the host computer includes a nonvolatile memory for storing the data, a disk-shaped memory device for storing the data, and a controller for controlling the nonvolatile memory and the disk-shaped memory device. The controller redundantly configures the logical device with the nonvolatile memory and the disk-shaped memory device.

Abstract: Register halves are allocated independently when performing register allocation during program compilation, thereby effectively doubling the number of registers which are available for allocation, which in turn may reduce spill code and improve run-time performance. When hardware registers are 64 bits wide, for example, an architecture supporting the present invention provides some number of separate hardware instructions that operate on the 32-bit high-word and/or the 32-bit low word of the hardware registers as if those 32-bit words are separate registers. Such hardware instructions are able to manipulate the register halves independently, leaving the other register half untouched. A register coloring algorithm using in the compilation process is invoked using the number of register halves, instead of the number of hardware registers.

Abstract: A memory and a method for controlling a memory including: a set of first memory blocks of identical size, intended to contain first words, a set of second memory blocs of identical size, intended to contain second words, the number of second words being identical to the number of first words, a third memory block identical to the first blocks, a fourth memory block identical to the second blocks, each memory address comprising a first portion identifying a same line in all blocks, and each first word of the third block identifying a free word from among the second words sharing a same second address portion.

Abstract: A data management device includes a memory configured to save data and a processor. The processor is configured to save acquired data into the memory when the save command is received. The processor is further configured to execute a process which processes the data acquired by the acquisition unit when the specific command is received. The process is different from saving the data into the memory. The processor is still further configured to generate a first data name in accordance with a first rule and attach the first data name to the acquired data. Moreover, the processor is configured to generate a second data name in accordance with a second rule different from the first rule and attach the second data name to the acquired data.

Abstract: A hardware description language (HDL) design structure embodied on a machine-readable data storage medium includes elements that when processed in a computer aided design system generates a machine executable representation of a device for implementing dynamic refresh protocols for DRAM based cache. The HDL design structure further includes a DRAM cache partitioned into a refreshable portion and a non-refreshable portion; and a cache controller configured to assign incoming individual cache lines to one of the refreshable portion and the non-refreshable portion of the cache based on a usage history of the cache lines; wherein cache lines corresponding to data having a usage history below a defined frequency are assigned by the controller to the refreshable portion of the cache, and cache lines corresponding to data having a usage history at or above the defined frequency are assigned to the non-refreshable portion of the cache.

Abstract: A method and apparatus for auto-tuning memory is provided. Memory on a computer system comprises at least one shared memory area and at least one private memory area. Addresses in the shared memory area are accessible to multiple processes. Addresses in the private memory area are dedicated to individual processes. Initially, a division in the amount of memory is established between the shared and private memory areas. Subsequently, a new division is determined. Consequently, memory from one memory area is “given” to the other memory area. In one approach, such sharing is achieved by causing the shared and private memory areas to be physically separate from each other both before and after a change in the division. The division of the amount of memory may be changed to a new division by deallocating memory from one of the memory areas and allocating that memory to the other of the memory areas.

Abstract: An underlying physical volume of a storage system is an aggregate having a plurality of storage devices. The aggregate has its own physical volume block number (pvbn) space. A file system layout apportions the underlying physical volume into a plurality of virtual volumes of the storage system each having a virtual volume identification (vvid). Each virtual volume has its own virtual volume block number (vvbn) space. The block allocation structures of a virtual volume are sized to the virtual volume, and not to the underlying aggregate, to thereby allow operations that manage data served by the storage system (e.g., snapshot operations) to efficiently work over the virtual volumes. Each storage block in a virtual volume is identified by the triplet: pvbn, vvid, and vvbn.

Abstract: Tracking dynamic memory de-allocation using a single configuration table having a first register and a second register includes setting the first register as an active register, initiating a de-allocation of desired storage increments from a memory partition, setting the storage increments in the second register as invalid, purging all caches associated with the single configuration table, setting the second register as the active register and the first register as an inactive register, setting the desired storage increments in the first register as invalid, switching the active register from the second register to the first register to complete memory de-allocation using the single configuration table.

Abstract: Systems and methods are provided for selectively retiring blocks based on refresh events of those blocks. In addition to refresh events, other criteria may be applied in making a decision whether to retire a block. By applying the criteria, the system is able to selectively retire blocks that may otherwise continue to be refreshed.

Abstract: A plurality of processors in a multiprocessor circuit is electrically connected to a plurality of independently addressable memory banks via a connection circuit. The connection circuit is arranged to forward addresses from a combination of the processors to addressing inputs of memory banks selected by the addresses. The connection circuit provides for a conflict resolution scheme wherein at least one of the processors is associated with one of the memory banks as an associated processor. The connection circuit guarantees the associated processor a higher minimum guaranteed access frequency to the associated memory banks than to non-associated memory banks. A defragmenter detects data associated with a task running on the associated processor that is stored on one of the memory banks and moves the data to the associated memory banks during execution of the task.

Abstract: There is provided a storage control system in which various controls to a plurality of storage controllers connected to each other can be effectively performed. The storage control system controls first and second storage controllers, in which a second storage controller 10 is connected to a first storage controller 1-1 to which a host system 1-2 is connected. With reference to a memory in which a table defining correspondence relationships between internal logical volumes and a host logical volume 32 of the second storage controller 10 is stored, a channel adapter 1-3 of the first storage controller 1-1 controls power supplies of driving mechanisms of storage devices corresponding to the internal logical volumes.

Abstract: A data storage device comprising at least one non-volatile storage medium having a plurality of data blocks, and a controller configured to allocate at least one of the data blocks for a writing operation based at least in part on data integrities of the data blocks.

Abstract: An apparatus includes a processor; a volatile, high-to-low working memory partition connected to the processor; a volatile, low-to-high working memory partition connected to the processor; a high-side, input/output section providing an interface to a high-side network or data bus, and configured to send messages to the high-to-low working memory, and to receive messages from the low-to-high working memory; a low-side, input/output section providing an interface to a low-side network or data bus, and configured to send messages to the low-to-high working memory, and to receive messages from the high-to-low working memory; a first non-volatile memory for storing a rule set binary image, whereby the processor controls the transfer of messages between the high-side input/output section and the low-side input/output section in accordance with the rule set; and a second non-volatile, memory for storing firmware for controlling executive functions of the apparatus.

Abstract: For address management of a nonvolatile memory, the whole logical address space is divided into logical address ranges (0 to 15), and the physical address space is divided into physical areas (segments (0 to 15)). The logical address ranges are respectively associated with the physical areas (segments) to manage the addresses. The sizes of the logical address ranges are equalized. The size of the physical area (segment (0)) corresponding to the logical address range (0) in which data of high rewrite frequency such as an FAT is expected to be stored is larger than those of the other physical areas, and the logical address ranges and the physical areas are allocated. Alternatively, the sizes of the physical areas are equalized, and the size of the logical address range (0) is set as a smaller one than those of the other logical address ranges. With this, the actual rewrite frequencies of the physical areas (segments) are equal to one another, and consequently the life of the nonvolatile memory can be prolonged.

Abstract: A controlling circuit applicable in a physical storage device includes: a dividing circuit coupled to the physical storage device for dividing a storage capacity of the physical storage device into a plurality of divided storage areas, wherein a divided storage capacity of each divided storage area is not larger than the capacity corresponding to the largest address generated by an operating system; and a feedback circuit coupled to the dividing circuit for feeding back the plurality of divided storage areas to the operating system such that the operating system regards the plurality of divided storage areas as a plurality of independent physical storage devices.

Abstract: To maintain reliability even when the repetition of the power saving control for storage systems occurs frequently due to the access from the host computer. During the course of controlling the operation mode of the drives, the controller measures the start/stop cycle count and the load/unload cycle count, calculates the S/S wear-out rate showing the ratio of the measured value of the start/stop cycle count to the first upper limit value and the L/U wear-out rate showing the ratio of the measured value of the load/unload cycle count to the second upper limit value, and for the drives in the idle operation mode, selects the low-speed rotation operation mode if the S/S wear-out rate is greater than the L/U wear-out rate, or selects the standby operation mode if the S/S wear-out rate is less than the L/U wear-out rate.