Abstract: Systems, methods, and apparatuses relating to hardware control of processor performance levels are described. In one embodiment, a processor includes a plurality of logical processing elements; and a power management circuit to change a highest non-guaranteed performance level and a highest guaranteed performance level for each of the plurality of logical processing elements, and set a notification in a status register when the highest non-guaranteed performance level is changed to a new highest non-guaranteed performance level.

Abstract: A method for clearing a register, including: causing the PLD to set preset bits of a first register and a second register as an invalid state, detect whether a command is received from a MCU; when the command being received, parsing the command and determining whether a reading or writing event is triggered; when the reading event being triggered, setting the preset bit of the first register as a valid state, reading data of the preset bit of the first register, postponing clearing, by the PLD, the preset bit of the first register for a preset time; when the writing event being triggered, setting the preset bit of the second register as the valid state, writing, by the MCU, data into the preset bit of the second register, causing the PLD to acquire the data, postpone clearing the preset bit of the second register for a second preset time.

Abstract: Multilevel command and address (CA) signals are used to provide commands and memory addresses from a controller to a memory system. Using multilevel signals CA signals may allow for using fewer signals compared to binary signals to represent a same number of commands and/or address space, or using a same number of multilevel CA signals to represent a larger number of commands and/or address space. A number of external command/address terminals may be reduced without reducing a set of commands and/or address space. Alternatively, a number of external terminals may be maintained, but provide for an expanded set of commands and/or address space.

Abstract: Multilevel command and address (CA) signals are used to provide commands and memory addresses from a controller to a memory system. Using multilevel signals CA signals may allow for using fewer signals compared to binary signals to represent a same number of commands and/or address space, or using a same number of multilevel CA signals to represent a larger number of commands and/or address space. A number of external command/address terminals may be reduced without reducing a set of commands and/or address space. Alternatively, a number of external terminals may be maintained, but provide for an expanded set of commands and/or address space.

Abstract: Devices, methods and articles advantageously allow communications between qubits to provide an architecture for universal adiabatic quantum computation. The architecture includes a first coupled basis A1B1 and a second coupled basis A2B2 that does not commute with the first basis A1B1.

Abstract: Operations include determining whether to cache resources accessed by a query based on the execution time of the query. The system identifies a set of executions of a same query. The system determines a cumulative execution time for the set of executions of the same query. If the cumulative execution time exceeds a threshold value, then the system caches a resource used for execution of the query.

Abstract: Quantum processors having qubits with tunable capacitance are provided. The qubits include Josephson junctions shunted by capacitors and are tunably coupled to capacitance loops such that the resonant frequencies of the qubits and capacitance loops avoid entanglement with each other. Methods for tuning the capacitance of such qubits by varying the coupler's coupling strength are provided. These methods include methods for calibrating qubits' capacitance.

Abstract: Methods, systems, and computer program products for identifying microservices from a monolith application through static code analysis are provided herein. A method includes performing a static code analysis to extract multiple features of a monolith application; partitioning code elements of the monolith application into multiple groups using an agglomerative clustering process, wherein the agglomerative clustering process is based on the extracted multiple features and a set of clustering metrics; obtaining at least one weight corresponding to one or more of: at least one of the multiple features and at least one of the multiple groups; adjusting the groups based on the at least one weight; generating a list of candidate microservices for the monolith application, wherein each candidate microservice in the list corresponds to a different one of the adjusted multiple groups; and outputting the list of candidate microservices to at least one of a system and a user.

Abstract: The present disclosure is related to performing speculation in, for example, a memory device or a computing system that includes a memory device. Speculation can be used to identify data that is accessed together or to predict data that will be accessed with greater frequency. The identified data can be organized to improve efficiency in providing access to the data.

Abstract: Methods and systems for analysis of image data generated from various reference points. Particularly, the methods and systems provided are useful for real time analysis of image and sequence data generated during DNA sequencing methodologies.

Abstract: A computer-implemented method can measure query locality during execution of a plurality of incoming queries in a database management system. The database management system includes a query execution plan cache which has a size that can store at least some of query execution plans generated for the plurality of incoming queries. Based on the measured query locality, the method can adjust the size of the query execution plan cache.

Abstract: Described herein are techniques for performing compilation operations for heterogeneous code objects. According to the techniques, a compiler identifies architectures targeted by a compilation unit, compiles the compilation unit into a heterogeneous code object that includes a different code object portion for each identified architecture, performs name mangling on functions of the compilation unit, links the heterogeneous code object with a second code object to form an executable, and generates relocation records for the executable.

Abstract: A multi-core processor configured to improve processing performance in certain computing contexts is provided. The multi-core processor includes multiple processing cores that implement barrel threading to execute multiple instruction threads in parallel while ensuring that the effects of an idle instruction or thread upon the performance of the processor is minimized. The multiple cores can also share a common data cache, thereby minimizing the need for expensive and complex mechanisms to mitigate inter-cache coherency issues. The barrel-threading can minimize the latency impacts associated with a shared data cache. In some examples, the multi-core processor can also include a serial processor configured to execute single threaded programming code that may not yield satisfactory performance in a processing environment that employs barrel threading.

Abstract: A cluster of processing elements has a split mode in which the processing elements are configured to process independent processing workloads, and a lock mode in which the processing elements comprise at least one primary processing element and at least one redundant processing element, each redundant processing element configured to perform a redundant processing workload for checking an outcome of a primary processing workload performed by a corresponding primary processing element. A shared cache is provided, having a predetermined cache capacity accessible to each of the processing elements when in the split mode. In the lock mode, the predetermined cache capacity of the shared cache is fully accessible to the at least one primary processing element.

Abstract: A memory device includes a memory cell array, an information register and a prefetch circuit. The memory cell array stores a valid data array, a base array and a target data array, where the valid data array includes valid elements among elements of first data, the base array includes position elements indicating position values corresponding to the valid elements and the target data array includes target elements of second data corresponding to the position values. The information register stores indirect memory access information including a start address of the target data array and a unit size of the target elements. The prefetch circuit prefetches, based on the indirect memory access information, the target elements corresponding to the position elements that are read from the memory cell array.

Abstract: The present disclosure provides a multi-core processor. The multi-core processor comprises a plurality of cores and a debug circuit, the debug circuit comprising debug circuits in the same number as that of the cores, transmission controllers in the same number as that of the cores, and a master control circuit, each of the debug circuits being connected to one core and one transmission controller, respectively, and all transmission controllers being connected to the master control circuit. Each of the debug circuits is configured to generate a debug event signal and respond to the generated debug event signal or received debug event signals generated by other debug circuits. Each of the transmission controllers is configured to respectively control transmission of the debug event signal between the respectively connected debug circuit and the master control circuit. The master control circuit is configured to forward debug event signals among different transmission controllers.

Abstract: A method performed by a physical computing system includes, with a hypervisor, determining a first time difference between when pause exiting was last enabled for the virtual machine and present time. The method further includes, with the hypervisor, in response to determining that the first time difference is greater than an enablement threshold, enabling pause exiting. The method further includes, with the hypervisor, with pause loop exiting enabled, determining a second time difference between when pause exiting was last disabled and the present time. The method further includes, with the hypervisor, disabling pause exiting in response to determining that the second time difference exceeds a disablement threshold.

Abstract: Memory access commands are placed in a memory interface queue and transmitted from the memory interface queue to a heterogeneous memory channel coupled to a volatile dual in-line memory module (DIMM) and a non-volatile DIMM. Selected memory access commands that are placed in the memory interface queue are stored in a replay queue. The non-volatile reads that are placed in the memory interface queue are in a non-volatile command queue (NV queue). The method detects, based on information received over the heterogeneous memory channel, that an error has occurred requiring a recovery sequence. In response to the error, the method initiates the recovery sequence including (i) transmitting selected memory access commands that are stored in the replay queue, and (ii) transmitting non-volatile reads that are stored in the NV queue.

Abstract: An initial configuration query for an initial configuration query result is received from a service. The initial configuration query result comprises an executable configuration query engine that can be run by the service to serve one or more subsequent configuration query results to one or more subsequent configuration queries constrained by one or more immutable configuration constraints, wherein the initial configuration query comprises the one or more immutable configuration constraints. A subset of configuration data from a configuration database is selected based at least in part on the one or more immutable configuration constraints. The executable configuration query engine is generated, wherein the executable configuration query engine serves configuration data from the selected subset of configuration data.

Abstract: A power supply apparatus for vehicles includes a first power supply circuit that converts a voltage applied to a first conductive path and applies the resulting voltage to a second conductive path, and second power supply circuits that convert a voltage applied to the first conductive path and apply the resulting voltage to third conductive paths, and switch portions are provided respectively between the second conductive path and the third conductive paths. Control units switch switch portions off when at least one of the first power supply circuit and the second conductive path is not in the predetermined abnormal state, and switch the switch portions on in the predetermined abnormal state.

Abstract: A method and an apparatus for secure interaction between terminals, where the method includes indicating or indirectly indicating, by a companion terminal with an embedded Universal Integrated Circuit Card (eUICC), a Hypertext Transfer Protocol (HTTP) over Secure Socket Layer (HTTPS) Uniform Resource Locator (URL) including security information to a primary terminal such that the primary terminal initiates establishment of a local Transport Layer Security (TLS) connection according to the HTTPS URL, receiving, by the companion terminal, an HTTP request from the primary terminal using the local TLS connection, completing establishment of an HTTPS session when the companion terminal determines that the HTTP request includes the security information, and receiving, by the companion terminal, an operation instruction for the eUICC from the primary terminal using the HTTPS session.

Abstract: Approaches, techniques, and mechanisms are disclosed for assigning paths to network packets. The path assignment techniques utilize path state information and/or other criteria to determine whether to route a packet along a primary candidate path selected for the packet, or one or more alternative candidate paths selected for the packet. According to an embodiment, network traffic is at least partially balanced by redistributing only a portion of the traffic that would have been assigned to a given primary path. Move-eligibility criteria are applied to traffic to determine whether a given packet is eligible for reassignment from a primary path to an alternative path. The move-eligibility criteria determine which portion of the network traffic to move and which portion to allow to proceed as normal. In an embodiment, the criteria and functions used to determine whether a packet is redistributable are adjusted over time based on path state information.

Abstract: An example method for adjusting operation of an integrated circuit includes testing a plurality of electronic elements of the integrated circuit including one or more redundant electronic elements designated as inactive according to a manufacturer's default configuration of the integrated circuit to determine one or more operating parameters of the integrated circuit. The method further includes selecting a subset of electronic elements from the plurality of electronic elements based on the one or more operating parameters, wherein the subset of electronic elements is designated as active according to an updated configuration of the integrated circuit, and controlling operation of the integrated circuit using the updated configuration instead of the manufacturer's default configuration.

Abstract: A processing core of a plurality of processing cores is configured to execute a speculative region of code a single atomic memory transaction with respect one or more others of the plurality of processing cores. In response to determining an abort condition for issued one of the plurality of program instructions and in response to determining that the issued program instruction is not part of a mispredicted execution path, the processing core is configured to abort an attempt to execute the speculative region of code.

Abstract: A computer data processing system includes an instruction pipeline having a front end and a back end, a decoding and dispatch unit to dispatch a current instruction; and a pipeline by-pass unit to invoke an out-of-order pipeline by-pass operation. The pipeline by-pass unit by-passes a section of the instruction pipeline such that the current instruction architecturally completes before initiating instruction execution. The computer data processing system further includes a post-completion execution unit that executes the current instruction after the current instruction architecturally completes.

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. Upon a stream break instruction specifying one of the nested loops, the stream engine ends a current iteration of the loop. If the specified loop was not the outermost loop, the streaming engine begins an iteration of a next outer loop. If the specified loop was the outermost nested loop, the streaming engine ends the stream. The streaming engine places a vector of data elements in order in lanes within a stream head register. A stream break instruction is operable upon a vector break.

Abstract: A communication device may receive a target IP address from a target device by using a first communication scheme; after the target IP address which is a global IP address has been received from the target device, send a first signal including the target IP address as a destination IP address via the Internet by using a second communication scheme; determine whether a second signal is received via the Internet by using the second communication scheme in response to sending the first signal, the second signal including the target IP address as a source IP address; and in a case where it is determined that the second signal is received, execute a security process related to security of the target device.

Abstract: A storage system includes a communication fabric, a storage module, a client device having an object descriptor (OD) generator to generate object descriptors (ODs) to access data stored in storage devices of the storage module. The storage system further includes a first control module (CM) coupled to the client device and the storage module via the communication fabric to manage accesses of the storage module. The first CM is adapted to receive a request from client device to access a data object stored in the storage module, where the request includes an OD uniquely identifying the data object and created by the OD generator of the client device. In response, the first CM examines a first object descriptor table (ODT) associated with the first CM to determine whether the OD is valid, and if the OD is valid allows the storage module to service the request.

Abstract: A method for runtime optimization of a configurable processing architecture are disclosed. The method comprises receiving a plurality of calls for running at least one function; identifying at least one pattern among the plurality of received calls; and based on the at least one pattern, manipulating at least a portion of the configurable processing architecture, to compute the least one function.

Abstract: A data processing system includes a host processor, a local memory coupled to the host processor, a plurality of remote memory media, and a scalable data fabric coupled to the host processor and to the plurality of remote memory media. The scalable data fabric includes a filter for storing information indicating a location of data that is stored by the data processing system. The host processor includes a hardware sequencer coupled to the filter for selectively moving data stored by the filter to the local memory.

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer, a doped layer, and a barrier layer disposed between the doped layer and the quantum well layer; and gates disposed above the quantum well stack. The doped layer may include a first material and a dopant, the first material may have a first diffusivity of the dopant, the barrier layer may include a second material having a second diffusivity of the dopant, and the second diffusivity may be less than the first diffusivity.

Abstract: Systems, methods, and apparatuses relating to circuitry to accelerate store processing are described. In one embodiment, a processor includes a (e.g.

Abstract: Systems and methods for multi-architecture computing. Some computing devices may include: a processor system including at least one first processing core having a first instruction set architecture (ISA), and at least one second processing core having a second ISA different from the first ISA; and a memory device coupled to the processor system, wherein the memory device has stored thereon a first binary representation of a program for the first ISA and a second binary representation of the program for the second ISA, and the memory device has stored thereon data for the program having an in-memory representation compatible with both the first ISA and the second ISA.

Abstract: A method and apparatus are provided. The method includes executing a plurality of threads in a temporal dimension, executing a plurality of threads in a spatial dimension, determining a branch target address for each of the plurality of threads in the temporal dimension and the plurality of threads in the spatial dimension, and comparing each of the branch target addresses to determine a minimum branch target address, wherein the minimum branch target address is a minimum value among branch target addresses of each of the plurality of threads.

Abstract: A method is disclosed for storing vector data into memory with a processor. The method includes obtaining, by the processor, a variable-length vector store instruction. The method also includes determining that the vector store instruction specifies a vector register for a source, a memory address, and a length, where the memory address and the length are each specified in at least a general purpose register. The method also includes determining whether data should be stored into memory at the memory address using big endian byte-ordering or little endian byte-ordering. The method further includes storing data from the vector register into memory, where if the length is less than a length of the vector register, storing only the data from the vector register specified by the length.

Abstract: A method is disclosed for loading a vector with a processor. The method includes obtaining, by the processor, a variable-length vector load instruction. The method also includes determining that the vector load instruction specifies a vector register for a target, a memory address, and a length, wherein the memory address and the length are each specified in at least a general purpose register. The method also includes determining whether data should be loaded into the vector register using big endian byte-ordering or little endian byte-ordering. The method further includes loading data from memory into the vector register, wherein if the length is less than a length of the vector register, setting one or more residue bytes in the vector register to a pad value, wherein the residue bytes are determined based on the determined byte-ordering.

Abstract: A method and system for an online help network containing a server and a plurality of terminals are disclosed. The method includes registering users of the plurality of terminals, wherein the plurality of terminals form a peer-to-peer network over which the plurality of terminals communicate with one another without going through the server; determining a question from a user of one of the terminals and a target recipient as one of the server and the peer-to-peer network; receiving an answer to the question from the target recipient; obtaining a risk detection category from the user; obtaining one or more detection patterns associated with the risk detection category; based on the one or more detection patterns, detecting a cyber risk on the terminal of the user with the risk detection category; and prompting the user of the cyber risk detected on the terminal of the user.

Abstract: A system and method for selecting a resource from among a plurality of resources. A total range of numbers is divided into a plurality of sub-ranges, each associated with a respective one of the resources. An indexing number, e.g., a random number, is generated and, when it falls within the total range of numbers, the resource associated with the sub-range into which the indexing number falls is selected. When the indexing number falls outside of the total range, a resource associated with the difference between the indexing number and the greatest number in the total range is selected.

Abstract: Provides a method to control the Background Region of a Memory Protection Unit (MPU) in order to create isolated privileged tasks (ptasks), which are an important step in the process of converting ordinary tasks to unprivileged tasks (utasks) and which also offer improved security and reliability in privileged mode.

Abstract: An information processing system that facilitates management of information security policy even for an extended application installed from exterior. A receiving unit receives security policy data in which a security policy is described. A management unit manages an extended application that can be added and deleted and that operates in an image processing apparatus. A notification unit notifies an administrator of error information about a security policy of an extended application managed by the management unit, when the extended application managed by the management unit does not comply with the security policy described in the security policy data, and when an identifier of an extended application that is extracted from the security policy data and that is excepted from applying the security policy does not match with the identifier of the extended application managed by the management unit.

Abstract: According to one embodiment of the present disclosure, there is provided a processing method including obtaining parallelized unit information for video parallel processing; obtaining performance information that indicates performance of a plurality of cores; and allocating a plurality of video unit data to the plurality of cores based on the parallelized unit information and the performance information. The parallelized unit information includes complexity information that indicates complexity of the plurality of video unit data.

Abstract: Systems, methods, and computer program products relating to compiling source code to reduce memory operations during execution. A compiler receives source code. The compiler identifies an indirect access array operation in the source code. The compiler generates replacement code for the indirect access array operation. The replacement code includes a mask array and a union data structure. The compiler generates modified code. The modified code modifies the source code to include the replacement code in place of the indirect access array operation.

Abstract: A method including fetching a group of instructions, where the group of instructions is configured to execute atomically by a processor is provided. The method further includes decoding at least one of a first instruction or a second instruction, where: (1) decoding the first instruction results in a processing of information about a group of instructions, including information about a size of the group of instructions, and (2) decoding the second instruction results in a processing of at least one of: (a) a reference to a memory location having the information about the group of instructions, including information about the size of the group of instructions or (b) a processor status word having information about the group of instructions, including information about the size of the group of instructions.

Abstract: A plurality of Peripheral Component Interconnect Express (PCIe) endpoints of a multi-socket network interface device are attached to a host for exchanging ingress traffic and egress traffic. An operating system of the host includes a bonding/teaming module having a plurality of network interfaces. The bonding/teaming module is configured to select one of the endpoints for the egress traffic. The network interface device has a hardware bond module configured to steer the ingress traffic to designated ones of the endpoints.

Abstract: In some embodiments, distributed video reorder buffers of a video (e.g. HEVC, H.265) encoder/decoder each include a circular FIFO array of pointers to buffer allocation units, and control logic which assigns allocation units to incoming video data in an order that allocation units are released by outgoing video data. The assignment order allows increased buffer utilization and lower buffer sizes, which is of increased importance for relatively large (e.g. 64×64, 32×32) video blocks, as supported by HEVC encoding/decoding.

Abstract: A system and method for extrapolating a set of specific representational identifiers that are represented or covered by a generic representational identifier found in a target document. Queries are constructed and performed on a corpus of source documents in which members of the extrapolated set of specific representational identifiers are compared to a database of representational data. By matching representational data in this way, any overlap between the generic representational data and specific instances of the generic representational identifier within the source documents is determined. In a more specific implementation, the system and method reduces the scope of the generic representational identifier such that the reduced scope generic representational identifier encompasses only novel specific representational identifiers.

Abstract: A removable base of a wearable medical monitor includes a mating surface configured to reversibly couple the removable base to a body of the wearable medical monitor. The removable base may also include certain functional features, such as a sensor configured to detect a physiological parameter of a patient and/or a memory configured to store data for identifying characteristics of the sensor or the patient.

Abstract: A computer-implemented method, system, and computer program product are provided for demand charge management. The method includes receiving an active power demand for a facility, a current load demand charge threshold (DCT) profile for the facility, and a plurality of previously observed load DCT profiles. The method also includes generating a forecast model from a data set of DCT values based on the current load DCT profile for the facility and the plurality of previously observed load DCT profiles. The method additionally includes forecasting a monthly DCT value for the facility using the forecast model. The method further includes preventing actual power used from a utility from exceeding the next month DCT value by discharging a battery storage system into a behind the meter power infrastructure for the facility.

Abstract: Various examples are directed to exposing database artifacts. For example, a rules engine may receive schema data describing a database schema of an in-memory database. The schema data may describe a table, a view, and a procedure. The rules engine may generate a data model comprising a plurality of translation artifacts including a table translation artifact describing a table of the database schema, a view translation artifact describing a view of the database schema, and a procedure translation artifact describing a procedure of the database schema. A mapping service may receive from a client application a first client request comprising first metadata describing the view translation artifact. The mapping service may initiate execution of the view at an in-memory database to determine a view result; and send the view result to the client application.

Abstract: According to certain general aspects, the present embodiments allow register files and states with different data types to share logic area while minimizing unnecessary use of power in a configurable processor. Embodiments include allowing configurable processor designers to describe alias register files and states. Using alias register files and states, designers can implement vector and scalar operations on different register files, but the scalar register file can be implemented on the vector register file. In addition, the upper lanes of the vector register file can be clock gated when the scalar operation performs computations. With this gating, the clocks for the entire upper lanes (including the register file, state, semantic, mux, decoder) can be disabled, which provides power savings.