Abstract: In a distributed shared memory type multiprocessor system, even a cell, which has no address solution mechanism, can be used as a constitutional component, so that the multiprocessor system can be flexibly operated by the various memory-constitutions. A network 500 has address solution mechanisms corresponding to the respective cells 400 and input/output controlling apparatuses 600. Each address solution mechanisms is retrieved by an address given from the cell 400 or input/output controlling apparatus 600 so as to output which memory module of a cell the address corresponds to.

Abstract: A system and method for using wider data paths within Processing Elements (PEs) of a Massively Parallel Array (MPP) to speed the computational performance of the PEs and the MPP array while still allowing for use of the simple 1-bit interconnection network to transfer data between PEs in the MPP is disclosed. A register having a data width equal to the data width of the PE for holding data for movement from one PE to another is provided in each PE. The register can be loaded in parallel within the PE, and operated as a shift register to transfer a full data width word from one PE to another PE using a 1-bit wide serial interconnection.

Abstract: A single chip active memory includes a plurality of memory stripes, each coupled to a full word interface and one of a plurality of processing element (PE) sub-arrays. The large number of couplings between a PE sub-array and its associated memory stripe are managed by placing the PE sub-arrays so that their data paths run at right angle to the data paths of the plurality of memory stripes. The data lines exiting the memory stripes are run across the PE sub-arrays on one metal layer. At the appropriate locations, the data lines are coupled to another orthogonally oriented metal layer to complete the coupling between the memory stripe and its associated PE sub-array. The plurality of PE sub-arrays are mapped to form a large logical array, in which each PE is coupled to four other PEs. Physically distant PEs are coupled using current mode differential logical couplings an drivers to insure good signal integrity at high operational speeds. Each PE contains a small DRAM register array.

Abstract: A set of S-machines, a T-machine corresponding to each S-machine, a General Purpose Interconnect Matrix (GPIM), a set of I/O T-machines, a set of I/O devices, and a master time-base unit form a system for scalable, parallel, dynamically reconfigurable computing. Each S-machine is a dynamically reconfigurable computer having a memory, a first local time-base unit, and a Dynamically Reconfigurable Processing Unit (DRPU). The DRPU is implemented using a reprogrammable logic device configured as an Instruction Fetch Unit (IFU), a Data Operate Unit (DOU), and an Address Operate Unit (AOU), each of which are selectively reconfigured during program execution in response to a reconfiguration interrupt or the selection of a reconfiguration directive embedded within a set of program instructions. Each reconfiguration interrupt and each reconfiguration directive references a configuration data set specifying a DRPU hardware organization optimized for the implementation of a particular Instruction Set Architecture (ISA).

Abstract: A multi-processor system (10) includes a plurality of processors (12). Each processor (12) has an integrated memory (16) operable to provide, receive, and store data. Each processor (12) also includes an integrated memory controller (30) in order to control read and write access to the integrated memory (16). Additionally, each processor (12) includes an integrated memory directory (18) operable to maintain a plurality of memory references to data within the integrated memory (16). The multi-processor system (10) also includes an external switch (14) coupled to each of the plurality of processors (12). The external switch (14) passes data to and from any of the plurality of processors (12). The external switch (14) has an external directory (22). The external directory (22) provides a memory reference for each of the plurality of processors (12) to remote data that is not provided within its own integrated memory directory (18).

Abstract: A hardware emulation system is disclosed which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The reconfigurable logic system of the present invention comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common I/O pins and circuit board traces. A logic analyzer for a hardware emulation system is also disclosed. The logic circuits necessary for executing logic analyzer functions is programmed into the programmable resources in the logic chips of the emulation system.

Abstract: An array of processor elements has multiple instruction streams and multiple data streams broadcast to all of the processor elements. The processor elements are each connected to multiple neighbouring processor elements within a cruciate neighbourhood. The architecture is suitable for use in fine-grained applications. The array may have a processor element for each pixel of an image. The array is preferably provided on a single integrated circuit having 10,000 or more processor elements.

Abstract: A messaging scheme that conserves system memory bandwidth during a memory read operation in a multiprocessing computer system is described. A source processing node sends a memory read command to a target processing node to read data from a designated memory location in a system memory associated with the target processing node. The target node transmits a read response to the source node containing the requested data and also concurrently transmits a probe command to one or more of the remaining nodes in the multiprocessing computer system. In response to the probe command each remaining processing node checks whether the processing node has a cached copy of the requested data. If a processing node, other than the source and the target nodes, finds a modified cached copy of the designated memory location, that processing node responds with a memory cancel response sent to the target node and a read response sent to the source node.

Abstract: A single-instruction multiple-data (SIMD) array processor providing enhanced data transfer efficiency. The SIMD array processor includes at least one memory and a plurality of mesh-connected processing elements configured in an array. Each processing element in the array includes at least one “narrow” memory buffer, at least one “wide” data register, and at least one “wide” communication register. The narrow memory buffer is adapted to transfer data serially between the memory and the wide data register, the wide data register is adapted to transfer data directly to the wide communication register, and the wide communication register is adapted to transfer data directly to the communication register of a neighboring processing element while the memory buffer is accessing data from the memory.

Abstract: An associative processor includes a plurality of arrays of content addressable memory (CAM) cells and a plurality of tags registers in a tags logic block. Different tags registers are associated with different CAM cell arrays at will, to support parallel execution of the same or different arithmetical operations on two or more CAM cell arrays, and to support pipelined arithmetical operations by having two CAM cell arrays share a tags register to transfer data from one CAM cell array to another using appropriate compare and write operations. All the CAM cell arrays share the same mask and pattern registers. Preferably, at least one tags register is located physically between two of the CAM cell arrays.

Abstract: A two-dimensional direct memory access system that maximizes processing resources in image processing systems. The present invention includes a two-dimensional direct memory access machine. Also, it employs a ping-pong style memory buffer to assist in the transfer and management of data. In certain applications of the invention, the type of data used by the invention is image data. The two-dimensional direct memory access machine transfers a specific cross sectional area of the image data to a processor. The efficient method of providing the processor only with the specific cross sectional area of the image data that is to be processed at a given time provides decreased processing time and a better utilization of processing resources within the two-dimensional direct memory access system.

Abstract: A processing or control system having arrangements for separately and simultaneously generating instruction addresses and data addresses having two bus systems for accessing instruction and data storage, and having a single address range for both instructions and data. The boundary between the instruction range and the data range can be varied and placed under the control of the processor according to the needs of the particular application being processed. Some or all of the blocks of storage can access either the instruction bus or the data bus system, and the selection is made under the control of a control register within the processor. Advantageously, applications which require a larger amount of instruction storage, this can be provided; for applications which require a larger amount of data storage, that can be provided also; both are limited only by the total amount of storage available.

Abstract: A method for providing a fill pattern for integrated circuit designs is disclosed. A keepout file having keepout data is generated from a chip design layout file having chip design layout data. The keepout file includes a map of areas of an integrated circuit design where fill patterns cannot be placed. The map of areas from the keepout file is then overlaid with a fill pattern to yield a fill-pattern file. Fill patterns from the fill-pattern file is removed from locations that coincide with locations as defined by the keepout data to yield a final-fill file with crucial fill pattern data. The crucial fill pattern data from the final-fill file is overlaid on the design layout data in the chip design layout file to yield a complete design layout file. Finally, the design rule integrity and logical to physical correspondence of the complete design layout file is verified.

Abstract: Disclosed is a solid state disk emulator system for significantly improving access time, i.e., improving both the seek time and the rotational latency. The disk emulator complies with the SMD interface convention and thus to the central processor and the SMD disk controller, the disk emulator appears as a disk with virtually a zero access time. In one embodiment, the primary systems of the disk emulator are a 66-bit shift register, a parity circuit, a latch circuit, a 66-bit parallel bus and a dynamic random access memory (DRAM) array. Each of these systems interface with control systems of the disk emulator which provide the signals required for the read and write operations of the disk emulator. An error correction process is incorporated in the disk emulator which corrects single bit hard memory errors using only a single parity bit.

Abstract: A method and an apparatus for configuring arbitrary sized data paths comprising multiple context processing elements (MCPEs) are provided. Multiple MCPEs may be chained to form wider-word data paths of arbitrary widths, wherein a first ALU serves as the most significant byte (MSB) of the data path while a second ALU serves as the least significant byte (LSB) of the data path. The ALUs of the data path are coupled using a left-going, or forward, carry chain for transmitting at least one carry bit from the LSB ALU to the MSB ALU. The MSB ALU comprises configurable logic for generating at least one signal in response to a carry bit received over the left-going carry chain, the at least one signal comprising a saturation signal and a saturation value. The MCPEs of the data path use configurable logic to manipulate a resident bit sequence in response to the saturation signal transmitted thereby reconfiguring, or changing the operation of, the data path in response to he saturation signal.

Abstract: A non-volatile semiconductor memory device that includes an address buffer block, a matrix of memory cells, and an output buffer block. The address buffer block receives input signals external to the memory device, that in a first operating mode are controlled by devices outside to the memory device, and transmit signals to the matrix of memory cells, which are adapted to decode the received signals and to transmit in turn output decoded signals through the output buffer block. A command block is provided that is activatable through an external control signal and once activated, it puts the memory device in a second operating mode in which the command block receives at least a part of the signals in output of said matrix of memory cells and, after having processed them, transmits internal address signals to the address buffer block. This provides a feedback inside the memory device capable of making the same able to autonomously execute a succession of instructions stored in the matrix of memory cells.

Abstract: A method and an apparatus for retiming in a network of multiple context processing elements are provided. A programmable delay element is configured to programmably delay signals between a number of multiple context processing elements of an array without requiring a multiple context processing element to implement the delay. The output of a first multiple context processing element is coupled to a first multiplexer and to the input of a number of serially connected delay registers. The output of each of the serially connected delay registers is coupled to the input of a second multiplexer. The output of the second multiplexer is coupled to the input of the first multiplexer, and the output of the first multiplexer is coupled to a second multiple context processing element. The first and second multiplexers are provided with at least one set of data representative of at least one configuration memory context of a multiple context processing element.

Abstract: An associative signal processing apparatus for processing a plurality of samples of an incoming signal in parallel, the apparatus comprising: (a) an array, of processors, each processor including a multiplicity of associative memory cells, the memory cells being operative to perform: (i) compare operations, in parallel, on the plurality of samples of the incoming signal; and (ii) write operations, in parallel, on the plurality of samples of the incoming signal; and (b) an I/O buffer register including a multiplicity of associative memory cells, the register being operative to: (i) input the plurality of samples of the incoming signal to the array of processors in parallel by having the I/O buffer register memory cells perform at least one associative compare operation and the array memory cells perform at least one associative write operation; and (ii) receive, in parallel, a plurality of processed samples from the array of processors by having the array memory cells perform at least one associative compare o

Abstract: In accordance with the present invention, an FPGA input/output buffer including a tristate enable register is provided. A bus line provides the FPGA output through a tristate buffer to the pad or pin. A register controls the state of the tristate buffer. A register for providing an input signal from the pad or pin may also be provided. By placing an address on address lines controlling the register clocks, any selected one of the input/output buffers can be accessed. In one embodiment, separate addresses are provided for loading a tristate control value into the output control register and for loading data into the input register.

Abstract: A two-dimensional direct memory access system that maximizes processing resources in image processing systems. The present invention includes a two-dimensional direct memory access machine. Also, it employs a ping-pong style memory buffer to assist in the transfer and management of data. In certain applications of the invention, the type of data used by the invention is image data. The two-dimensional direct memory access machine transfers a specific cross sectional area of the image data to a processor. The efficient method of providing the processor only with the specific cross sectional area of the image data that is to be processed at a given time provides decreased processing time and a better utilization of processing resources within the two-dimensional direct memory access system.

Abstract: A data processing unit comprises an input section 1 for inputting first data from the outside, an operation section 2 for operating the first data inputted therefrom, to generate second data, a memory section 3 for storing the second data, an output section 4 for outputting the second data stored in the memory section to the outside, and a control section 5 for controlling the memory section to enable storing and outputting of the second data.

Abstract: A memory component, on a single integrated circuit, operated as a slave to an external master, includes a RAM, one or more configuration registers, data formatting logic, and associated control logic. The behavior of the memory component, and in particular the selection of a burst transfer format, is controllable via configuration register bits in the one or more configuration registers. Specifically, based on a format selection specified by the configuration bits, the control logic determines the sequence-length of the data transfers between the RAM and the external master. Other than the sequence-length, the data is not otherwise altered during the data transfers.

Abstract: A microcomputer comprises an integrated circuit device with processor and memory and communication links arranged to provide non-shared connections to similar links of other microcomputers. The communication links include message synchronisation and permit creation of networks of microcomputers with rapid communication between concurrent processes on the same or different microcomputers.

Abstract: An internal bus system for DFPs and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity. The bus system can transmit data between a plurality of function blocks, where multiple data packets can be on the bus at the same time. The bus system automatically recognizes the correct connection for various types of data or data transmitters and sets it up.

Abstract: According to the SIMD control parallel processing method for performing common operation in parallel in a plurality of elements, comprising first retaining means for retaining operation data specified by n-bit for each of said plurality of elements; second retaining means for previously retaining operated result with all possible combinations comprising said data according to a predetermined operation; and selecting means for selecting said operated data retained in said first retaining means from among said operated results retained by said second retaining means, from among retained data obtained through operation, data corresponding to that resultant from the operation is selected for each element, thereby enabling a configuration to be simplified, smaller and less costly.

Abstract: A data-processing arrangement for a plurality of parallel data processors is disclosed. An operation carried out by at least one of the parallel processors is defined by an instruction word or code. The data-processing arrangement includes a control processor that makes compositions of instruction words using instruction-word composing software. A composition (VLIW) of instruction words defines operations which are to be carried out in parallel. The compositions are then provided to each parallel data processor as required. Storage of instruction-word composing software generally requires less memory space than storage of independent VLIW-s for each parallel data processor. The cost-saving this provides generally outweighs any additional costs associated with providing the control processor. Thus, the data-processing arrangement yields better cost and memory efficiency.

Abstract: A memory device which utilizes a plurality of memory modules coupled in parallel to a master I/O module through a bus. Each memory module has independent address and command decoders to enable independent operation. Thus each memory module is activated by commands on the bus only when a memory access operation is performed within the particular memory module. Each memory module has a programmable identification register which stores a communication address of the module. The communication address for each module can be changed during operation of the memory device by a command from the bus. The memory device includes redundant memory modules to replace defective memory modules. Replacement can be carried out through commands on the bus.

Abstract: A variety of applications do not require a high data throughput. The standardization of the interface in the field of smart cards fixes the processing width at 1 bit. Therefore, it is effective to use a programmable structure which operates with a data width of one bit. A data processing arrangement in the form of a 1-chip implementation with a processing width of 1 bit can be used in chip cards for simple control and automation functions while utilizing serial protocols. This structure features uncomplicated circuitry, a small chip surface area, a wide field of application and a low power consumption.

Abstract: Methods, systems, and articles of manufacture consistent with the present invention provide a development tool that enables computer programmers to design and develop a data flow program for execution in a multiprocessor computer system. The tool displays an interface that enables the programmer to define a region divided into multiple blocks, wherein each block is formed of a set of values associated with a function, and to define sets of the blocks, each block in a set having a state reflected by a designated portion of the program that when executed transforms the values forming the block based on the function. The interface also records any dependencies among the blocks, each dependency indicating a relationship between two blocks and requiring the portion of the program associated with a first block of the relationship to be executed before the portion of the program associated with a second block of the relationship.

Abstract: A messaging scheme that conserves system memory bandwidth during a memory read operation in a multiprocessing computer system is described. A source processing node sends a memory read command to a target processing node to read data from a designated memory location in a system memory associated with the target processing node. The target node transmits a read response to the source node containing the requested data and also concurrently transmits a probe command to one or more of the remaining nodes in the multiprocessing computer system. In response to the probe command each remaining processing node checks whether the processing node has a cached copy of the requested data. If a processing node, other than the source and the target nodes, finds a modified cached copy of the designated memory location, that processing node responds with a memory cancel response sent to the target node and a read response sent to the source node.

Abstract: General purpose flags (ACFs) are defined and encoded utilizing a hierarchical one-, two- or three-bit encoding. Each added bit provides a superset of the previous functionality. With condition combination, a sequential series of conditional branches based on complex conditions may be avoided and complex conditions can then be used for conditional execution. ACF generation and use can be specified by the programmer. By varying the number of flags affected, conditional operation parallelism can be widely varied, for example, from mono-processing to octal-processing in VLIW execution, and across an array of processing elements (PE)s. Multiple PEs can generate condition information at the same time with the programmer being able to specify a conditional execution in one processor based upon a condition generated in a different processor using the communications interface between the processing elements to transfer the conditions.

Abstract: Processing element to processing element switch connection control is described using a receive model that precludes communication hazards from occurring in a synchronous MIMD mode of operation. Such control allows different communication topologies and various processing effects such as an array transpose, hypercomplement or the like to be efficiently achieved utilizing architectures, such as the manifold array processing architecture. An encoded instruction method reduces the amount of state information and setup burden on the programmer taking advantage of the recognition that the majority of algorithms will use only a small fraction of all possible mux settings available. Thus, by means of transforming the PE identification based upon a communication path specified by a PE communication instruction an efficient switch control mechanism can be used.

Abstract: The present invention provides an address resolution method for use in a multiprocessor system with distributed shared memory. The method allows users to change a memory configuration and a system configuration to increase system operation flexibility and to isolate errors. A cell controller indexes into an address resolution table using the high-order part of a processor-specified address. A write protection flag specifies whether to permit write access from other cells. An attempt to write-access a cell inhibited for write access causes a logical circuit to output an access exception signal.

Abstract: A non-volatile semiconductor memory device that includes an address buffer block, a matrix of memory cells, and an output buffer block. The address buffer block receives input signals external to the memory device, that in a first operating mode are controlled by devices outside to the memory device, and transmit signals to the matrix of memory cells, which are adapted to decode the received signals and to transmit in turn output decoded signals through the output buffer block. A command block is provided that is activatable through an external control signal and once activated, it puts the memory device in a second operating mode in which the command block receives at least a part of the signals in output of said matrix of memory cells and, after having processed them, transmits internal address signals to the address buffer block. This provides a feedback inside the memory device capable of making the same able to autonomously execute a succession of instructions stored in the matrix of memory cells.

Abstract: The present invention reduces the processing time required for alltoall communications in a parallel computer. When performing alltoall communications in a parallel computer, the number of transfer data units and the number of computers are used as parameters to select between a method where a temporary work buffer is allocated in the memory of each computer and non-contiguous data is exchanged between computers and a method where data is exchanged between computers without allocating temporary work buffers.

Abstract: An apparatus for processing data has a Single-Instruction-Multiple-Data (SIMD) architecture, and a number of features that improve performance and programmability. The apparatus includes a rectangular array of processing elements and a controller. In one aspect, each of the processing elements includes one or more addressable storage means and other elements arranged in a pipelined architecture. The controller includes means for receiving a high level instruction, and converting each instruction into a sequence of one or more processing element microinstructions for simultaneously controlling each stage of the processing element pipeline. In doing so, the controller detects and resolves a number of resource conflicts, and automatically generates instructions for registering image operands that are skewed with respect to one another in the processing element array.

Abstract: The invention provides techniques for reducing the port pressure of a clustered processor. In an illustrative embodiment, the processor includes multiple clusters of execution units, with each of the clusters having a portion of a register file and a portion of a predicate file associated therewith, such that a given cluster is permitted to write to and read from its associated portions of the register and predicate files. A duplicator interconnection technique in accordance with the invention reduces port pressure by providing one or more global move units in the processor. A given global move unit uses an inter-cluster move instruction to copy a value from a portion of the register or predicate file associated with a source cluster to another portion of the register or predicate file associated with a destination cluster.

Abstract: The invention provides techniques for reducing the port pressure of a clustered processor. In an illustrative embodiment, the processor includes multiple clusters of execution units, with each of the clusters having a portion of a register file and a portion of a predicate file associated therewith, such that a given cluster is permitted to write to and read from its associated portions of the register and predicate files. A replication technique in accordance with the invention reduces port pressure by replicating, e.g., a register lock file and a predicate lock file of the processor for each of the clusters. The replicated files vary depending upon whether the technique is implemented with a write-only interconnection or a read-only interconnection.

Abstract: Multiple instances of operating systems execute cooperatively in a single multiprocessor computer wherein all processors and resources are electrically connected together. The single physical machine with multiple physical processors and resources is subdivided by software into multiple partitions, each with the ability to run a distinct copy, or instance, of an operating system. At different times, different operating system instances may be loaded on a given partition. Resources, such as CPUs and memory, can be dynamically assigned to different partitions and used by instances of operating systems running within the machine by modifying the configuration. The partitions themselves can also be changed without rebooting the system by modifying the configuration tree. CPUs, in particular, may be migrated, or reassigned, from one partition and operating system instance to another, allowing different loads in the system to be accommodated.

Abstract: A multiple use core logic chipset is provided in a computer system that may be configured either as a bridge between an accelerated graphics port (“AGP”) bus and host and memory buses, or as a bridge between a system area network interface and the host bus and the system memory bus. The function of the multiple use chipset is determined at the time of manufacture of the computer system, or in the field whether an AGP bus bridge or a system area network interface is to be implemented. Selection of the type of bus bridge (AGP or system area network interface) in the multiple use core logic chipset may be implemented by a hardware signal input, or by software during computer system configuration or power on self test (“POST”). Software configuration may also be determined upon detection of either an AGP device or a system area network interface connected to the core logic chipset.

Abstract: A massively-parallel computer includes a plurality of processing nodes and at least one control node interconnected by a network. The network faciliates the transfer of data among the processing nodes and of commands from the control node to the processing nodes. Each processing node includes an interface for transmitting data over, and receiving data and commands from, the network, at least one memory module for storing data, a node processor and an auxiliary processor. The node processor receives commands received by the interface and processes data in response thereto, in the process generating memory access requests for facilitating the retrieval of data from or storage of data in the memory module. The node processor further controlling the transfer of data over the network by the interface. The auxiliary processor is connected to the memory module and the node processor.

Abstract: A mechanism for performing parallel computations on an emulated spatial lattice by scheduling memory and communication operations on a static mesh-connected array of synchronized processing nodes. The lattice data are divided up among the array of processing nodes, each having a memory and a plurality of processing elements within each node. The memory is assumed to have a hierarchical granular structure that distinguishes groups of bits that are most efficiently accessed together, such as words or rows. The lattice data is organized in memory so that the sets of bits that interact during processing are always accessed together. Such an organization is based on mapping the lattice data into the granular structure of the memories in a manner that has simple spatial translation properties in the emulated space. The mapping permits data movement in the emulated lattice to be achieved by a combination of scheduled memory access and scheduled communication.

Abstract: A module connection assembly connects modules in a torus configuration that can be changed remotely. In particular, a single module can be added to or deleted from the configuration by remotely switching from conducting paths that provide end-around electrical paths to conducting paths that provide pass-through electrical paths. The assembly includes two backplanes, a first set of module connectors for electrically connecting modules to one of the backplanes, and a second set of module connectors for electrically connecting modules to the other backplane. The assembly further includes configuration controllers. Each configuration controller selects between end-around electrical paths that electrically connect multiple module connectors of the first set to each other, and pass-through electrical paths that electrically connect module connectors of the first set to module connectors of the second set.

Abstract: An architecture combining an associative processor memory array and a random access memory is provided. This combination architecture enables utilizing the parallel processing abilities of the associative processor memory array while storing temporary results and parameters in the random access memory for a fully programmable, low-cost die suitable for consumer electronics applications. Parallel communication between thousands of memory words in the associative memory array and the random access memory is provided via logic hardware operative as source and destination for associative search and modify (compare and write) processing operations and also operative to read and write thousands of data elements from and to the random access memory. The tags register also serves as a communication bus for parallel communication between associative memory words.

Abstract: An apparatus for processing data has a Single-Instruction-Multiple-Data (SIMD) architecture, and a number of features that improve performance and programmability. The apparatus includes a rectangular array of processing elements and a controller. The apparatus offers a number of techniques for shifting image data within the array. A first technique, the ROLL option, simultaneously shifts image planes in opposite directions within the array. A second technique, the gated shift option, makes a normal shift of an image plane to neighboring PEs conditional, for each PE, upon a value stored in a pattern register of each PE. A third technique, the carry propagate option, combines the computations from multiple PEs in order to complete an n-bit operation in fewer than n clocks by forming “supercells” within the array. The apparatus also includes a multi-bit X Pattern register and a multi-bit Y Pattern register.

Abstract: A two-dimensional PE (processing element) array that can achieve a small amount of hardware, short transfer time and high flexibility. It includes q.times.r CAMs, where q and r are any integers equal to or greater than two, and hit-flag lines. Each CAM has one-dimensionally arrayed w words, a hit-flag register capable of shift up and shift down, and an upper shift I/O port and a lower shift I/O port for inputting from and outputting to outside the contents of the hit-flag register. Each of the hit-flag lines connects the lower-shift I/O port of one of two horizontally adjacent CAMs with the upper-shift I/O port of the other of the two. The w words are arranged in m rows and n columns and are connected in a zigzag, and each word is assigned to a PE that performs various types of logical and arithmetic operations.

Abstract: A method and an apparatus for retiming in a network of multiple context processing elements are provided. A programmable delay element is configured to programmably delay signals between a number of multiple context processing elements of an array without requiring a multiple context processing element to implement the delay. The output of a first multiple context processing element is coupled to a first multiplexer and to the input of a number of serially connected delay registers. The output of each of the serially connected delay registers is coupled to the input of a second multiplexer. The output of the second multiplexer is coupled to the input of the first multiplexer, and the output of the first multiplexer is coupled to a second multiple context processing element. The first and second multiplexers are provided with at least one set of data representative of at least one configuration memory context of a multiple context processing element.

Abstract: An apparatus and method minimizes processing resource of a host system during service of interrupts generated closely in time by at least one peripheral device. The present invention determines, before the end of a prior interrupt service routine for a prior interrupt, a predicted interrupt time point when a subsequent interrupt will be generated by the at least one peripheral device. The host system operates in a polling mode if the predicted interrupt time point is before a predetermined time period after the end of the prior interrupt service routine. Thus, the host system avoids the processing resources needed for context switching time when the subsequent interrupt is generated closely in time from the prior interrupt. The host system operates in an interrupt mode if the predicted interrupt time point is after the predetermined time period after the end of the prior interrupt service routine.

Abstract: A mechanism structured to check for instruction collisions at the Dispatch Unit rather than the Completion Unit. In processors which issue multiple commands simultaneously, a flag bit is sent to the Completion Unit and attached to the instruction in the queue that follows the other in program order if they both have the same targeted address. When the instructions from position 1 and position 2 of the instruction queue are ready to issue, the Completion Unit checks position 2 for a flag bit. If there is a bit, then the instruction in position 1 is discarded and the instruction in position 2 is written to the target address. If there is no flag bit with the instruction in position 2, the instruction in position 1 is written to the target register. This method eliminates the need to compare all the targeted addresses that are associated with the rename registers. It requires two comparisons instead of a minimum of 15 comparisons.

Abstract: Vector shifting elements of a vector register by varying amounts in a single process is achieved in a vector supercomputer processor. A first vector register contains a set of operands, and a second vector register contains a set of shift counts, one shift count for each operand. Operands and shift counts are successively transferred to a vector shift functional unit, which shifts the operand by an amount equal to the value of the shift count. The shifted operands are stored in a third vector register. The vector shift functional unit also achieves word shifting of a predetermined number of vector register elements to different word locations of another vector register.