Abstract: Described herein are techniques for enabling a programmer to express a call for a data parallel call-site function in a way that is accessible and usable to the typical programmer. With some of the described techniques, an executable program is generated based upon expressions of those data parallel tasks. During execution of the executable program, data is exchanged between non-data parallel (non-DP) capable hardware and DP capable hardware for the invocation of data parallel functions.

Abstract: A method and system for transposing a multi-dimensional array for a multi-processor system having a main memory for storing the multi-dimensional array and a local memory is provided. One implementation involves partitioning the multi-dimensional array into a number of equally sized portions in the local memory, in each processor performing a transpose function including a logical transpose on one of said portions and then a physical transpose of said portion, and combining the transposed portions and storing back in their original place in the main memory.

Abstract: Systems and methods for partial reconfiguration of reconfigurable application specific integrated circuit (ASIC) devices that may employ an interconnection template to allow partial reconfiguration (PR) blocks of an ASIC device to be selectively and dynamically interconnected and/or disconnected in standardized fashion from communication with a packet router within the same ASIC device.

Abstract: A method for generating a reflection of data in a plurality of processing elements comprises shifting the data along, for example, each row in the array until each processing element in the row has received all the data held by every other processing element in that row. Each processing element stores and outputs final data as a function of its position in the row. A similar reflection along a horizontal line can be achieved by shifting data along columns instead of rows. Also disclosed is a method for reflecting data in a matrix of processing elements about a vertical line comprising shifting data between processing elements arranged in rows. An initial count is set in each processing element according to the expression (2×Col_Index) MOD (array size). In one embodiment, a counter counts down from the initial count in each processing element as a function of the number of shifts that have peen performed. Output is selected as a function of the current count.

Abstract: A method of rotating data in a plurality of processing elements comprises a plurality of shifting operations and a plurality of storing operations, with the shifting and storing operations coordinated to enable a three shears operation to be performed on the data. The plurality of storing operations is responsive to the processing element's positions.

Abstract: A computer array (10) has a plurality of computers (12). The computers (12) communicate with each other asynchronously, and the computers (12) themselves operate in a generally asynchronous manner internally. Instruction words (48) can include a micro-loop (100) which is capable of performing a series of operations repeatedly. In a particular example, the series of operations are included in a single instruction word (48). The micro-loop (100) in combination with the ability of the computers (12) to send instruction words (48) to a neighboring computer (12) provides a powerful tool for allowing a computer (12) to utilize the resources of a neighboring computer (12).

Abstract: A method for processing data for pattern matching includes: receiving a first sequence of data values; and generating a second sequence of data values based on the first sequence and one or more patterns and history of data values in the first sequence, wherein the second sequence has fewer data values than the first sequence and all subsequences in the first sequence that match at least one of the one or more patterns are represented in the second sequence.

Abstract: In an array of groups of cryptographic processors, the processors in each group operate together but are securely connected through an external shared memory. The processors in each group include cryptographic engines capable of operating in a pipelined fashion. Instructions in the form of request blocks are supplied to the array in a balanced fashion to assure that the processors are occupied processing instructions.

Abstract: A reconfigurable processor (RP) structure is provided, and particularly, a multi-mode providing apparatus including an exclusive coarse-grained array unit for each mode and a multi-mode providing method thereof are provided.

Abstract: An apparatus for processing data may include an array of processing elements (such as an n×m or n×n array of processing elements) configured to simultaneously perform operations on a plurality of data elements using a single instruction. Each processing element in the array may be configured to transfer data directly to at least one neighboring processing element within the array. In selected embodiments, the apparatus may include exchange registers to temporarily store data transferred between neighboring processing elements.

Abstract: A parallel computer comprises a plurality of compute nodes organized into at least one operational group for collective parallel operations. Each compute node is assigned a unique rank and is coupled for data communications through a global combining network. One compute node is assigned to be a logical root. A send buffer and a receive buffer is configured. Each element of a contribution of the logical root in the send buffer is contributed. One or more zeros corresponding to a size of the element are injected. An allreduce operation with a bitwise OR using the element and the injected zeros is performed. And the result for the allreduce operation is determined and stored in each receive buffer.

Abstract: Systems and methods for hardware accelerated multi-channel content-based data routing and filter. Data packets are received at a filtering circuit from one or more sources. The packets are filtered in accordance with parameters established by a system user to select specific information of relevance to the system user. The filtering may be facilitated by the assignment of a content identifier to a data element and routing data elements with the assigned content identifier to a memory associated with a processor core for collection and processing. The filtering, collection and processing is performed without calls to an operating system. The data are then distributed to data consumers over a network for further processing and use.

Abstract: An apparatus for physical properties computation comprising an array processor. The array processor comprises of a plurality of processing elements, said processing elements arranged in a grid. A processing unit (PU) is coupled to the array processor. A local memory is coupled to the PU. The PU broadcasts data to rows of said processing elements in said grid, and performs physical computations in an order of complexity of O((?N) log N).

Abstract: A software-defined radio (SDR) system comprising: 1) a reconfigurable baseband subsystem for supporting a plurality of wireless communication standards comprising a first plurality of reconfigurable context-based operation instruction set processors; and 2) a reconfigurable application subsystem for supporting a plurality of end-user applications comprising a second plurality of reconfigurable context-based operation instruction set processors. Each of the first and second pluralities of reconfigurable context-based operation instruction set processors comprises: i) a reconfigurable data path comprising a plurality of reconfigurable functional blocks; and ii) a programmable finite state machine that controls the reconfigurable data path, wherein the programmable finite state machine is capable of executing a plurality of instructions associated with a particular function.

Abstract: A serial array processor may have an execution unit, which is comprised of a multiplicity of single bit arithmetic logic units (ALUs), and which may perform parallel operations on a subset of all the words in memory by serially accessing and processing them, one bit at a time, while an instruction unit of the processor is pre-fetching the next instruction, a word at a time, in a manner orthogonal to the execution unit.

Abstract: An efficient method and device for the parallel processing of multimedia data. Blocks (or portions thereof) are transmitted to various parallel processors, in the order of their dependency data. Earlier blocks are sent to the parallel processors first, with later blocks sent later. The blocks are stored in the parallel processors in specific locations, and shifted around as necessary, so that every block, when it is processed, has its dependency data located in a specific set of earlier blocks with specified relative positions. In this manner, its dependency data can be retrieved with the same commands. That is, earlier blocks are shifted around so that later blocks can be processed with a single set of commands that instructs each processor to retrieve its dependency data from specific known relative locations that do not vary.

Abstract: A method for generating a reflection of data in a plurality of processing elements comprises shifting the data along, for example, each row in the array until each processing element in the row has received all the data held by every other processing element in that row. Each processing element stores and outputs final data as a function of its position in the row. A similar reflection along a horizontal line can be achieved by shifting data along columns instead of rows. Also disclosed is a method for reflecting data in a matrix of processing elements about a vertical line comprising shifting data between processing elements arranged in rows. An initial count is set in each processing element according to the expression (2×Col_Index) MOD (array size). In one embodiment, a counter counts down from the initial count in each processing element as a function of the number of shifts that have peen performed. Output is selected as a function of the current count.

Abstract: Systems and methods that optimize GPU processing by front loading activities from a set time/binding time to creation time via enhancements to an API that configures the GPU. Such enhancements to the API include: implementing layering arrangements, employing state objects and view components for data objects; incorporating a pipeline stage linkage/signature, employing a detection mechanism to mitigate error conditions. Such an arrangement enables front loading of the work and reduction of associated API calls.

Abstract: An archive cluster application runs in a distributed manner across a redundant array of independent nodes. Each node preferably runs a complete archive cluster application instance. A given nodes provides a data repository, which stores up to a large amount (e.g., a terabyte) of data, while also acting as a portal that enables access to archive files. Each symmetric node has a set of software processes, e.g., a request manager, a storage manager, a metadata manager, and a policy manager. The request manager manages requests to the node for data (i.e., file data), the storage manager manages data read/write functions from a disk associated with the node, and the metadata manager facilitates metadata transactions and recovery across the distributed database. The policy manager implements one or more policies, which are operations that determine the behavior of an “archive object” within the cluster. The archive cluster application provides object-based storage.

Abstract: A method and apparatus for processing a stream of data. The apparatus includes an array of processors connected to one another by single drop busses. The data stream is inputed to one of the processors 305(da), which splits off a substream and passes the data stream onto a second processor 305(db), which repeats the process; this continues until all of the data stream has been split into substreams. Each substream is processed in parallel by a second grouping 315 of processors. This second group of processors may have multiple steps and processors 315, 320. The processed substreams are assembled into a single data stream 330 by a third group of processors 325 reversing the splitting process and outputted from the array by a last processor 305(ae).

Abstract: In data path means, processor elements individually execute data processing in accordance with command codes described in a computer program, and switching elements individually control a connection relationship to switch among a plurality of processor elements in accordance with the command codes. When an access to an external memory is made from the data path means, slave memory means generates event data indicative of a task change while temporarily holding access information for executing the access with a delay, and executes the access in place of the data path means. Task changing means changes a task to be executed by the data path means when event data indicative of a task change is generated by the slave memory means.

Abstract: Aspects for reducing the time-to-market concerns for embedded system design are described. The aspects include providing an infrastructure to support a plurality of heterogeneous processing nodes as a reconfigurable network. Further included is utilizing the infrastructure to customize at least one of the heterogeneous processing nodes according to individualized design needs to achieve a desired embedded system signal processing engine.

Abstract: An array calculation device that includes a processor array composed of a plurality of processor elements having been assigned with orders, acquires an instruction in each cycle, generates, in each cycle, operation control information for controlling an operation of a processor element of a first order, and then generates an instruction to the processor element of the first order in accordance with the operation control information and the acquired instruction, and also generates, in each cycle, operation control information for controlling an operation of each processor element of a next order and onwards, in accordance with operation control information generated for controlling an operation of a processor element of an immediately preceding order, and then generates an instruction to each processor element of the next order and onwards, in accordance with the operation control information generated and the acquired instruction.

Abstract: The present invention is capable of placing or loading input data into a 2D or 3D array of processing elements interconnected in a variety of ways, and moving the data around by using a combination of shifts, e.g. north, south, east, west, which can be combined in any desired manner. The exact type and combination of shifts depends upon the particular data manipulation desired. As the sifting proceeds, each processing element is presented with a plurality of different array values. Each processing element can conditionally load any of the values it sees into the output result. The timing of the loading is achieved by monitoring a local counter. In a preferred embodiment, when the value in the local counter is non-positive, the current array value is selected as the final output for the output result. In general, each local counter is initialized to a different positive value and, at certain points in the shifting process, the counter is decremented.

Abstract: A matrix of execution blocks form a set of rows and columns. The rows support parallel execution of instructions and the columns support execution of dependent instructions. The matrix of execution blocks process a single block of instructions specifying parallel and dependent instructions.

Abstract: Methods and systems for application framework development for wireless devices are provided herein. Aspects of the method may include acquiring an MMI event from an MMI event queue within the MMI wireless framework. An identity of the acquired MMI event may be determined and the acquired MMI event may be dispatched to an event handler based on the determined identity of the acquired event. If the acquired MMI event comprises a timing event, the acquired MMI event may be dispatched to an MMI event owner within the MMI wireless framework. If the acquired MMI event comprises a keypad event, the acquired MMI event may be dispatched to a currently active MMI view within the MMI wireless framework. If the acquired MMI event comprises an addressed event, the acquired MMI event may be dispatched to a destination handler within the MMI wireless framework.

Abstract: The present invention related to monitoring internet traffic for illegal Intellectual Property transfers, viruses, criminal and other illegal activities. It also assists the Internet search engine providers in generating fast and accurate responses to Internet Recipient (IR) database queries. A massively parallel network of processing units residing within a single programmable ASIC device assures speeds in excess of 100 Gigabits/second.

Abstract: A delay circuit that can prevent an increase in the scale of circuits. A data delay section included in the delay circuit delays input data by a plurality of data delay elements. A validity information delay section included in the delay circuit delays input validity information which indicates that the input data is valid by a plurality of validity information delay elements corresponding to the plurality of data delay elements included in the data delay section. As a result, the input data and the input validity information pass through a data delay element and a validity information delay element, respectively, which are associated with each other at the same timing. An output signal outputted from each data delay element can be taken out. Similarly, an output signal outputted from each validity information delay element can be taken out. Therefore, a plurality of output signals having desired delay amounts can be obtained for one input signal inputted to a delay circuit.

Abstract: A customization program for use in customizing a baseboard management controller used for monitoring operation of various computer system components is disclosed. A user interacts with the customization program to customize the baseboard management controller based on a configuration of components specified for the baseboard of the computer system. The customization program provides a user interface having a repository of icons and a design page. The icons represent various components that may be connected, either directly or indirectly, to the baseboard. The design page is used for constructing a model representing the specified configuration of components. As a user drags icons onto the design page, the model is updated to reflect selection of the components corresponding to these icons. Further, the customization program creates a configuration file that identifies and describes each of the selected components.

Abstract: An integrated circuit device with a data processing block is provided, the data processing block including a plurality of operation units that are arranged in a matrix, a plurality of first wire sets that extend in a first direction in the matrix and transfer input data of each operation unit, a plurality of second wire sets that extend in a second direction in the matrix and transfer output data of each operation unit, and a plurality of switching units that are arranged at each intersection between the first and second wire sets and can select and connect any wire in the first wire sets and any wire in the second wire sets. The plurality of operation units include a plurality of types of operation units with different data paths that are suited to special-purpose, processing, with an arrangement of operation units of the same type in the first direction or the second direction being formed in at least part of the data processing block.

Abstract: An archive cluster application runs in a distributed manner across a redundant array of independent nodes. Each node preferably runs a complete archive cluster application instance. A given nodes provides a data repository, which stores up to a large amount (e.g., a terabyte) of data, while also acting as a portal that enables access to archive files. Each symmetric node has a set of software processes, e.g., a request manager, a storage manager, a metadata manager, and a policy manager. The request manager manages requests to the node for data (i.e., file data), the storage manager manages data read/write functions from a disk associated with the node, and the metadata manager facilitates metadata transactions and recovery across the distributed database. The policy manager implements one or more policies, which are operations that determine the behavior of an “archive object” within the cluster. The archive cluster application provides object-based storage.

Abstract: The computer node architecture provides a separate computer for the execution of the respective one of the application software and the middleware software, with an interface precisely defined in the time and value range provided between said two computers, and thus to decouple largely these two subsystems so that development is improved and the time needed for real-time applications better foreseeable.

Abstract: An integrated circuit (203) for use in processing streams of data generally and streams of packets in particular. The integrated circuit (203) includes a number of packet processors (307, 313, 303), a table look up engine (301), a queue management engine (305) and a buffer management engine (315). The packet processors (307, 313, 303) include a receive processor (421), a transmit processor (427) and a risc core processor (401), all of which are programmable. The receive processor (421) and the core processor (401) cooperate to receive and route packets being received and the core processor (401) and the transmit processor (427) cooperate to transmit packets. Routing is done by using information from the table look up engine (301) to determine a queue (215) in the queue management engine (305) which is to receive a descriptor (217) describing the received packet's payload.

Abstract: An eventpoint chaining apparatus for generalized event detection and action specification in a processing environment is described. In one aspect, the eventpoint chaining apparatus includes a first processor which has a programmable eventpoint module with an input trigger (InTrig) input. The first processing element detects an occurrence of a first processor event (p-event) and produces an OutTrigger (OT) signal. The eventpoint chaining apparatus also includes a second processor which has a programmable eventpoint module with an input trigger (InTrig) input which receives the OT signal from the first processing element. The second processing element detects an occurrence of a second p-event and produces, in response to the OT signal received from the first processing element and the detection of a second p-event, an eventpoint (EP) interrupt signal.

Abstract: A surface computer includes an address generator for generating an address for adjusting surface region data concerning at least a storage region and a concurrent computer, provided at a subsequent stage of the address generator, having a plurality of unit computers.

Abstract: In a network of digital signal processor nodes connected in a peer-to-peer relationship, a data packet sent to a node causes a return transmission from that node. The requester digital signal processor sends a data packet to a target digital signal processor. Upon arrival at the target digital signal processor, its receiver drives the arriving request packet into an I/O memory and triggers a transmitter interrupt. Next, the pull interrupt causes the transmitter to execute on a next packet boundary the pull request packet. Finally, the execution of the pull request causes the transmitter to pull a portion of the local I/O memory and send it back to the requester digital signal processor. The same physical portion of the I/O memory is overlaid with two logical uses, a receiver channel and a transmitter code block.

Abstract: A system for designing and implementing digital integrated circuits utilizing a set of synchronized sequencers that permit quick and efficient parallel processing of system level designs. The system and method converts digital schematics and hardware description language (HDL) based designs into a set of logic equations and single bit arithmetic-logic operations executed by a set of parallel operating sequencers. The system includes software for converting netlists and HDL designs into Boolean logic equations, and a compiler for distributing these logic equations between multiple sequencers. Each sequencer is comprised of a logic processor and the associated program memory for storing the executable code of the assigned Boolean logic equations and data memory for storing the results of processing of logic equations. To synchronize execution of logic equations by multiple sequencers, all program memories are addressed by one common address register.

Abstract: In accordance with a parallel matrix processing method adopted in a shared-memory scalar computer, a matrix to be subjected to LU factorization is divided into a block D of the diagonal portion and blocks beneath the D diagonal block such as L1, L2 and L3. Then, D+L1, D+L2 and D+L3 are assigned to 3 processors respectively for processing them in parallel. Next, a block U is updated by adopting an LU-factorization method and C1 to C3 are updated with L1 to L3 and U. By carrying out this processing on the inner side gradually decreasing in size as blocks, finally, a portion corresponding to the D diagonal block remains to be processed. By applying the LU factorization to this D portion, the LU factorization for the entire matrix can be completed.

Abstract: The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations.

Abstract: Processing element to processing element switch connection control is described using a receive model that precludes communication hazards from occurring in a synchronous MIMD mode of operation. Such control allows different communication topologies and various processing effects such as an array transpose, hypercomplement or the like to be efficiently achieved utilizing architectures, such as the manifold array processing architecture. An encoded instruction method reduces the amount of state information and setup burden on the programmer taking advantage of the recognition that the majority of algorithms will use only a small fraction of all possible mux settings available. Thus, by means of transforming the PE identification based upon a communication path specified by a PE communication instruction an efficient switch control mechanism can be used.

Abstract: An system-on-a-chip integrated circuit has a field programmable gate array core having logic clusters, static random access memory modules, and routing resources, a field programmable gate array virtual component interface translator having inputs and outputs, wherein the inputs are connected to the field programmable gate array core, a microcontroller, a microcontroller virtual component interface translator having input and outputs, wherein the inputs are connected to the microcontroller, a system bus connected to the outputs of the field programmable gate array virtual component interface translator and also to the outputs of said microcontroller virtual component interface translator, and direct connections between the microcontroller and the routing resources of the field programmable gate array core.

Abstract: To execute all processing in an array section of an array-type processor, each processor must execute processing of different types, i.e., processing of an operating unit and processing of a random logic circuit, which limits its size and processing performance. A data path section including processors arranged in an array are connected via programmable switches to primarily execute processing of operation and a state transition controller configured to easily implement a state transition function to control state transitions are independently disposed. These sections are configured in customized structure for respective processing purposes to efficiently implement and achieve the processing of operation and the control operation.

Abstract: An array of processor elements has multiple instruction streams and multiple data streams broadcast to all of the processor elements. The processor elements are each connected to multiple neighbouring processor elements within a cruciate neighbourhood. The architecture is suitable for use in fine-grained applications. The array may have a processor element for each pixel of an image. The array is preferably provided on a single integrated circuit having 10,000 or more processor elements.

Abstract: A cascadable arithmetic and logic unit (ALU) which is configurable in function and interconnection. No decoding of commands is needed during execution of the algorithm. The ALU can be reconfigured at run time without any effect on surrounding ALUs, processing units or data streams. The volume of configuration data is very small, which has positive effects on the space required and the configuration speed. Broadcasting is supported through the internal bus systems in order to distribute large volumes of data rapidly and efficiently. The ALU is equipped with a power-saving mode to shut down power consumption completely. There is also a clock rate divider which makes it possible to operate the ALU at a slower clock rate. Special mechanisms are available for feedback on the internal states to the external controllers.

Abstract: Different portions of a header of each packet containing protocol data are analyzed in succession from different gate registers of the TRIE memory. As a packet arrives, its header is stored in a buffer memory and a first portion of the stored header is analyzed. Each analysis of a portion of header produces either the forwarding reference associated with the packet or an intermediate reference containing a first code, making it possible to locate at an arbitrary location of the buffer memory a next portion to be analyzed, and a second code, making it possible to locate at an arbitrary location of the TRIE memory a gate register from which this next portion is to be analyzed. Having analyzed the first portion of a stored header, the subsequent portions thereof are analyzed in accordance with the first and second codes contained in the intermediate references produced in succession until the forwarding reference is produced.

Abstract: A component architecture for digital signal processing is presented. A two dimensional reconfigureable array of identical processors, where each processor communicates with its nearest neighbors, provides a simple and power-efficient platform to which convolutions, finite impulse response (“FIR”) filters, and adaptive finite impulse response filters can be mapped. An adaptive FIR can be realized by downloading a simple program to each cell. Each program specifies periodic arithmetic processing for local tap updates, coefficient updates, and communication with nearest neighbors. During steady state processing, no high bandwidth communication with memory is required.

Abstract: A method in a multi-processor computing system is disclosed. The method is an object-oriented method that allows a user to make associations between processes to be executed and available CPUs of the system. In particular, the method includes the displaying of the associations for a user to manipulate. Responses are accepted by the method from a user for creating logical groupings of the CPUs, hereinafter referred to as affinity groups. Next, an affinity mask is accepted from the user for each of the affinity groups, which affinity mask assigns available ones of the CPUs. After this a determination is made as to whether or not there are more CPUs to be assigned to the affinity groups, and if not; specific rules that make associations between the processes and the affinity groups are then accepted by the method from the user.

Abstract: A data-processing arrangement comprises a plurality of elementary circuits such as processing circuits [PRC] and memory circuits [MEM]. The data-processing arrangement further comprises a controller [MCP]. The controller [MCP] is programmed to successively apply, in response to a task-initialization data [TID], control data [CD] to different subsets of elementary circuits. This causes the data-processing arrangement to process a block of data [DB] in accordance with a certain data-processing chain [DPC]. Each subset of elementary circuits implements a different element [E] of the data-processing chain [DPC].

Abstract: A system for designing and implementing digital integrated circuits utilizing a set of synchronized sequencers that permit quick and efficient parallel processing of system level designs. The system and method converts digital schematics and hardware description language (HDL) based designs into a set of logic equations and single bit arithmetic-logic operations executed by a set of parallel operating sequencers. The system includes software for converting netlists and HDL designs into Boolean logic equations, and a compiler for distributing these logic equations between multiple sequencers. Each sequencer is comprised of a logic processor and the associated program memory for storing the executable code of the assigned Boolean logic equations and data memory for storing the results of processing of logic equations. To synchronize execution of logic equations by multiple sequencers, all program memories are addressed by one common address register.

Abstract: The invention relates to an application-specific integrated circuit (ASIC) for processing defined sequences of assembler instructions (TASKs). To improve data throughput in applications with high memory access rates, the ASIC contains a TASK scheduler, which is implemented as hardware and which chronologically coordinates, in an appropriate manner, the processing of different TASKs on an ASIC internal processing means (EXU). Compared to conventional software control units for multitasking systems, this TASK scheduler which is implemented as hardware offers the advantage, among others, that the operating system is relieved of load, and an expensive memory architecture is not required.