Abstract: A method and an apparatus for configuring arbitrary sized data paths comprising multiple context processing elements (MCPEs) are provided. Multiple MCPEs may be chained to form wider-word data paths of arbitrary widths, wherein a first ALU serves as the most significant byte (MSB) of the data path while a second ALU serves as the least significant byte (LSB) of the data path. The ALUs of the data path are coupled using a left-going, or forward, carry chain for transmitting at least one carry bit from the LSB ALU to the MSB ALU. The MSB ALU comprises configurable logic for generating at least one signal in response to a carry bit received over the left-going carry chain, the at least one signal comprising a saturation signal and a saturation value. The saturation signal is generated using logic that tests for saturation in the data path. The ALUs of the data path are further coupled using a right-going carry chain for transmitting the saturation signal back down the data path.

Abstract: The invention relates to computer science, in particular, to computer systems using data flow control over computations and to the further inclusion of processing means utilizing the von Neumann principle of computation resulting in an improvement of performance and a decrease in the volume (size) of associative memory.

Abstract: In a superscalar processor, multiple instructions are executed in parallel to obtain multiple execution results, and the multiple execution results are stored in a working register file. Each execution result in the working register file has at least one status bit associated therewith which identifies the execution result as valid data. The multiple execution results contained in the working register data then retired by changing the status bits associated with each execution result to identify the execution result as final data. In this manner, the speculative data is retired as the final data without data movement of the speculative data, thus reducing a number of ports needed in the superscalar processor.

Abstract: The invention relates to computer science, in particular, to a computer system comprising a processor, an input-output switch, an instruction loading switch, instruction memory, and a data access unit which uses the dataflow principle of computation. Performance is increased by decreasing the volume of associative memory by means of the introduction of the use of a fragment routine processor to process segments of the program which are better processed by von Neumann principles of computation.

Abstract: A method and an apparatus for configuring arbitrary sized data paths comprising multiple context processing elements (MCPEs) are provided. Multiple MCPEs may be chained to form wider-word data paths of arbitrary widths. The ALUs of the data path are coupled using a carry chain for transmitting at least one carry bit from the LSB ALU to the MSB ALU. The MSB ALU comprises configurable logic for generating a signal in response to a carry bit received over the carry chain, the signal comprises a saturation signal and a saturation value. The saturation signal is generated using logic that tests for saturation in the data path. The ALUs of the data path are further coupled using a right-going carry chain for transmitting the saturation signal back down the data path. The saturation signal is transmitted from the MSB ALU through the ALUs of the data path to the LSB ALU using a first back propagation channel.

Abstract: The compilation of source code to a primary and a secondary processor. The method relates to reconfigurable secondary processors, and is especially relevant to secondary processors which can be reconfigured to some degree during execution of code. Selective extraction of dataflows from the source code is followed by transformation of the extracted dataflows into trees. The trees are then matched against each other to determine minimum edit cost relationships for transformation of one tree into another, where these minimum edit cost relationships are determined by the architecture of the secondary processor. A group or a plurality of groups of dataflows is determined on the basis of said minimum edit cost relationships and for each group a generic dataflow capable of supporting each dataflow in that group is created.

Abstract: An architecture combining an associative processor memory array and a random access memory is provided. This combination architecture enables utilizing the parallel processing abilities of the associative processor memory array while storing temporary results and parameters in the random access memory for a fully programmable, low-cost die suitable for consumer electronics applications. Parallel communication between thousands of memory words in the associative memory array and the random access memory is provided via logic hardware operative as source and destination for associative search and modify (compare and write) processing operations and also operative to read and write thousands of data elements from and to the random access memory. The tags register also serves as a communication bus for parallel communication between associative memory words.

Abstract: In a multi-processor computing system, a multi-layer architecture is described in which each layer has a plurality of dual ported microprocessors, one port of which receives data for processing and the other port of which is utilized for unloading or passing data to a subsequent layer. If the processing cannot be completed prior to the time allotted for the next load cycle for a particular processor, the processing is interrupted, the state of the processor currently engaged in the processing is stored in the data and the state of the processor is transferred to a processor of a subsequent layer where processing resumes as if no interruption had occurred.

Abstract: A pipeline structure processes data in a series of stages, each of which has a data input latch (LDIN) and passes it on to the next stage in the pipeline via a data output latch (LDOUT). The stages are preferably connected to two non-overlapping clock phases (PH0, PH1) Adjacent stages are also connected via a validation line (IN.sub.-- VALID, OUT.sub.-- VALID) and an acceptance line (IN.sub.-- ACCEPT, OUT.sub.-- ACCEPT), and in some embodiments also via an extension bit line (IN.sub.-- EXTN, OUT.sub.-- EXTN). Input data is transferred from any stage to the following device on every complete period of both clock signals only if both the validation and acceptance signals in the respective latch are in an affirmative state, whereby data is transferred between stages regardless of the state of the validation and acceptance signals in other stages. A two-wire interface is thus formed between the stages.

Abstract: A memory-like I/O system is provided for interfacing a processing element array with a host system. The I/O system includes cornerturn logic for converting data written to the processing element array from horizontal format to vertical format and for converting data read from the processing element array from vertical format to horizontal format. Addressable interface memory is provided and includes a first bank for receiving and storing data which has been output from the cornerturn logic and for outputting that data for delivery to the processing element array. The addressable interface memory includes a second bank for receiving and storing data which has been output from the processing element array and for outputting that data for delivery to the cornerturn logic. The interface of the invention can provide support for concurrent I/O and processing, thereby allowing processing and I/O operations to proceed in parallel.

Abstract: A multi-standard video decompression apparatus has a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system.

Abstract: An asynchronous circuit having a pipelined completion mechanism to achieve improved throughput.

Abstract: A device controller is described within a data storage system for pre-fetching device work information from multiple data storage devices, and accumulating the device work information to immediately respond to a subsequent device poll command from a storage controller. The device controller includes a device receiver to receive the device poll command, a device transmitter to transmit a response to the device poll command, a device information register for storing the pre-fetched device work information for each data storage device, and a sequencer for periodically pre-fetching the device work information from each data storage device. The sequencer pre-fetches such information by verifying that no device subsystem command from the storage controller is pending in the device receiver, then issuing a background poll command to a selected device to query the device for its device work information, and storing the device work information in the device information register.

Abstract: An array processor includes processing elements arranged in clusters which are, in turn, combined in a rectangular array. Each cluster is formed of processing elements which preferably communicate with the processing elements of at least two other clusters. Additionally each inter-cluster communication path is mutually exclusive, that is, each path carries either north and west, south and east, north and east, or south and west communications. Due to the mutual exclusivity of the data paths, communications between the processing elements of each cluster may be combined in a single inter-cluster path. That is, communications from a cluster which communicates to the north and east with another cluster may be combined in one path, thus eliminating half the wiring required for the path. Additionally, the length of the longest communication path is not directly determined by the overall dimension of the array, as it is in conventional torus arrays.

Abstract: A parallel computer system which divides the entire space of facilities into a plurality of small divisions; assigns a plurality of processors thereof to the divisions, respectively, the lower stream processors receiving data on a boundary condition from the upper stream processor by communication to determine a condition for the continuity of the adjacent divisions, the processors carrying out parallel analytical operations for the analysis of the data on the corresponding divisions so as to meet the received boundary condition; and collects data obtained by the parallel analytical operations of the processors in a host computer to obtain analytical data on the large-scale facilities.

Abstract: A transmit scheduler and method of operation are provided for an asynchronous transfer mode network. The transmit scheduler is operable to write data to and read data from a scheduler table and a virtual channel identifier ("VCI") table in order to schedule cells for virtual channels. The transmit scheduler calculates a location in the scheduler table in which to schedule a cell for a current virtual channel and determines whether a cell for a prior virtual channel is scheduled in the calculated location in the scheduler table. The transmit scheduler then schedules the cell for the current virtual channel at the calculated location in the scheduler table. If a cell for a prior virtual channel was scheduled in the calculated location in the scheduler table, the transmit scheduler writes a pointer into a next pointer field of a record for the current virtual channel in the VCI table, where the pointer provides a link to a record for the prior virtual channel in the VCI table.

Abstract: A message-passing protocol for accommodating early arrival messages passed between source and destination nodes in a computer system with a plurality of asynchronous computing nodes interconnected by bidirectional asynchronous communications channels. The protocol includes transmitting the message from sender to receiver without waiting for a request for the message from the receiver; determining at the receiver if a receive buffer has been posted for the message; and if the receive buffer has not been posted for the message, then either truncating the message by storing its message header in an early arrival queue at the receiver and discarding its data or allocating a temporary receive buffer at the receiver to hold the message data.