Abstract: According to one aspect of the invention, there is provided a method for renaming memory references to stack locations in a computer processing system. The method includes the steps of detecting stack references that use architecturally defined stack access methods, and replacing the stack references with references to processor-internal registers. The architecturally defined stack access methods include memory accesses that use one of a stack pointer, a frame pointer, and an argument pointer. Moreover, the architecturally defined stack access methods include push, pop, and other stack manipulation operations.

Abstract: A loop control circuit and a loop control method that allow control on multiplexed loop operations to be executed with less overhead are provided. A loop control circuit comprises a means for address storage that stores in memory the address of a loop instruction at a second or subsequent stage in multiplexed loops or the address of the instruction immediately preceding the loop instruction when the loop instruction is executed for the first time, a means for loop instruction recurrence prediction that predicts a recurrence of the loop instruction at the second or subsequent stage by comparing the address of the loop instruction or the address of the instruction immediately preceding the loop instruction stored in memory with a value at a program counter and a means for loop instruction skipping that skips the loop instruction if it is predicted that the loop instruction is to occur next.

Abstract: A stack pointer update technique in which the stack pointer is updated without executing micro-operations to add or subtract a stack pointer value. The stack pointer update technique is also described to reset the stack pointer to a predetermined value without executing micro-operations to add or subtract stack a stack pointer value.

Abstract: The present invention provides a non-copy shared stack and register set device and a dual language processor structure using the same, which achieve non-copy data sharing by controlling a selector and the stack pointer of a data stack. The selector is connected to each item of the data stack and a register of the register set, such that, when the register set requires to exchange data with the data stack, the selector is controlled and the stack pointer is updated thereby the selector is switched to make the stack item pointed by the stack pointer communicate with the register.

Abstract: Methods and apparatus for eliminating C recursion from interpreter loops are disclosed. According to one aspect of the present invention, a computer-implemented method for substantially eliminating C recursion from the execution of static initializer methods in a virtual machine environment includes rewriting native C code associated with a static initializer as a Java programming language method, and using a transition frame in a Java programming language stack to execute the Java programming language method. The method also includes using a native method to manipulate the Java programming language stack, and using a first opcode in the transition frame. In one embodiment, using the first opcode in the transition frame includes using the first opcode to determine that the transition frame is associated with the static initializer.

Abstract: A digital data processor comprising a stack storage having a plurality of locations classified into two or more banks, and a stack pointer circuit pointing to one or more stack banks of the stack storage. The stack pointer circuit operates in response to decoding signals from an instruction decoder which decodes a current instruction to determine whether a one-word or a multi-word stack operation is desired.

Abstract: A system may include a memory file and an execution core. The memory file may include an entry configured to store an addressing pattern and a tag. If an addressing pattern of a memory operation matches the addressing pattern stored in the entry, the memory file may be configured to link a data value identified by the tag to a speculative result of the memory operation. The addressing pattern of the memory operation includes an identifier of a logical register, and the memory file may be configured to predict whether the logical register is being specified as a general purpose register or a stack frame pointer register in order to determine whether the addressing pattern of the memory operation matches the addressing pattern stored in the entry. The execution core may be configured to access the speculative result when executing another operation that is dependent on the memory operation.

Abstract: A method is proposed for virtual enlargement of the stack of a portable data carrier allowing reloading of executable program code. To permit the execution of programs requiring a larger stack than that physically present, the stack is segmented into at least two stack segments and their fill state monitored. When complete occupation of a segment is recognized, the oldest stack segment is swapped out to a further storage medium. The further storage medium is a nonvolatile read-write memory that can be a slower memory compared to the stack. When sufficient memory space is available in the stack again, the swapped out segment is returned. The method includes managing a destination address of each stack segment swapped out to the non-volatile read-write memory in a register in a volatile read-write memory.

Abstract: A processing device comprises an instruction memory 120 for storing virtual machine instructions, such as Java byte codes. A processor 112 of the processing device comprises a predetermined microcontroller core 114 for executing native instructions from a predetermined set of microcontroller specific instructions. The native instructions differ from the virtual machine instructions. The processor 112 is of a type which may request re-feeding of a plurality of native instructions. For instance, the processor 112 may have a pipeline and/or instruction cache which after an interrupt need to be re-filled. The processing device comprises a pre-processor 130 with a converter 132 for converting at least one virtual machine instruction, fetched from the instruction memory, into at least one native instruction.

Abstract: An apparatus comprising a processor and a translator circuit. The processor may (i) comprise a number of internal registers and (ii) be configured to manipulate contents of the internal registers in response to instruction codes of a first instruction set. The translator circuit may be configured to implement a stack using one or more of the internal registers of the processor.

Abstract: A data processor comprises a register bank containing a plurality of “n” bit registers for storing data items, a set of registers within the register bank being allocatable to hold stack data items from a portion of the stack, and each register in the set storing as an n-bit value stack data items of the first or second type. An arithmetic logic unit executes operations upon data items held in the registers and a decoder decodes a stack-based instruction to specify a number of operations to be executed by the arithmetic logic unit upon one or more stack data items held in predetermined registers in the set. Further, a stack controller is arranged to control movement of stack data items between the stack and the set of registers, and is responsive to the decoder causing one or more stack data items to be held in the predetermined registers.

Abstract: A computer thread utilizes an auxiliary stack resource to execute program code function calls requiring substantial stack memory resources. In a wrapper embodiment, portions of the program code having function calls requiring substantial stack resources are wrapped in a wrapper that calls an auxiliary stack resource for executing the function call and returns the auxiliary stack resource when the function call is completed. In one embodiment, the stack memory allocated to the thread is selected to accommodate a first class of function calls requiring comparatively low amounts of stack memory and the auxiliary stack resource is called to accommodate the requirements of a second class of function calls requiring comparatively large amounts of stack memory. The allocation of stack memory according to the requirements of function calls allows for multiple computing tasks, such as those carried out by Internet websites and services, to be carried out more efficiently.

Abstract: A dual instruction set processor can decode and execute both code received from a network and other code supplied from a local memory. Thus, the dual instruction set processor is capable of executing two different types of instructions, from two different sources, permitting the dual instruction set processor to have maximum efficiency. A computer system with the foregoing described dual instruction set processor, a local memory, and a communication interface device, such as a modem, for connection to a network, such as the Internet or an intranet, can be optimized to execute, for example, JAVA code from the network, and to execute non-JAVA code stored locally, or on the network but in a trusted environment or an authorized environment.

Abstract: A memory architecture in accordance with an embodiment of the present invention improves the speed of method invocation. Specifically, method frames of method calls are stored in two different memory circuits. The first memory circuit stores the execution environment of each method call, and the second memory circuit stores parameters, variables or operands of the method calls. In one embodiment the execution environment includes a return program counter, a return frame, a return constant pool, a current method vector, and a current monitor address. In some embodiments, the memory circuits are stacks; therefore, the stack management unit to cache can be used to cache either or both memory circuits. The stack management unit can include a stack cache to accelerate data transfers between a stack-based computing system and the stacks. In one embodiment, the stack management unit includes a stack cache, a dribble manager unit, and a stack control unit.

Abstract: The Java Virtual Machine (JVM) can be decoupled from its Java-enabled browser. To maintain access to certain system resources (a “privilege”) by applets, each Java thread that enables the privilege will now create an entry that describes the privilege in a linked list based on the stack frame address. Sufficient information is stored in the link list for validation purposes. Further, system classes that require specific privileges will have them implicitly granted by an implicit privilege list.

Abstract: Improved techniques for invocations of native methods in Java computing environments are disclosed. The techniques can be implemented in Java computing environments to facilitate efficient use of methods (functions or subroutines) written in programming languages other than Java (e.g., C, C++, etc.). As such, the techniques are highly suitable for use by virtual machines operating with relatively less memory and/or computing power (e.g., embedded systems). A lightweight native method invocation interface can be implemented to provide direct access to Java parameters on the execution stack. In addition, the lightweight native method invocation can include macro instructions that operate efficiently to convert the Java parameters into native parameters. Thus, the lightweight native method invocation can significantly reduce the overhead associated with conventional Java native method invocation techniques.

Abstract: A microprocessor apparatus is provided for performing a pop-compare operation. The microprocessor apparatus includes paired operation translation logic, load logic, and execution logic. The paired operation translation logic receives a macro instruction that prescribes the pop-compare operation, and generates a pop-compare micro instruction. The pop-compare micro instruction directs pipeline stages in a microprocessor to perform the pop-compare operation. The load logic is coupled to the paired operation translation logic. The load logic receives the pop-compare micro instruction, and retrieves a first operand from an address in memory, where the address is specified by contents of a register. The register is prescribed by the pop-compare micro instruction. The execution logic is coupled to the load logic. The execution logic receives the first operand, and compares the first operand to a second operand.

Abstract: The present invention discloses a method and device for ordering memory operation instructions in an optimizing compiler. for a processor that can potentially enter a stall state if a memory queue is full. The method uses a dependency graph coupled with one or more memory queues. The dependency graph is used to show the dependency relationships between instructions in a program being compiled. After creating the dependency graph, the ready nodes are identified. Dependency graph nodes that correspond to memory operations may have the effect of adding an element to the memory queue or removing one or more elements from the memory queue. The ideal situation is to keep the memory queue as full as possible without exceeding the maximum desirable number of elements, by scheduling memory operations to maximize the parallelism of memory operations while avoiding stalls on the target processor.

Abstract: Methods and apparatus for eliminating C recursion from interpreter loops are disclosed. According to one aspect of the present invention, a computer-implemented method for substantially eliminating C recursion from the execution of static initializer methods in a virtual machine environment includes rewriting native C code associated with a static initializer as a Java™ method, and using a transition frame in a Java™ stack to execute the Java™ method. The method also includes using a native method to manipulate the Java™ stack, and using a first opcode in the transition frame. In one embodiment, using the first opcode in the transition frame includes using the first opcode to determine that the transition frame is associated with the static initializer. In another embodiment, the method further includes causing the static initializer to run, wherein the static initializer using a second opcode, and resuming execution at the second opcode after the static initializer has run.

Abstract: A system and method for managing utilization in a stack. A stack base and a stack pointer are initialized for the stack. Upon fetching a program instruction to be executed in a computing environment, a determination is made if the program instruction involves accessing a location within a valid stack range that is defined by a high water mark operable to identify the stack pointer's farthest location from the stack base. The farthest location is indicative of how far the stack has grown at any time during the program's execution. A warning may be provided upon determining that the location to be accessed is not within the valid stack range.

Abstract: In a compiler, a method of generating assembly code for stack unwinding is disclosed. One or more source code lines are obtained. Assembly code for the one or more source code lines is then generated. The assembly code includes one or more stack unwind assembler having one or more associated stack unwind sub directives. Each of the stack unwind assembler directives is adapted for indicating to an assembler that one or more encoded data sections containing stack information to be used for stack unwinding is to be generated in an object file from the one or more associated stack unwind sub directives.

Abstract: Systems, methods, and devices are provided for instruction architecture. One embodiment includes a first integrated circuit (IC). The first IC includes at least two instruction stacks and an arbiter coupled to the at least two instruction stacks. A second IC is provided. The first and the second ICs are coupled using a serial interface.

Abstract: A pipelined, simultaneous and redundantly threaded (“SRT”) processor comprising, among other components, load/store units configured to perform load and store operations to or from data locations such as a data cache and data registers and a cycle counter configured to keep a running count of processor clock cycles. The processor is configured to detect transient faults during program execution by executing instructions in at least two redundant copies of a program thread and wherein false errors caused by incorrectly replicating cycle count values in the redundant program threads are avoided by implementing a cycle count queue for storing the actual values fetched by read cycle count instructions in the first program thread. The load/store units then access the cycle count queue and not the cycle counter to fetch cycle count values in response to read cycle count instructions in the second program thread.

Abstract: A system and method for managing utilization in a unidirectional stack. An application programming interface (API) is provided for facilitating user interaction with a stack management system associated with a computing environment such as an architectural simulator. The unidirectional stack is initialized via the API with respect to a fixed stack marker boundary, a stack base and a stack pointer. A high water mark is maintained for tracking the stack pointer's farthest location from the stack base during the execution of a program. When a program instruction is operable to access a stack location, one or more validity rules are applied to determine if the access operation is permissible. Where the program instruction is operable to modify the stack pointer, another set of validity rules are applied to determine if the stack pointer operation is permissible. User warning and optional return of program control are available when an invalid access operation or stack pointer operation is attempted.

Abstract: A central processing unit (CPU) for easily testing and debugging an application program, which includes a data communications unit for performing data communications with a host computer, a status register having a flag representing whether an operational mode of the CPU is a general operational mode representing a general operational state or a debugging mode representing a debugging state, a debugging stack pointer register which is used as a stack pointer designating a stack memory storing data of a debugging program, and a comparator for comparing a value stored in a break register with break data, wherein the CPU is converted into the debugging mode if the break register value is same as the break data, the flag of the status register has a value representing a debugging mode, a start address for performing a debugging program is loaded in a program counter, and the debugging program is executed to perform a debugging according to a command from the host computer via the data communications unit.

Abstract: Apparatus and methods to track a register value. A microprocessor can include a first register, a control circuit, and an adder. The first register can store a tracked register value. The control circuit can include an instruction input to receive at least a portion of an instruction and a first output to output an arithmetic operation indication. The adder can include a control input to receive the arithmetic operation indication, a first input to receive an immediate operand of an instruction, and a second input to receive the tracked register value.

Abstract: A system and method for managing stack utilization in a two-stack arrangement wherein the stacks are operable to grow towards each other. An application programming interface (API) is provided for facilitating user interaction with a stack management system associated with a computing environment such as an architectural simulator. Each of two stacks is initialized via the API with a stack base, a growth direction indicator and a stack pointer. High water marks are maintained for tracking each stack pointer's farthest location from the respective stack base during the execution of a program. When a program instruction is operable to access a location in either of the stacks, one or more validity rules are applied to determine if the access operation is permissible. Where the program instruction is operable to modify either of the stack pointers, another set of validity rules are applied to determine if the stack pointer operation is permissible.

Abstract: A method of executing a stack-based program using a processor having a register-based architecture, the processor having means for simulating a stack using a subset of its registers such that the processor may operate in a simulated stack-based mode as well as a register-based mode. The method comprises the steps of fetching stack-based instructions from a program memory, translating individual stack-based instructions or sequences of stack-based instructions into register-based instructions, and including in at least certain of the translated instructions an indication that these instructions are to be executed using the simulated stack-based mode. Translated instructions, including said indication, are executed using the simulated stack-based mode, and other translated instructions are executed using the register-based mode.

Abstract: A processor includes a CPU, a data memory, a stack memory, a memory address generator, and a stack pointer generator. The CPU is used to process data and instructions. The data memory is used to store non-stack data. The stack memory is used to store stack data. The memory address generator is used to generate addresses for accessing the data memory. The stack pointer generator is used to generate pointers for accessing the stack memory.

Abstract: A microprocessor may be switchable between a normal mode and a test mode for performing a test program and may include a central processing unit (CPU) for saving contextual data in a stack of the microprocessor at the time of switching to the test mode. The CPU may deliver, at the beginning of the test program and on an input/output port, contextual data present in the stack beginning with the top of the stack. The CPU may also decrement a stack pointer by a value corresponding to a number of contextual data delivered.

Abstract: There is provided a data processing apparatus capable of increasing a number of general purpose registers while maintaining upper compatibility. Register designating information for designating a register is divided in two portions. The two portions are arranged in separate basic units on the basic units of an instruction code. When one instruction code is made ignorable and the ignorable instruction code is ignored, a control unit (CONT) executes register selecting operation by implicitly assuming predetermined register designating information. Thereby, when only a general purpose register (existing general purpose register) capable of being designated implicitly is used, the ignorable instruction code can be ignored and accordingly, the instruction codes are not increased. When an at least conventionally equivalent general purpose register is used, a conventionally equivalent instruction code may be used. By preventing the instruction codes from increasing, processing speed is not reduced.

Abstract: A floating point processor including a plurality of explicitly-addressable processor registers, an emulation register capable of storing a value used to logically rename the explicitly-addressable registers to emulate registers of a floating point stack, a computer-executable software process for calculating and changing a value in the emulation register to a value indicating a change in addresses of registers of a floating point stack when executing a floating point stack operation, and adder circuitry combining a register address and the value in the emulation register in response to the computer-executable process to rename the plurality of explicitly-addressable processor registers.

Abstract: A microprocessor architecture for executing byte compiled Java programs directly in hardware. The microprocessor targets the lower end of the embedded systems domain and features two orthogonal programming models, a Java model and a RISC model. The entities share a common data path and operate independently, although not in parallel. The microprocessor includes a combined register file in which the Java module sees the elements in the register file as a circular operand stack and the RISC module sees the elements as a conventional register file. The integrated microprocessor architecture facilitates access to hardware-near instructions and provides powerful interrupt and instruction trapping capabilities.

Abstract: In general, the invention relates to a method for optimized execution of a computer program including detecting a preservable static field in said computer program with a compiler, comprising detecting at least one selected from the group consisting of a getstatic instruction and a putstatic instruction, annotating said preservable static field to create an annotation indicating whether said field is preservable, compiling said computer program to produce an output using said annotation, wherein said output includes information about said field, encoding said output if backward compatibility is required, loading said output, and executing said output in an environment.

Abstract: Among the embodiments of the present invention is a processor (22) having a number of registers in a register bank (50). The registers include a general purpose register (52a) and a stack pointer register (52b) having a common register name. Processor (22) includes logic responsive to programming to perform a program instruction that references the common register name. This instruction is performed with general purpose register (52a) under a first condition and with stack pointer register (52b) under a second condition. Accordingly, multiple registers identified by the same name can be selectively accessed based on the establishment of certain conditions.

Abstract: Method and apparatus for managing access to registers that are outside a current register stack frame are disclosed. An instruction execution unit in a processor receives an instruction to be executed. A processor includes a register stack, the register stack including a plurality of register stack frames. Each of the register stack frames includes zero or more registers. One of the plurality of register stack frames is a current register stack frame. When execution of the instruction requires writing to a register referenced by the instruction, the instruction execution unit determines whether the register referenced by the instruction is within the current register stack frame. If the instruction execution unit determines that the register is not within the current register stack frame, the instruction execution unit does not execute the instruction and may, for example, generate a fault.

Abstract: A method and a device for performing stack operations within a processing system. A first and second stack pointers point to a top of a stack and to a memory location following the top of the stack. A first stack pointer is used during pop operations and a second stack pointer is used during push operations. When a stack pointer is selected, it replaces the other stack pointer. The selected memory pointer is provided to a memory module in which a stack is implemented, and is also updated. When a pop operation is executed the updated stack pointer points to a memory location preceding a memory location pointed by the selected stack pointer and when a push operation is executed the updated stack pointer points to a memory address following that address.

Abstract: A scaleable microprocessor architecture has an efficient and orthogonal instruction set of 20 basic instructions, and a scaleable program word size from 15 bits up, including but not limited to 16, 24, 32, and 64 bits. As many instructions are packed into a single program word as allowed by the size of a program word. An integral return stack is used for nested subroutine calls and returns. An integral data stack is also used to pass parameters among nested subroutines. The simplified instruction set and the dual stack architecture make it possible to execute all instructions in a single clock cycle from a single phase master clock. Additional instructions can be added to facilitate accessing arrays in memory, for multiplication and division of integers, for real time interrupts, and to support an UART I/O device. This scaleable microprocessor architecture greatly increases code density and processing speed while decreasing significantly silicon area and power consumption.

Abstract: The present invention provides a non-copy shared stack and register set device and a dual language processor structure using the same, which achieve non-copy data sharing by controlling a selector and the stack pointer of a data stack. The selector is connected to each item of the data stack and a register of the register set, such that, when the register set requires to exchange data with the data stack, the selector is controlled and the stack pointer is updated thereby the selector is switched to make the stack item pointed by the stack pointer communicate with the register.

Abstract: A method includes pushing a datum onto a stack by a first processor and popping the datum off the stack by a second processor.

Abstract: The present invention provides a data processing apparatus and method for executing stack-based instructions specifying operations to be executed upon stack data items held in a stack, a first type of stack data item having a first size and a second type of stack data item having a second size. The data processing apparatus comprises a register bank containing a plurality of “n” bit registers for storing data items, a set of registers within the register bank being allocatable to hold stack data items from a portion of the stack, and each register in the set being able to store as an n-bit value a stack data item of the first type or a stack data item of the second type. An arithmetic logic unit is then provided for executing operations upon data items held in the registers.

Abstract: A method and apparatus for fault handling in computer systems. In one embodiment, a first register is used to store an address which points to the top of a stack. The address stored in the first register may be updated during the execution of an instruction. A second register may be used to store an address previously first register. The contents of the second register may be kept unchanged until the retirement of the instruction that is currently executing. If a fault occurs during execution of the instruction, a microcode fault handler may perform routines that may clear the fault or those conditions which led to the fault. The microcode fault handler may also copy the contents of the second register back into the first register. Execution of the instruction may be restarted from the operation just prior to when the fault occurred. The program from which the instruction originated may then continue to run.

Abstract: A computer system comprising a data file having entries each of which is designed to hold data, an advanced and a completed mapping file each having entries each of which is designed to hold a data-file-entry address, an operation window that is a buffer to hold substances of operations waiting execution, and a state-modification queue that is designed to be able to hold a substance of a modification on the advanced mapping file for each clock cycle; wherein making a modification on the advanced mapping file, entering the substance of this modification into the state-modification queue, and entering substances of operations into the operation window are each to be done in one clock cycle, and operations held in the operation window are to be executed out of order. The system can attain high performance easily and utilize programs described in any machine language for traditional register-based/stack-based processors.

Abstract: A computer system for accelerated processing of stack oriented interpretive language instructions comprising a translator which establishes correlations between address values and core operations, a processing accelerator core for performing core operations, a cache memory for storing operand data, a control logic device for reading and writing operand data and for determining core operations corresponding with address values and an arithmetic logic unit for receiving data and performing core operations, being specified solely by address values.

Abstract: A data processor comprises an arithmetic logic unit [ALU] for carrying out an arithmetic or logic operation on a first and second input data [OP1, OP2]. It further comprises a stack [STCK] for storing data and for applying a data having a certain position [P(1)] in the stack to the arithmetic logic unit [ALU] as the first input data [OP1]. The data processor can execute an instruction [INSTR] which comprises an address [ADDR] indicating a memory location [REG(i)] among a plurality of memory locations [REG]. The address [ADDR] causes a data, which is contained in the memory location [REG(i)] that it indicates, to be applied to the arithmetic logic unit [ALU] as the second input data [OP2].

Abstract: The data processing circuit of this invention enables efficient description and execution of processes that act upon the stack pointer, using short instructions. It also enables efficient description of processes that save and restore the contents of registers, increasing the speed of processing of interrupts and subroutine calls and returns. A CPU that uses this data processing circuit comprises a dedicated stack pointer register SP and uses an instruction decoder to decode a group of dedicated stack pointer instructions that specify the SP as an implicit operand. This group of dedicated stack pointer instructions are implemented in hardware by using general-purpose registers, the PC, the SP, an address adder, an ALU, a PC incrementer, internal buses, internal signal lines, and external buses.

Abstract: The data processing device maintains two stacks. The length of the basic unit of information is different for each stack. Pops and pushes cause a change in the stack pointer which differs dependent on which stack is used. Instructions refer to different locations on the stack as registers defined by an offset of a number of basic units relative to the top of stack. In an embodiment a reference to registers is normally interpreted as a reference to one of a set of registers (including the top of stack register) without push or pop, but a reference to one register is interpreted as a reference to top of stack including a push or pop.

Abstract: A processor comprises an arithmetic logic unit (ALU) that co-operates with a stack arrangement (STCK). The processor is arranged to execute instructions (INSTR) which include a stack control field (SCF) and an opcode field (OPF) for controlling the stack arrangement (STCK) and the arithmetic logic unit (ALU), respectively.

Abstract: A memory architecture in accordance with an embodiment of the present invention improves the speed of method invocation. Specifically, method frames of method calls are stored in two different memory circuits. The first memory circuit stores the execution environment of each method call, and the second memory circuit stores parameters, variables or operands of the method calls. In one embodiment the execution environment includes a return program counter, a return frame, a return constant pool, a current method vector, and a current monitor address. In some embodiments, the memory circuits are stacks; therefore, the stack management unit to cache can be used to cache either or both memory circuits. The stack management unit can include a stack cache to accelerate data transfers between a stack-based computing system and the stacks. In one embodiment, the stack management unit includes a stack cache, a dribble manager unit, and a stack control.

Abstract: A processor comprises an arithmetic logic unit (ALU) that co-operates with a stack arrangement (STCK). The processor is arranged to execute instructions (INSTR) which include a stack control field (SCF) and an opcode field (OPF) for controlling the stack arrangement (STCK) and the arithmetic logic unit (ALU), respectively.