Abstract: A memory system includes: a storage device for storing data; a system memory in which normal firmware and debugging firmware are stored; a firmware implementer for implementing the normal firmware or the debugging firmware; and a controller for controlling the storage device in a normal mode in which the memory system is driven by the normal firmware. When an error detected in the normal mode is uncorrectable, the controller uploads the debugging firmware stored in the system memory to the firmware implementer to change the normal mode to a debugging mode. The firmware implementer performs a debugging operation on the storage device by implementing the uploaded debugging firmware.

Abstract: In one example, a hardware accelerator comprises: a programmable hardware instruction decoder programmed to store a plurality of opcodes; a programmable instruction schema mapping table implemented as a content addressable memory (CAM) and programmed to map the plurality of opcodes to a plurality of definitions of operands in a plurality of instructions; a hardware execution engine; and a controller configured to: receive an instruction that includes a first opcode of the plurality of opcodes; control the hardware instruction decoder to extract the first opcode from the instruction; obtain, from the instruction schema mapping table and based on the first opcode, a first definition of a first operand; and forward the instruction and the first definition to the hardware execution engine to control the hardware execution engine to extract the first operand from the instruction based on the first definition, and execute the instruction based on the first operand.

Abstract: A scheduler of a batch job management service determines that a set of resources a client is insufficient to execute one or more jobs. The scheduler prepares a multi-dimensional statistical representation of resource requirements of the jobs, and transmits it to a resource controller. The resource controller uses the multi-dimensional representation and resource usage state information to make resource allocation change decisions.

Abstract: A predetermined field of a fetched instruction is extended to secure an instruction type and an operand length. An instruction conversion table stores an extension field longer than the predetermined field in association with a bit pattern of the predetermined field of an instruction. An extension field acquisition unit acquires the extension field by referring to the instruction conversion table, with a bit pattern of the predetermined field of the fetched instruction. An instruction decoder performs a decoding process on a new instruction including the extension field in place of the predetermined field of the fetched instruction.

Abstract: A method of generating an output log for analysis of a computer program, the method comprising: receiving a recording of an execution of the program; receiving an additional print instruction to print a value of a data item and an indication of a point in the program at which the additional print instruction is to be evaluated; determining a corresponding point in the recording of the execution based upon the indication of the point in the program; and evaluating the additional print instruction based upon the recording of the execution and the determined corresponding point to determine an output of the additional print instruction for insertion into the output log.

Abstract: A data processor comprising a plurality of registers, and instruction execution circuitry having an associated instruction set, wherein the instruction set includes an instruction specifying at least a mask operand, a register operand and an immediate value operand, and the instruction execution circuitry, in response to an instance of the instruction, determines a Boolean value based on the mask operand and sets a respective one of a plurality of registers specified by the register operand of the instance to a value of the immediate value operand if the Boolean value is true. The instruction execution circuitry, in response to the instance of the instruction, may set the respective one of the plurality of registers specified by the register operand of the instance to zero if the Boolean value is false.

Abstract: An emulator can use compiler metadata to efficiently emulate execution of executable machine code compiled from the source code. Based on accessing compiler metadata associated with machine code, an emulator can identify behavior(s) of the source code from which the machine code is compiled which are not implied by the machine code. From these behaviors, the emulator can identify emulator optimization(s) that can be applied, during emulation of execution of a thread, to reduce a number of steps needed to emulate execution the machine code, while preserving any externally-visible side-effects. These optimizations can operate to reduce a number of emulator operations needed emulate execution of the machine code, or to elide one or more machine code instructions from emulation. These optimizations can then be applied while emulating execution of the thread. The emulated execution could be recorded to a trace that is equivalent to a trace recorded without these optimizations.

Abstract: Embodiments of the present invention provide a system for balancing a global completion table (GCT) in a microprocessor via frontend steering or stalls. A non-limiting example of the system includes an instruction dispatch unit (IDU) that includes an instruction queue and the system includes an instruction sequencing unit (ISU) that includes a GCT having a first area and a second area. The IDU is configured to determine whether a full group of instructions exist in the instruction queue and to determine whether additional instructions will be received by the instruction queue in a subsequent cycle. The IDU is configured to stall the instruction queue for at least one cycle until a full group of instructions is accumulated at the instruction queue upon determining that additional instructions will be received by the instruction queue in subsequent cycle.

Abstract: A method for performing a high-level compilation of a computer program language (CPL) description of a system to generate a hardware description language (HDL) of the system includes inserting one or more compression/decompression units into the HDL in response to detecting a user inserted term in a kernel definition of an argument in the CPL description to indicate that the argument requires compression.

Abstract: In an aspect, the present disclosure provides a method that comprises automatic generation of a NoC from specified topological information based on projecting NoC elements of the NoC onto a grid layout. In an aspect, the specified topological information, including specification of putting constraints on positions/locations of NoC elements and links thereof, can be input by a user in real space, and can then be projected on the grid layout.

Abstract: Aspects of the present disclosure provide systems and methods for automatic generation of physically aware aggregation/distribution networks that enable optimized arrangement of a plurality of hardware elements, and provide positions and connectivity for one or more intermediate hardware elements. One or more intermediate hardware elements can be configured to aggregate signals/commands/messages/data from their corresponding hardware elements or from other intermediate hardware elements, and send the aggregated signals/commands/messages/data to a root hardware element that acts as a communication interface for the network. The intermediate hardware elements can also be configured to segregate/distribute signals/commands/message received from the root hardware element to a plurality of specified hardware elements and/or intermediate hardware elements.

Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing and using a partial-address select-signal generator with address shift.

Abstract: Intelligent application back stack management may include generating a first back stack for activities of an application that have been executed by a device that executes the application. The first back stack may include a back stack size limit. A further back stack may be generated for selected ones of the activities of the application if a total number of the activities of the application and further activities of the application exceeds the back stack size limit. The first back stack may be an in-memory back stack for the device that executes the application, and the further back stack may include an external on-device back stack for the device that executes the application and/or a Cloud storage based back stack. Intelligent application back stack management may further include regenerating an activity of the selected ones of the activities that is pulled from the further back stack.

Abstract: A data processor comprising a plurality of registers, and instruction execution circuitry having an associated instruction set, wherein the instruction set includes an instruction specifying at least a mask operand, a register operand and an immediate value operand, and the instruction execution circuitry, in response to an instance of the instruction, determines a Boolean value based on the mask operand and sets a respective one of a plurality of registers specified by the register operand of the instance to a value of the immediate value operand if the Boolean value is true. The instruction execution circuitry, in response to the instance of the instruction, may set the respective one of the plurality of registers specified by the register operand of the instance to zero if the Boolean value is false.

Abstract: Disclosed are an asynchronous pipeline system, a stage, and a data transfer mechanism. The asynchronous pipeline system having a plurality of stages based on a 4-phase protocol, includes: a first stage among the plurality of stages; and a second stage among the plurality of stages connected next to the first stage, wherein the first stage transmits and the second receives bundled data and control data through an always bundled data channel and on-demand data through an on-demand data channel according to need of the second stage.

Abstract: A method of an aspect includes generating real time instruction trace (RTIT) packets for a first logical processor of a processor. The RTIT packets indicate a flow of software executed by the first logical processor. The RTIT packets are stored in an RTIT queue corresponding to the first logical processor. The RTIT packets are transferred from the RTIT queue to memory predominantly with firmware of the processor. Other methods, apparatus, and systems are also disclosed.

Abstract: A resource-constrained device comprises a processor configured to execute multiple instruction streams comprising multiple instructions having an opcode and zero or more operands. Each of the multiple instruction streams is associated with one of multiple instruction execution modes having an instruction set comprising multiple instruction implementations. At least one of the multiple instruction implementations is configured to change the processor from a first instruction execution mode to a second instruction execution mode. The processor comprises an instruction fetcher configured to fetch an instruction from one of the multiple instruction streams based at least in part upon a current instruction execution mode.

Abstract: A microprocessor includes an instruction translation unit that extracts condition information from the IT instruction and fuses the IT instruction with the first IT block instruction. For each instruction of the IT block, the instruction translation unit: determines a respective condition for the IT block instruction using the condition information extracted from the IT instruction and translates the IT block instruction into a microinstruction. The microinstruction includes the respective condition. Execution units conditionally execute the microinstruction based on the respective condition. For each IT block instruction, the instruction translation unit determines a respective state value using the extracted condition information. The state value comprises the lower eight bits of the IT instruction having the lower five bits left-shifted by N-1 bits, where N indicates a position of the IT block instruction in the IT block.

Abstract: An embodiment generally pertains to a method of secure address handling in a processor. The method includes detecting an instruction that implicitly designates a target address and retrieving an encoded location associated with the target address. The method also includes decoding the encoded location to determine the target address. Another embodiment generally relates to detecting an instruction having an operand designating an encoded target address and determining a location of a target instruction associated with the target address. The method also includes determining a location of a subsequent instruction and encoding the location of the subsequent instruction. The method further includes storing the encoded location of the subsequent instruction.

Abstract: A microprocessor includes a hardware instruction translator that translates x86 ISA and ARM ISA machine language program instructions into microinstructions, which are encoded in a distinct manner from the x86 and ARM instructions. An execution pipeline executes the microinstructions to generate x86/ARM-defined results. The microinstructions are distinct from the results generated by the execution of the microinstructions by the execution pipeline. The translator directly provides the microinstructions to the execution pipeline for execution. Each time the microprocessor performs one of the x86 ISA and ARM ISA instructions, the translator translates it into the microinstructions. An indicator indicates either x86 or ARM as a boot ISA. After reset, the microprocessor initializes its architectural state, fetches its first instructions from a reset address, and translates them all as defined by the boot ISA. An instruction cache caches the x86 and ARM instructions and provides them to the translator.

Abstract: A system and method for improving software maintainability, performance, and/or security by associating a unique marker to each software code-block; the system comprising of a plurality of processors, a plurality of code-blocks, and a marker associated with each code-block. The system may also include a special hardware register (code-block marker hardware register) in each processor for identifying the markers of the code-blocks executed by the processor, without changing any of the plurality of code-blocks.

Abstract: Disclosed herein are systems, methods, and non-transitory computer-readable storage media for obfuscating branches in computer code. A compiler or a post-compilation tool can obfuscate branches by receiving source code, and compiling the source code to yield computer-executable code. The compiler identifies branches in the computer-executable code, and determines a return address and a destination value for each branch. Then, based on the return address and the destination value for each branch, the compiler constructs a binary tree with nodes and leaf nodes, each node storing a balanced value, and each leaf node storing a destination value. The non-leaf nodes are arranged such that searching the binary tree by return address leads to a corresponding destination value. Then the compiler inserts the binary tree in the computer-executable code and replaces each branch with instructions in the computer-executable code for performing a branching operation based on the binary tree.

Abstract: The memory device comprises a physical memory plane (PMP) comprising m first physical lines (RGP1i) extending along a first direction and n second physical lines (RGP2j) extending along a second direction, reception means for receiving a logical address (ADR) designating a first logical line (RG1i) and a second logical line (RG2j) of a matrix logical memory plane (PML), possessing 2p first logical lines extending along the first direction and 2q second logical lines extending along the second direction, in that m and n are each different from a power of two, m being a multiple of 2k, k being less than or equal to p, and the product of m and n being equal to the nearest integer above 2p+q, and in that it comprises means for addressing the physical memory plane (PMP) that are configured to address a first physical line and a part only of a second physical line on the basis of the content of the said logical address received and of the remainder of a Euclidean division of a part of the content of this logical ad

Abstract: A processor architecture includes a plurality of processing elements and a bus structure. Each element has at least one input port and at least one output port, each port having at least a data bus and a valid data signal line. The bus structure contains a plurality of switches arranged to connect an output port of any first processing element to the input port of any second processing element for a time interval. Each processing element sets a value on the valid data signal line of its output port to a first logic state when the associated data bus contains a transfer value and to a second logic state when it does not contain a transfer value. Each processing element enters a waiting state for a predetermined time interval when the value on the valid data signal line of the associated input port is in the second logic state.

Abstract: An architecture includes a controller. The controller is configured to receive a microprogram. The microprogram is configured for performing at least one of hierarchical or a sequence of polynomial computations. The architecture also includes an arithmetic logic unit (ALU) communicably coupled to the controller. The ALU is controlled by the controller. Additionally, the microprogram is compiled prior to execution by the controller, the microprogram is compiled into a plurality of binary tables, and the microprogram is programmed in a command language in which each command includes a first portion for indicating at least one of a command or data transferred to the ALU, and a second portion for including a control command to the controller. The architecture and implementation of the programmable controller may be for cryptographic applications, including those related to public key cryptography.

Abstract: An apparatus of one aspect includes a microcode storage, a microcode subroutine stored in the microcode storage, and a microcode caller of the microcode subroutine stored in the microcode storage. The microcode caller has a save microinstruction that indicates a destination storage location. The apparatus also includes microcode alias locations. Each of the microcode alias locations is operable to store a value. The value in the microcode alias location corresponds to a parameter passed between the microcode caller and the microcode subroutine. The apparatus includes save logic coupled with the microcode alias locations to receive the values from the microcode alias locations. The save logic is operable, responsive to the save microinstruction, to save the values from the microcode alias locations in the destination storage location indicated by the save microinstruction.

Abstract: An apparatus of an aspect includes a plurality of microcode alias locations and a microcode storage. A microinstruction of a microcode subroutine is stored in the microcode storage. The microinstruction has an indication of a microcode alias location. A microcode caller of the microcode subroutine is also stored in the microcode storage. The microcode caller is operable to specify a location of a parameter in the microcode alias location that is indicated by the microinstruction of the microcode subroutine. The apparatus also includes parameter location determination logic that is coupled with the microcode alias locations. The parameter location determination logic is operable, responsive to the microinstruction of the microcode subroutine, to receive the indication of the microcode alias location from the microinstruction and determine the location of the parameter specified in the microcode alias location indicated by the microinstruction.

Abstract: An electronic device that comprises a processor including an individual instruction and a first group of instructions. The device further comprises a memory externally coupled to the processor, as well as a second group of instructions. When executed, the first group of instructions causes the processor to execute the second group of instructions in lieu of the individual instruction.

Abstract: An instruction processing circuit includes a decoder circuit operable to receive a sequence of instructions and to decode the received sequence of instructions into a first type of sequence of operations, and a trace builder circuit operable to receive at least a portion of the sequence of operations of the first type and to generate, based thereon, a second type of sequence of operations, where the at least a portion of the sequence of operations of the first type represents a first portion of the sequence of instructions, where the first portion of the sequence of instructions includes at most one conditional control transfer instruction that, when present, ends the first portion of the sequence of instructions, and where the sequence of operations of the second type also represents the first portion of the sequence of instructions.

Abstract: A system, method and computer program product for translations in a computer system. The system includes a general purpose register containing a base address of an address translation table. The system also includes a millicode accessible special displacement register configured to receive a plurality of elements to be translated. The system further includes a multiplexer for selecting a particular one of the plurality of elements from the millicode accessible special displacement register and for generating a displacement or offset value. The system further includes an address generator for creating a combined address containing the base address from the general purpose register and the generated displacement or offset value.

Abstract: A data processing system is provided that includes an instruction decoder 20 responsive to a compare and branch instruction CHKA.X that performs a comparison between first and second values stored in first and second registers Rn, Rm respectively. A target branch address is determined from a pre-programmed stored value and a branch to a sub-routine is performed in dependence upon a result of the comparison.

Abstract: In an embodiment, an address generation unit (AGU) is configured to generate a pseudo sum from an index portion of two or more operands. The pseudo sum may equal the index if the carry-in of the actual sum to the least significant bit of the index is a selected value (e.g. zero). The AGU may also include circuitry coupled to receive the operands and to generate the actual carry-in to the least significant bit of the index. The AGU may transmit the pseudo sum and the carry-in to a decode block for a memory array. The decode block may decode the pseudo sum into one or more one-hot vectors. The one-hot vectors may be input to muxes, and the one-hot vectors rotated by one position may be the other input. The actual carry-in may be the selection control of the mux.

Abstract: An information processing device includes: a first processing unit which asserts a first chip select signal or a second chip select signal in accordance with an address space to access; and a second processing unit accessible by the first processing unit by a first access method or a second access method, wherein when asserting the first chip select signal, the first processing unit accesses the second processing unit by the first access method, and when asserting the second chip select signal, the first processing unit accesses the second processing unit by the second access method.

Abstract: A method and system for patching instructions in a 3-D graphics pipeline. Specifically, in one embodiment, instructions to be executed within a scheduling process for a shader pipeline of the 3-D graphics pipeline are patchable. A scheduler includes a decode table, an expansion table, and a resource table that are each patchable. The decode table translates high level instructions to an appropriate microcode sequence. The patchable expansion table expands a high level instruction to a program of microcode if the high level instruction is complex. The resource table assigns the units for executing the microcode. Addresses within each of the tables can be patched to modify existing instructions and create new instructions. That is, contents in each address in the tables that are tagged can be replaced with a patch value of a corresponding register.

Abstract: A system and method for modifying the hardware instruction set of an instruction processor is disclosed. The invention utilizes one or more bits of an instruction opcode and one or more programmable bits stored within the instruction processor to generate a branch address. The branch address is then used to address a storage device such as a microcode RAM to retrieve one or more microcode instructions that control execution of the instruction opcode. Address generation is controlled by selecting a previously unused instruction opcode, then modifying the programmable bits as necessary to generate a desired branch address. By loading modified microcode instructions at the branch address, instruction execution can be modified without changing the hardware design.

Abstract: A processor 6 is provided with an instruction decoder 18 which is responsive to memory access instructions to determine whether the base register value being used matches a null value and if such a match occurs then branches to a null value exception handler.

Abstract: A microprocessor REP MOVS macroinstruction specifies the word length of the string in the IA-32 ECX register. The microprocessor includes a memory, configured to store a first and second sequence of microinstructions. The first sequence conditionally transfers control to a microinstruction within the first sequence based on the ECX register. The second sequence does not conditionally transfer control based on the ECX register. The microprocessor includes an instruction translator, coupled to the memory. In response to a macroinstruction that moves an immediate value into the ECX register, the instruction translator sets a flag and saves the immediate value. In response to a macroinstruction that modifies the ECX register in a different manner, the translator clears the flag. In response to a REP MOVS macroinstruction, the instruction translator transfers control to the first sequence if the flag is clear; and transfers control to the second sequence if the flag is set.

Abstract: A multiple-core processor having a hierarchical microcode store. A processor may include multiple processor cores, each configured to independently execute instructions defined according to a programmer-visible instruction set architecture (ISA). Each core may include a respective local microcode unit configured to store microcode entries. The processor may also include a remote microcode unit accessible by each of the processor cores. Any given one of the processor cores may be configured to generate a given microcode entrypoint corresponding to a particular microcode entry including one or more operations to be executed by the given processor core, and to determine whether the particular microcode entry is stored within the respective local microcode unit of the given core. In response to determining that the particular microcode entry is not stored within the respective local microcode unit, the given core may convey a request for the particular microcode entry to the remote microcode unit.

Abstract: An article comprising an instruction stored on a storage medium. The instruction includes opcode field storing an opcode signal and an operand field storing an operand signal. The operand is compressed prior to being stored in the operand field.

Abstract: A method for register management in a simulation environment including receiving an instruction from an instruction unit decode pipeline. An address generation interlock (AGI) function is executed in the simulation environment if the instruction is an AGI instruction. The executing an AGI function is responsive to a pool of registers controlled by a register manager and to the instruction. An early AGI function is executed in the simulation environment if the instruction is an early AGI instruction. The executing an early AGI function is responsive to the pool of registers and to the instruction.

Abstract: Various embodiments of methods and systems for implementing a set of microcode operations corresponding to a microcoded instruction as a microcode subroutine are disclosed. In one embodiment, a microprocessor includes a dispatch unit configured to dispatch operations and a scheduler coupled to the dispatch unit and configured to schedule dispatched operations for execution. In response to receiving a microcoded instruction, the dispatch unit is configured to dispatch a microcode subroutine call operation that specifies a tag identifying a microcode subroutine.

Abstract: A microprocessor includes an instruction translator that translates a store macroinstruction into exactly one fused store microinstruction. The store macroinstruction in the microprocessor's macroarchitecture macroinstruction set instructs the microprocessor to store data from a general purpose register of the microprocessor to a memory location. The fused store microinstruction is an instruction in the microprocessor's microarchitecture microinstruction set. A reorder buffer (ROB) receives the fused store microinstruction from the instruction translator into exactly one of its plurality of entries. An instruction dispatcher dispatches for execution a store address microinstruction and a store data microinstruction to different respective execution units of the microprocessor in response to receiving the fused store microinstruction. Neither the store address microinstruction nor the store data microinstruction occupy any of the ROB entries.

Abstract: A data processing system 2 is provided which includes an instruction decoder 18 responsive to a handler branch instruction HLB, HBLP which includes an index value field to calculate a handler pointer in dependence upon a handler base address HBA and the index value field and then to branch to that handler pointer position. A handler program 24, 26 at the branch target is then executed following which a return is made to an address following the handler branch instruction using a link address value stored when the handler branch instruction was executed.

Abstract: An extendable instruction set architecture is provided. In an embodiment, a microprocessor includes a memory, a virtual instruction expansion store, and substitution logic. The memory stores at least one virtual instruction that includes an index and at least one parameter. The virtual instruction expansion store includes at least one instruction template and at least one parameter selector. The substitution logic forms a sequence of at least one expanded instruction. In an example, each expanded instruction is based on an instruction template and includes a new parameter for use with the instruction template. The new parameter is generated by performing a logical operation from the parameter selector on one or more parameter of the virtual instruction.

Abstract: A processor comprising a decode logic coupled to a first storage unit and comprising a data structure. The processor also comprises a second storage unit coupled to the decode logic. The decode logic obtains a single instruction from the first storage unit and, if indicated by a first bit in the data structure, processes a group of instructions in lieu of the single instruction, where the single instruction requires an operand. If indicated by a second bit in the data structure, the decode logic obtains the operand from the first storage unit, modifies the operand, and stores the operand to the second storage unit for use by the group of instructions.

Abstract: Embodiments of the present invention relate to high-performance processors, and more specifically, to processors that store all operation information associated with each instruction in a single memory. A processor including multiple programmable logic arrays (PLAs); an instruction pointer queue coupled to the multiple PLAs; and an instruction pointer sequencing logic/predictor component coupled to the instruction pointer queue. The processor further includes a micro-operation cache coupled to the instruction pointer sequencing logic/predictor component; a micro-operation memory coupled to the micro-operation cache; and a trace pipe (TPIPE) coupled to the micro-operation cache and the instruction pointer queue.

Abstract: A system and method of executing an interpretive language in a system having a processing component with native software processes and a memory component. A hardware component is coupled with the processing component and the memory component. The hardware component assists with the processing of the interpretive language and the system is permitted to execute the native software processes of the processing component.

Abstract: A method for register management in a simulation environment including receiving an instruction from an instruction unit decode pipeline. An address generation interlock (AGI) function is executed in the simulation environment if the instruction is an AGI instruction. The executing an AGI function is responsive to a pool of registers controlled by a register manager and to the instruction. An early AGI function is executed in the simulation environment if the instruction is an early AGI instruction. The executing an early AGI function is responsive to the pool of registers and to the instruction.

Abstract: A double indirect method of accessing a block of data in a register file is used to allow efficient implementations without the use of specialized vector processing hardware. In addition, the automatic modification of the register addressing is not tied to a single vector instruction nor to repeat or loop instructions. Rather, the technique, termed register file indexing (RFI) allows full programmer flexibility in control of the block data operational facility and provides the capability to mix non-RFI instructions with RFI instructions. The block-data operation facility is embedded in the iVLIW ManArray architecture allowing its generalized use across the instruction set architecture without specialized vector instructions or being limited in use only with repeat or loop instructions.

Abstract: An apparatus and method for performing a shuffle operation on packed data using computer-implemented steps is described. In one embodiment, a first packed data operand having at least two data elements is accessed. A second packed data operand having at least two data elements is accessed. One of the data elements in the first packed data operand is shuffled into a lower destination field of a destination register, and one of the data elements in the second packed data operand is shuffled into an upper destination field of the destination register.