Abstract: An apparatus and a method are distinguished in that an instruction queue is provided which is configured such that when instruction data are written into the instruction queue and/or when instruction data are read out of the instruction queue, a plurality of defined points within the instruction queue are made to start up selectively. As a result, the incidence of pauses in program execution can be reduced to a minimum.

Abstract: A method for preferentially ordering the retrieval of data from a cache line of a cache within a vertical cache configuration. The method includes the steps of first encoding a set of bits with a processor-preferred order of data retrieval based on the cache configuration. The set of bits is then sent along with the read request via the address bus to the first cache. The cache directory is check to see if a “hit” occurs (i.e., the data is present in that cache). If the data is present, a modified cache controller having preference order logic or a preference order logic component interprets the set of bits and directs the retrieval of the requested data from the cache line according to the preferred order for that cache. If no hit (i.e., a miss) occurs, the read request and the preferred order set of bits are sent to the next level cache. In one embodiment, a single set of bits is utilized.

Abstract: An article comprising an instruction stored on a storage medium. The instruction includes opcode field storing an opcode signal and an operand field storing an operand signal. The operand is compressed prior to being stored in the operand field.

Abstract: A processing system in accordance with the present invention is disclosed. The processing system comprises a processor and a microcode sequencer coupled to the processor. The microcode sequencer includes a plurality of modules. Each of the modules enables a specific function based upon a selection signal from the processor. A system and method in accordance with the present invention provides for many advantages over conventional systems. First of all, there is an efficient register bank and the hardware is smaller and more efficient than a DSP. Finally, since it is possible to program macro instructions for different applications, it is more flexible than DSP systems. It also is smaller, has a lower gate count and is faster to market because it is software programmable. Unlike RISC or coprocessor type systems, only a single assembler is needed to handle DSP and multimedia instructions. In addition, a large cache memory is not required while having a higher code density for a particular application.

Abstract: A microprocessor for providing an extended linear address of more than 32 bits. The extended linear address may be provided by concatenating a linear address with a segment selector extension, or by concatenating the values from two registers. Hierarchical translation of a linear address to a physical address is performed in which the number of levels in the hierarchy depends upon whether the linear address is an extended linear address.

Abstract: A method and apparatus for manipulating data from a processor on a stack memory is disclosed. The method and apparatus comprises aligning a stack pointer (104) in the stack memory (110) to a first memory address (126). The method further comprises incrementing the stack pointer (104) to a second memory address (128). The method further comprises saving data from a register (102) into the stack memory (110) at the second memory address (128). The method further comprises aligning the stack pointer (104) to a next even address if at an odd address when the saving step is complete. The method further comprises performing processor operations. The method further comprises unaligning the stack pointer (104) from the even address back to the odd address. The method further comprises restoring data from the stack memory (110) into the register (102). The method further comprises decrementing the stack pointer (104) from the second memory address (128) to the first memory address (126).

Abstract: An article comprising an instruction stored on a storage medium. The instruction includes opcode field storing an opcode signal and an operand field storing an operand signal. The operand is compressed prior to being stored in the operand field.

Abstract: An arrangement and a method provide instruction processing. Instructions are delivered to a multi-stage pipeline arrangement from at least one instruction source. A storing arrangement stores jump address information for jump instructions. The storing arrangement includes at least one FIFO-register. The conditional jump target address information is stored in the FIFO-register while at least the jump instructions are stored in the pipeline arrangement. The jump target address information is delivered from the FIFO-register in such a way that substantially sequential and continuous prefetching of the instructions is enabled irrespective of the number of conditional jumps and irrespective of whether the jumps are taken or not.

Abstract: An apparatus and method for correcting a call/return stack internal to a microprocessor is provided. In the case of a call, the microprocessor pushes the return address onto the internal call/return stack and in the case of a return, the microprocessor pops the return address from the internal call/return stack into the instruction register. However, prior to speculative execution of the call or return, the correction apparatus stores correction information to enable correction of the internal call/return stack. If the conditional branch instruction was mispredicted, the correction apparatus corrects the internal call/return stack based on the correction information previously stored. The correction information is stored in stack memories so that corrections can be made in the reverse order of which the incorrect modifications to the internal call/return stack were made.

Abstract: A processing system in accordance with the present invention is disclosed. The processing system comprises a processor and a microcode sequencer coupled to the processor. The microcode sequencer includes a plurality of modules. Each of the modules enables a specific function based upon a selection signal from the processor. A system and method in accordance with the present invention provides for many advantages over conventional systems. First of all, there is an efficient register bank and the hardware is smaller and more efficient than a DSP. Finally, since it is possible to program macro instructions for different applications, it is more flexible than DSP systems. It also is smaller, has a lower gate count and is faster to market because it is software programmable. Unlike RISC or coprocessor type systems, only a single assembler is needed to handle DSP and multimedia instructions. In addition, a large cache memory is not required while having a higher code density for a particular application.

Abstract: A method of use of real time machine control software integrating both event based mode and task based components. In particular, a collection of constructs have been created that allow machine control applications to be expressed in event based terms and the event based constructs to be seamlessly integrated with task based constructs. The method includes the use of response time specifications, in particular in conjunction with ReactiveTask and Task constructs. The method also includes the use of Register, ReferenceClock, and SchedulerLock constructs.

Abstract: In an information processing apparatus, priorities are assigned to a plurality of central processing units (CPUS) and the CPUs transfer their respective display lists of drawing instructions to a drawing unit on a priority basis. With such a scheme, when a master CPU (Geometry Subsystem 0) is creating a display list (List #0-1) and a drawing unit (a rendering system) is in an idle state, a right to make an access to the drawing unit is handed over to a slave CPU (Geometry Subsystem 1), enabling the slave CPU to supply a display list (List 1-1) created thereby, if any, to the drawing unit. Receiving the display list (List #1-1), the drawing unit starts drawing processing in accordance with List #1-1. As the master CPU completes the creation of the display list (List #0-1), the slave CPU returns the right to make an access to the drawing unit to the master CPU, enabling the master CPU to supply List #0-1 to the drawing unit.

Abstract: A microprocessor capable of executing a process instruction having at least one RISC type instruction is constructed to include an instruction decoding section for decoding a microcode including information which indicates transfer contents of input and output data and address information which indicates a storage location of the process instruction, a data reading section for reading input data corresponding to the information which indicates the transfer contents of the input and output data decoded by the instruction decoding section and reading the process instruction corresponding to the address information, and an operation process executing section for implementing one or a plurality of operation unit resources capable of executing an operation process according to the input data read by the data reading section and the process instruction.

Abstract: A superscalar processor and method are disclosed for efficiently recovering from misaligned data addresses. The processor includes a memory device partitioned into a plurality of addressable memory units. Each of the plurality of addressable memory units has a width of a first plurality of bytes. A determination is made regarding whether a data address included within a memory access instruction is misaligned. The data address is misaligned if it includes a first data segment located in a first addressable memory unit and a second data segment located in a second addressable memory unit where the first and second data segments are separated by an addressable memory unit boundary. In response to a determination that the data address is misaligned, a first internal instruction is executed which accesses the first memory unit and obtains the first data segment. A second internal instruction is executed which accesses the second memory unit and obtains the second data segment.

Abstract: A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instructions in-order.

Abstract: A general-use register set includes a plurality of registers in a central processing unit body. A register-bank memory has memory regions relevant to the plurality of registers and is connected to the central processing unit. An output signal of an address circuit included in the central processing unit is supplied to the register-bank memory. Alternatively, an output signal of a decoding circuit included in the central processing unit may be supplied to the register-bank memory. A signal for selecting either activation or deactivation of the register-bank memory is a signal which indicates a selection of the deactivation of the register-bank memory except in a case where data is written in the general-use register set and a case of a restoration operation after register bank switching.

Abstract: A microprogrammable microprocessor that stores microprogramming instruction sets in a dual ROM configuration enhancing reusability of subroutine operations common between two or more instructions. A first ROM contains a look up table identifying the subroutine(s) utilized by each instruction. The second ROM contains the subroutines needed to implement the required operations for each instruction. The dual ROM microprogrammable microprocessor is used in a Universal Serial Bus microcontroller development system having a microprocessor, control circuit, and an interface to USB bus. The microprocessor system state and I/O registers are mapped to a system bus sharing the same lines with a control circuit. The control circuit provides an RS-232 interface to an attached computing device able to write and read data words to the system bus, thereby to control the microprocessor and associated hardware by setting the system state and writing/reading data from RAM.

Abstract: An embodiment of the invention is directed at a method for accessing a cache by detecting a branch instruction having an address and containing a first set of bits representing a displacement value, and generating a modified instruction containing a second set of bits representing a combination based on the first set of bits and the address.

Abstract: The present invention utilizes a cache which stores various decoded instructions, or parcels, so that these parcels can be made available to the execution units without having to decode a microprocessor instruction, such as a CISC instruction, or the like. This increases performance by bypassing the fetch/decode pipeline stages on the front end of the microprocessor by using a parcel cache to store previously decoded instructions. The parcel cache is coupled to the microprocessor fetch/decode unit and can be searched during an instruction fetch cycle. This search of the parcel cache will occur in parallel with the search of the microprocessor instruction cache. When parcel(s) corresponding to the complex instruction being fetched are found in the parcel cache a hit occurs and the corresponding micro-ops are then sent to the execution units, bypassing the previous pipeline stages.

Abstract: Dynamically typed registers in a processor are provided by associating a type specifier with a register specifier for each register in the processor, storing the register specifiers and associated type specifiers in a register type table. The type specifier associated with an operand register of an instruction is employed to dispatch the instruction to an appropriate execution unit within the processor. The results of the instruction are stored in a register having an associated type specifier matching the execution unit type. Register specifiers are dynamically allocated to particular execution units within the processor by altering the type specifier associated with the register specifiers. Register values may be either discarded or converted when the register specifier type is altered. A general instruction allows conversion of the value from one type to another without storing the converted value in memory.

Abstract: A compiler system (190) stores a data structure (101, e.g., a program) to a memory (110) of an execution system (100). The data structure (101) comprises, for example, processor instructions coded by compressed portions of variable lengths. The compiler system (190) partitions some or all memory lines (115) of the memory (110) into P≧2 partitions, e.g., &agr; and &bgr;, and writes code portions A to a first partition (e.g., &agr;) and second code portions B to a second partition (e.g., &bgr;) of an adjacent memory line (115). The compiler system (190) also stores addresses for some or all of the code portions in, for example, the memory (110). The addresses (260) have pointers (a and b) which indicate start positions (jA and jB) for portions A and B. Optionally, pointer magnitudes distinguish portion-to-pointer relations without the need for further identification bits.

Abstract: The processor is configured to predecode instruction bytes prior to their storage within an instruction cache. During the predecoding, relative branch instructions are detected. The displacement included within the relative branch instruction is added to the address corresponding to the relative branch instruction, thereby generating the target address. The processor replaces the displacement field of the relative branch instruction with an encoding of the target address, and stores the modified relative branch instruction in the instruction cache. The branch prediction mechanism may select the target address from the displacement field of the relative branch instruction instead of performing an addition to generate the target address. In one embodiment, relative branch instructions having eight bit and 32-bit displacement fields are included in the instruction set executed by the processor.

Abstract: The object space manager circuit is a device used in computer memory systems for determining the address of the first word of an object, given the address of any other word in the same object. It consists of a first-object-word encoding circuit, a memory circuit, and a first-object-word decoding circuit. The encoding circuit utilizes a hierarchical coding system to generate codes that relate the address of a first object word to any other object word. This particular coding system results in codes that are the same for particular ranges of object word addresses. The codes are stored in the memory circuit which permits the entry of a code at each address of a specified range of memory addresses to be accomplished simultaneously. The decoding circuit utilizes an input object-word address to retrieve the associated codes from the memory and then translates these codes into the address of the first object word.

Abstract: An apparatus and method for improving the execution of floating point instructions in a microprocessor is provided. During decode of a floating point instruction, translation logic generates absolute addresses of specified registers in a floating point register file. These absolute references, as opposed to relative references to a top-of-stack, are inserted into associated micro instructions. In the event of an exception, synchronization logic provides an architected top-of-stack for the floating point instruction associated with the exception to the translation logic so that subsequent instructions will properly reference floating point registers.

Abstract: Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.

Abstract: A method and apparatus for reducing processor response time to selected transfer instructions in an multi-instruction processor. The response time is shortened by using a fast path to generate addresses for selected transfer instructions. In this fast path a base address, retained in a register from a previous instruction, is summed with an offset from the current instruction to obtain an absolute address for memory accessing. Before the fast path is entered determinations are made whether the instruction is a particular transfer instruction of a particular class and subclass, and whether the base address is different than the base address for the previous instruction. Even through the fast path is entered the usual absolute address generator path is also entered where the instruction is subjected to both high and low limit tests.

Abstract: A microcode based decoder circuit for microprocessors that uses fast access tables to decode instructions. The pointers to the tables are generated directly from the instruction prefetch buffers. Information bits about the instruction are added to the tables at no extra cost and enable the faster decode of the instruction. The present invention includes the decode of an instruction using an entry ROM, which contains information regarding the instruction that can directly be used in generating the decoder outputs. This information is also used in selecting the correct ROM entry, thus enhancing the flexibility of the decoder, and to dynamically generate a generic microcode entry. Thus, microcode space requirements are reduced. A generic microcode instruction is used for commonly used, similar macroinstructions. This avoids duplication of microcode instructions and thus reduces the required microcode space.

Abstract: A flash reconfigurable programmable logic device is applied as a dynamic execution unit for a sequence of instructions. The sequence of instructions includes control portion, and a portion which indicates which configuration of the flash configurable programmable logic device is to be used with that instruction. In each execution cycle, a configuration is selected in accordance with the instruction being executed, switching from one configuration of the programmable logic device to any other configuration stored on the device in a single cycle. The configuration store stores a set of configuration words defining respective logic functions of the configurable logic elements in the programmable logic device. The configuration select circuits operate to apply a selected configuration word from the set of configuration words to configure the configurable logic elements. An instruction store stores a sequence of instructions for execution by the programmable logic device.

Abstract: A microprocessor comprises one or more instruction pipelines having a plurality of stages for processing a stream of instructions, with one or more of said instructions referencing a set of logical registers. A plurality of physical registers are allocated to store data associated with the logical registers by register translation circuitry. The register translation circuitry is selectively controlled by the microcode or by hardware signals generated by one or more of the stages.

Abstract: To provide a signal processor for performing processing in fewer cycles by selecting one of the two different operations in accordance with a flag signal and performing the selected operation without the use of a conditional branch instruction, the signal processor is provided with an instruction decoder, a control selecting circuit, a selecting circuit and an arithmetic unit. The instruction decoder decodes an instruction to output two control signals. The control selecting circuit is connected to the instruction decoder and selects one of the control signals in accordance with a flag signal stored in a flag holding circuit to output the selected signal. The selecting circuit selects one of a plurality of input data in accordance with the control signal outputted by the control selecting circuit and outputs the selected data. The arithmetic unit performs an operation on the data outputted by the selecting circuit.

Abstract: An apparatus and method for performing a shuffle operation on packed data using computer-implemented steps is described. In one embodiment, a first packed data operand having at least two data elements is accessed. A second packed data operand having at least two data elements is accessed. One of the data elements in the first packed data operand is shuffled into a lower destination field of a destination register, and one of the data elements in the second packed data operand is shuffled into an upper destination field of the destination register.

Abstract: An asynchronous circuit having a pipelined completion mechanism to achieve improved throughput.

Abstract: A superscalar microprocessor implements a repeated string instruction by putting the microcode unit in a continuous loop. The microcode sequence that implements the repeated string operation includes a conditional-exit instruction rather than a conditional branch and decrement microcode instruction. A conditional-exit instruction decrements a loop count value and conveys a termination signal to a microcode unit when a termination condition is detected. Because several iterations of the instructions that implement the string instruction may be dispatched before the conditional-exit instruction is evaluated, the additional iterations of the microcode loop are canceled. By eliminating the conditional branch and decrement microcode instruction, a loop iteration may be executed in a single clock cycle by three functional units.

Abstract: A computer processor with a mechanism for improved prefetching of instrucns into a local cache includes an instruction pointer multiplexer that generates one of a plurality of instruction pointers in a first pipeline stage, which is used to produce a physical address from an ITLB lookup. A comparison is performed by compare logic between the physical address (and tags) of a set in the local cache and the set associated with the selected instruction pointer. A way multiplexer selects the proper way output from either the compare logic or an instruction streaming buffer that stores instructions returned from the first cache, but not yet written into the local cache. An instruction is bypassed to the way multiplexer from the instruction streaming buffer in response to an instruction streaming buffer hit and a miss signal by the compare logic.

Abstract: A method of reducing microprocessor peak power by scheduling execution of instructions to multiple execution units. In the prior art, parallel processing of instructions by high-power execution units caused the microprocessor peak power to increase. The method of the present invention attempts to reduce microprocessor peak power by ensuring that two high-power execution units are not executing simultaneously. While a first instruction is being executed by a first execution unit, a first signal is asserted. A second instruction is prevented from being dispatched to a second execution unit while the first signal is asserted. Thus, the second execution unit remains in an idle state while the first execution unit is executing the first instruction.

Abstract: A data processor for executing instructions using operand data stored in a main memory includes an instruction control unit having a first associative memory storing instructions read out from the main memory. The data processor also includes an instruction controller reading out an instruction from the first associative memory when the instruction is present in the first associative memory and reading an instruction from the main memory when the instruction is not present in the first associative memory. The controller also has as an output instruction to be executed. An instruction execution unit has a second associative memory storing operand data read out from the main memory. An instruction executioner executes the instruction by using operand data read out from the second associative memory when the operand data is present in the second associative memory and from the main memory when the operand data is not present in the second associative memory.