Abstract: According to one embodiment, a memory system includes a non-volatile semiconductor memory, a block management unit, and a transcription unit. The semiconductor memory includes a plurality of blocks to which data can be written in both the first mode and the second mode. The block management unit manages a block that stores therein no valid data as a free block. When the number of free blocks managed by the block management unit is smaller than or equal to a predetermined threshold value, the transcription unit selects one or more used blocks that stores therein valid data as transcription source blocks and transcribes valid data stored in the transcription source blocks to free blocks in the second mode.

Abstract: An approach to selecting statements for inlining in a COBOL program involving creating a PERFORM Graph (PG), determining whether the PG is a Directed Acyclic Graph (DAG), responsive to determining the PG is not a DAG, identifying a maximum sub-graph DAG corresponding to the PG, computing one or more infeasible paths associated with a Control Flow Graph (CFG), wherein the infeasible paths are induced by PERFORM range calls associated with a plurality of edges corresponding to the PG or the maximum sub-graph DAG, ordering the plurality of edges corresponding to the PG or the maximum sub-graph DAG in a list, selecting one or more edges, based on traversing the list of the plurality of edges and generating an indicator of the one or more selected edges.

Abstract: A single chip sequential processor comprising at least one ALU-Block, where said sequential processor is capable of maintaining its op-codes while processing data such as to overcome the necessity of requiring a new instruction in every clock cycle.

Abstract: This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations. In a fifth aspect of the present disclosure, an interface select circuit, FIGS. 41-49, provides for selectively using either the 5 signal interface of FIG. 41 or the 3 signal interface of FIG. 8.

Abstract: More robust testing of computer module responses to processing errors using a flexible, lightweight solution that does not alter the computer module. Through modification of processing pointers, a wide variety of processing errors and delays are injected into a computer module without modifying the computer module.

Abstract: A computation method includes: obtaining one or more first performance values of one or more instructions in a specific code for each of a plurality of first combinations of behavior result of a cache memory when a plurality of accesses to a memory area are executed; obtaining a second combination of behavior result of the cache memory when the plurality of accesses are executed based on an execution result of behavior simulation of the cache memory for a case where a processor executes a program including the specific code; and computing, by a computer, a third performance value when the processor executes the specific code based on one or more second performance values of the one or more instructions corresponding to the second combination among the one or more first performance values when the second combination is included in the plurality of first combinations.

Abstract: A processing device comprises a debug port controller to monitor operations of the processing device to determine whether the processing device is operating in a first mode or a second mode and to collect trace information comprising operating characteristics of the processing device. The processing device further comprises a display engine logic to process display data for output to a display device. In addition, the processing device comprises a display engine interface to provide, to a plurality of existing platform connectors, the display data from the display engine logic when the processing device is operating in the first primary mode and the trace information from the debug port controller when the processing device is operating in the second mode as determined by the debug port controller.

Abstract: Embodiments of the invention relate to tracking processor transactional read and write sets, thereby eliminating speculative mis-predictions. Both non-speculative read set and write set indications are maintained for a transaction. The indications are stored in cache. In addition, load and write queues of addresses are maintained. The load queue of addresses relates to speculative members of a read set and the write queue of addresses relates to speculating member of a write set. For a received read request, a transaction resolution process takes place, and a resolution is performed if an address match in the write queue is detected. Similarly, for a receive write request the transaction interference additionally checks the load queue and the non-speculative read set for the pending address.

Abstract: An electronic tracing process includes packing both stall (215) and reason (219) data into a single high priority timing information stream. An integrated circuit includes an electronic processor (110), and a tracing circuit (120) operable to pack both stall and events data into a single timing information stream. Other circuits, processes and systems are also disclosed.

Abstract: Embodiments of the present invention, which relate to the field of electronic technologies, provide a monitoring method, a monitoring apparatus, and an electronic device, which can accurately locate an error point in MPI information delivered by a system chip. The apparatus may include: an address filter, a read/write controller connected to the address filter, and a memory connected to the read/write controller, where the address filter is configured to acquire multiple pieces of MPI information, and obtain, by filtering the multiple pieces of MPI information, first MPI information corresponding to a first service that is preset; the read/write controller is configured to write, into the memory according to a time sequence of receiving the first MPI information, the first MPI information that is obtained by the address filter by filtering; and the memory is configured to store the first MPI information written by the read/write controller.

Abstract: A control program execution unit, when a callee control program is called, stores a return address in a stack and stores input data for the callee control program in a data storage unit. An execution error information management unit, when an execution error occurs, acquires execution error information that includes the return address stored in the stack, the input data stored in the data storage unit, and a program name that corresponds to the return address and is obtained by using mapping information that indicates the storing positions of a control program and the callee control program in a user program storage unit.

Abstract: According to embodiments of the present invention, machines, systems, methods and computer program products for controlling two or more remote sessions are provided. Two or more remote sessions are synchronized to control each session using a common interface. One or more executable commands are sent to each remote session at substantially the same time using the common interface to control operation of that remote session. Data generated by each remote session from executing the commands is received and analyzed to identify one or more differences in data generated by each remote session. The one or more identified differences in the data are displayed on the common interface. An indication may be provided regarding possible root causes of the differences in the data generated by each remote session. Each remote session includes a program debug session. A report comprising the one or more identified differences in the data may be generated.

Abstract: A method comprises identifying a number of branches (Nb) and a number of iterations (Ni) in a loop in an instruction stream, generating a number of forward branches until the number of forward branches equals Nb, generating a non-branch instruction in between the forward branch instruction, recording in a memory, instruction stream generated and a history of each branch, an associated target address of each branch, and whether the branch is a taken branch or a not taken branch, determining whether a loop iterator number (i) is less than Ni?1, generating a backward branch with a target address which is greater than or equal to the start address and is lesser than the current address responsive to determining that (i) is less than Ni, and recording in the memory, a branch instruction of the generated backward branch and the associated target address of the backward branch.

Abstract: Methods and systems of simulating the effects of an attack seeking fraudulently to modify target code that is interpretable by a processor are disclosed. Various implementations may include means and operations for searching for a set of sensitive instructions in the target code; generating an interpretable “simulation” code having instructions representing the result of said attack on the set of instructions; selecting memory registers that might be accessed during the interpretation of the simulation code; interpreting at least a portion of the simulation code; and storing at least one value of the registers during the interpretation in order to enable the effects of the attack to be analyzed.

Abstract: The present application relates to a flash memory controller and a method of operating thereof. A system bus interface is provided to interface with a system bus and a debug bus interface is provided to interface with a debug bus. A flash access control block is provided to perform storage I/O operations on a flash memory array. A debug control block is provided to monitor debug related information. The flash memory controller is configured to selectively operate in one or storage operating mode or debug operating mode. In the debug operating mode: the storage control block is configured to serve only read data access requests; and the debug control block is configured to store trace messages in an allocated part of the storage resources of the flash memory controller in response to trace events. The trace messages are generated on the basis of the monitored debug related information.

Abstract: A computing system includes: a volatile memory configured to: store a debug assert flag mask including bits; cores, coupled to the volatile memory, configured to: detect an error in at least one of the cores, set at least one of the bits corresponding to the cores with the error detected, collect debug information for each of the cores with the error detected, collect operating information for each of the cores without the error detected, generate assert dump information based on compiling the debug information; and a nonvolatile memory, coupled to at least one of the cores, configured to: store the assert dump information, the operating information, configured to by at least one of the cores.

Abstract: A stream of tuples is received to be processed by processing elements operating on one or more computer processors with each processing element having one or more stream operators. A breakpoint is identified for a stream operator that is configured to be triggered when time for processing of a tuple by the first stream operator is predicted to exceed a threshold time. A tuple is received at the stream operator having a set of attributes. A predicted time to process the tuple is determined based on the set of attributes. It is determined that the predicted time exceeds the threshold time. The breakpoint is triggered, in response to determining that the predicted time exceeds the threshold time, to pause processing of the tuple by the first stream operator.

Abstract: A method for translating instructions for a processor. The method includes accessing a plurality of guest instructions that comprise multiple guest branch instructions, and assembling the plurality of guest instructions into a guest instruction block. The guest instruction block is converted into a corresponding native conversion block. The native conversion block is stored into a native cache. A mapping of the guest instruction block to corresponding native conversion block is stored in a conversion look aside buffer. Upon a subsequent request for a guest instruction, the conversion look aside buffer is indexed to determine whether a hit occurred, wherein the mapping indicates whether the guest instruction has a corresponding converted native instruction in the native cache. The converted native instruction is forwarded for execution in response to the hit.

Abstract: Embodiments of the invention relate to tracking processor transactional read and write sets, thereby eliminating speculative mis-predictions. Both non-speculative read set and write set indications are maintained for a transaction. The indications are stored in cache. In addition, load and write queues of addresses are maintained. The load queue of addresses relates to speculative members of a read set and the write queue of addresses relates to speculating member of a write set. For a received read request, a transaction resolution process takes place, and a resolution is performed if an address match in the write queue is detected. Similarly, for a receive write request the transaction interference additionally checks the load queue and the non-speculative read set for the pending address.

Abstract: More robust testing of computer module responses to processing errors using a flexible, lightweight solution that does not alter the computer module. Through modification of processing pointers, a wide variety of processing errors and delays are injected into a computer module without modifying the computer module.

Abstract: Embodiments of an invention for a guest-physical address translation lookaside buffer are disclosed. In an embodiment, a processor includes an instruction decoder, a control register, and memory address translation hardware. The instruction decoder is to receive an instruction to transfer control of the processor to guest software to execute on a virtual machine. The virtual machine is to have a plurality of resources to be controlled by a virtual machine monitor. The virtual machine monitor is to execute on a host machine having a host-physical memory to be accessed using a plurality of host-physical addresses. The plurality of resources is to include a guest-physical memory. The guest software is to access the guest-physical memory using a plurality of guest-virtual addresses. The control register is to store a pointer to a plurality of virtual address page tables.

Abstract: The disclosure describes a novel method and apparatuses for allowing a controller to select and access different types of access ports in a device. The selecting and accessing of the access ports is achieved using only the dedicated TDI, TMS, TCK, and TDO signal terminals of the device. The selecting and accessing of device access ports can be achieved when a single device is connected to the controller, when multiple devices are placed in a daisy-chain arrangement and connected to the controller, or when multiple devices are placed in a addressable parallel arrangement and connected to the controller. Additional embodiments are also provided and described in the disclosure.

Abstract: A system for obtaining performance data for different performance events includes a first application monitoring performance of a second application executing on a computing system. The first application identifies the type of event to be measured with respect to the second application, issues a first system call identifying the type of event, receives an identifier corresponding to the event type, and causes the second application to begin execution. After the execution of the second application is completed, the first application issues a second system call including the identifier corresponding to the event type, and receives a value of a hardware counter corresponding to the event type from an operating system.

Abstract: An apparatus comprising: a lower-layer decoder configured to decode a data stream formatted according to a lower-layer protocol that interleaves portions of a first data stream and one or more additional data streams to produce separated data streams comprising the first data stream and separately the one or more additional data streams; and a higher-layer decoder configured to decode the first data stream formatted according to a higher-layer protocol to produce trace data, the higher-layer decoder comprising: synchronization logic configured to process the first data stream to detect a data pattern within the first data stream as a synchronization event; and decoding logic configured to use the synchronization event to synchronize decoding of the received first data stream to produce the trace data.

Abstract: A method for debugging firmware/software by generating trace data includes the following steps: running a debug module in a power-on stage in a test system, to record a load address and a branch instruction execution record set of a tested module into an area for temporary storage; accessing, by an analyzer, in an operating system stage in the area for temporary storage, the load address and the branch instruction execution record set and accessing a program debug symbol table, where the program debug symbol table is generated when source program code is compiled; and finding, by the analyzer, an original source file, a function name, and line numbers of executed codes from the program debug symbol table according to the load address and the branch instruction execution record set to generate an analysis report that includes a program execution path and a program code coverage.

Abstract: A processing device implementing tracking of deferred data packets in a debug trace architecture is disclosed. The processing device is to determine an order number corresponding to an order in which an instruction was executed relative to other executed instructions that correspond to an instruction type within a sequence of executed instructions, identify a first data packet corresponding to a first packet type and sequentially ordered, according to the order number, with respect to data packets of the first packet type within a data trace log, identify a second data packet corresponding to a second packet type and sequentially ordered, according to the order number, with respect to data packets of the second packet type within the data trace log, and map the identified first and second data packets to the instruction, wherein at least one of the first or second data packets was generated post-retirement of the instruction.

Abstract: A method and information processing system provide trace compression for trace messages. In response to a branch of a conditional branch instruction having not been taken or having been taken, a flag of a history buffer is set or cleared. A trace address message is generated in response to a conditional indirect branch instruction being taken, wherein the trace address message includes address information indicating the destination address of the taken branch, and an index value indicating a corresponding flag of the history buffer. In response to a return from interrupt or return from exception instruction, a predicted return address is compared to an actual return address. A trace address message is generated in response to the predicted and actual return addresses not matching. A trace address message is not generated in response to the predicted and actual return addresses matching.

Abstract: A method for analyzing race conditions between multiple threads of an application is disclosed. The method comprises accessing hazard records for an application under test. It further comprises creating a graph comprising a plurality of vertices and a plurality of edges using the hazard records, wherein each vertex of the graph comprises information about a code location of a hazard and wherein each edge of the graph comprises hazard information between one or more vertices. Additionally, it comprises assigning each edge with a weight, wherein the weight depends on a number and relative priority of hazards associated with a respective edge. Finally, it comprises traversing the graph to report an analysis record for each hazard represented in the graph.

Abstract: An information processing apparatus includes a rewriting unit and an execution unit. The rewriting unit rewrites a first instruction described at a trace point in a function defined in a program to a second instruction which gives instructions to execute a trace code, and stores the first instruction in a storage unit. The execution unit executes the trace code on the basis of the second instruction at the time of execution at the trace point in the function. If a third instruction which calls the function is included in the trace code, the execution unit replaces, at the time of executing the third instruction, the second instruction at the trace point in the function with the first instruction stored in the storage unit, and performs the function.

Abstract: A replay core ensures that references to objects are removed at the same relative times and in the same relative order within a program's execution during both record time and replay time. A register method of a Finalizer class is modified to cause the register method to pass, to a specified programmatic mechanism, an object that was passed to the register method; modifying a finalize method of a class of the object to (a) cause the object to invoke a first method of the programmatic mechanism when the finalize method is invoked by a virtual machine and (b) prevent a remainder of the finalize method from completing under specified conditions, thereby causing a call to the finalize method to remain undispatched. The first method, when invoked, (a) adds, to the object, a reference that temporarily prevents the object from being deleted and (b) records an identifier of the object.

Abstract: Comparisons of different versions of an application may be compared using a behavior model of the application. A behavior model may be derived from n-gram analysis of observations of the application in production. The behavior model may include sequences of inputs received by the application or functions performed by the application, where each sequence is an n-gram observed in tracer data. Each n-gram may be coupled with a resource consumption to give a behavior model with performance data. A regression analysis may apply a behavior model derived from a first version of an application to the performance observations of a new version to create an expected performance metric for the new version. A similarly calculated metric from a previous version may be compared to the metric from a new version to determine an improvement or degradation of performance.

Abstract: An integrated circuit (IC) chip is provided. The IC chip includes a signal output via which an outgoing signal is transmitted, and a signal input via which an incoming data signal is received. Also included on the IC ship is a pass circuit to couple the signal output to the signal input during testing of the IC chip. Furthermore, a delay circuit produces a first timing signal and a second timing signal during testing of the IC chip. The second timing signal is delayed from the first timing signal according to a test parameter. The first timing signal triggers transmission of a test signal via the signal output, and the second timing signal triggers sampling of the received test signal via the signal input.

Abstract: A multiplier unit that may be configured to concurrently perform multiple division and square operations is disclosed. The multiplier unit may include multiple stages. Each stage may be configured to perform a corresponding arithmetic operation. Control circuitry coupled to the multiplier unit may be configured to schedule in a given cycle of the plurality of cycles, a respective tasks of a plurality of tasks included in a first operation for execution on a respective stage of the multiple stages. The control circuitry may be further configured to schedule execution of each tasks of a second plurality of tasks included in a second operation during a respective cycle on an unused stage of the multiple stages.

Abstract: Techniques relate to fingerprint-initiated trace extraction. A determination is made of whether a fingerprint is present in software that is currently executing on a processor of a computer system. The fingerprint comprises a representation of a sequence of behavior that occurs in the processor while the software is executing. In response to determining that the fingerprint is not present in the software currently executing on the processor, monitoring continues for the software executing on the processor to determine whether the fingerprint is present. In response to determining that the fingerprint is present in the software executing on the processor, a trace is triggered of a code segment of the software corresponding to when the fingerprint is recognized. The trace is for a record of instructions of the code segment of the software.

Abstract: A stream of tuples is received to be processed by processing elements operating on one or more computer processors with each processing element having one or more stream operators. A breakpoint is identified for a stream operator that is configured to be triggered when time for processing of a tuple by the first stream operator is predicted to exceed a threshold time. A tuple is received at the stream operator having a set of attributes. A predicted time to process the tuple is determined based on the set of attributes. It is determined that the predicted time exceeds the threshold time. The breakpoint is triggered, in response to determining that the predicted time exceeds the threshold time, to pause processing of the tuple by the first stream operator.

Abstract: A method comprises identifying a number of branches (Nb) and a number of iterations (Ni) in a loop in an instruction stream, generating a number of forward branches until the number of forward branches equals Nb, generating a non-branch instruction in between the forward branch instruction, recording in a memory, instruction stream generated and a history of each branch, an associated target address of each branch, and whether the branch is a taken branch or a not taken branch, determining whether a loop iterator number (i) is less than Ni?1, generating a backward branch with a target address which is greater than or equal to the start address and is lesser than the current address responsive to determining that (i) is less than Ni, and recording in the memory, a branch instruction of the generated backward branch and the associated target address of the backward branch.

Abstract: Techniques of debugging a computing system are described herein. The techniques may include an apparatus having an all-in-one port. The all-in-one port may include a configuration channel and a sideband channel. The sideband channel is configured to default to a debug mode when the configuration channel is not communicatively coupled to an external device.

Abstract: According to one embodiment, a system comprises one or more counters; comparison logic; and one or more hardware processors communicatively coupled to the one or more counters and the comparison logic. The one or more hardware processors are configured to instantiate one or more virtual machines that are adapted to analyze received content, where the one or more virtual machines are configured to monitor a delay caused by one or more events conducted during processing of the content and identify the content as including malware if the delay exceed a first time period.

Abstract: Methods and apparatuses for generating a suppressed address trace are described. In some embodiments, a processor includes a trace generator having a trace suppressor that outputs a suppressed address trace for instructions executed by the processor. In some embodiments, a method to generate a suppressed address trace for a processor includes generating a suppressed address trace of executed instructions from a trace suppressor of a trace generator of the processor.

Abstract: A example method is described in which a programmable logic device: samples a first instance of a log data word comprising at least one hardware signal; compares the first instance of the log data word to a previous instance of the log data word; detects a change in the log data word when the first instance of the log data word is different from the previous instance of the log data word; and stores the first instance of the log data word in a storage location in an embedded block random access memory of the programmable logic device when the change in the log data word is detected.

Abstract: During a pipeline stall in a processor, until a next to complete instruction group completes, a monitoring unit receives, from a completion unit of a processor, a next to finish indicator indicating the finish of an oldest previously unfinished instruction from among a plurality of instructions of a next to complete instruction group. The monitoring unit receives, from functional units of the processor, finish reports including completion reasons for separate instructions. The monitoring unit determines at least one stall reason from among multiple stall reasons for the oldest instruction from a selection of completion reasons from a selection of finish reports aligned with the next to finish indicator from among the finish reports. Once the monitoring unit receives a complete indicator from the completion unit, indicating the completion of the next to complete instruction group, the monitoring unit stores each determined stall reason aligned with each next to finish indicator in memory.

Abstract: A microcontroller which operates in a low power consumption mode is provided. A microcontroller includes a CPU, a memory, and a peripheral circuit such as a timer circuit. A register in the peripheral circuit is provided in an interface with a bus line. A power gate for controlling supply control is provided. The microcontroller can operate not only in a normal operation mode where all circuits are active, but also in a low power consumption mode where some of the circuits are active. A volatile memory and nonvolatile memory are provided in a register, such as a register of the CPU. Data in the volatile memory is backed up in the nonvolatile memory before the power supply is stopped. In the case where the operation mode returns to the normal mode, when power supply is started again, data in the nonvolatile memory is written back into the volatile memory.

Abstract: Techniques for detecting and addressing performance issues related to a mobile application are provided. Examples of performance issues include a backend service (to which the mobile application is configured to transmit requests) becoming unavailable or overloaded, a third-party service that the mobile application relies on for data pertaining to the backend service becoming unavailable, and security vulnerabilities or code irregularities in the code of the mobile application. A fallback service that is separate from the backend service detects the performance issues and sends fallback data to the mobile application. The fallback data may cause the mobile application to operate in an offline mode, where the mobile application requests locally stored data instead of transmitting data requests to the backend service. The fallback data may reference page views that the mobile application downloads and displays instead of other page views that are based on data from the backend service.

Abstract: A display and an operating method thereof are provided. The display includes a display panel, a timing controller, and a plurality of source drivers. The source drivers are coupled to the timing controller and the display panel, and the source drivers are coupled to one another. The timing controller outputs a plurality of training packets to the source drivers. When the source drivers lock a clock of the timing controller according to the training packets, a lock signal is output to the timing controller. The timing controller outputs a plurality of color data packets and at least one latch signal to the source drivers based on the lock signal. The source drivers respectively output a plurality of pixel voltages to the display panel according to the latch signal. The training packets and the color data packets are serially transmitted to the source drivers.

Abstract: The invention relates to a computer-implemented method for updating an operating system (OS) without a memory reset. The method includes launching a Virtual Execution Environment (VEE) under a host OS of a computer system. The VEE can be a VM or a Container. Next, a snapshot of the VEE is generated, including snapshotting user process data, of any processes that run under the VEE. A new OS is loaded onto the computer system, and control is given to the new OS without performing the memory reset. It is ensured that the user process data that is part of the snapshot is unaffected by the loading of the new OS and that the user process data remains in its original location. The VEE is re-launched under the new OS. User process data is restored from the snapshot into a random access memory.

Abstract: Embodiments of the invention relate to transforming a program-event-recording event into a run-time instrumentation event. An aspect of the invention includes enabling run-time instrumentation for collecting instrumentation information of an instruction stream executing on a processor. Detecting is performed, by the processor, of a program-event-recording (PER) event, the PER event associated with the instruction stream executing on the processor. A PER event record is written to a collection buffer as a run-time instrumentation event based on detecting the PER event, the PER event record identifying the PER event.

Abstract: Embodiments relate to systems and methods for error containment in a system comprising detecting an error by processing an input signal by multiple processing units, and delaying at least one output signal of a processing unit to enable, in case an error has been detected, modifying at least one output signal of the processing unit that would cause propagation of the error through the system.

Abstract: A mechanism for tracking subclasses of and operations performed by generic objects in a computer system is disclosed. A method of the disclosure includes receiving, by a debugging tool executed from a processing device, an invocation from a code annotation in a function executed by the processing device, the invocation to initialize an object subclass tracking module of the debugging tool, requesting a stack trace of a call stack of the function, generating an identification (ID) using the requested stack trace, and storing the generated ID and the stack trace in a new entry in an object tracking table.

Abstract: A processor is described having a functional unit within an instruction execution pipeline. The functional unit having circuitry to determine whether substantive data from a larger source data size will fit within a smaller data size that the substantive data is to flow to.

Abstract: Register renaming circuitry for a processing apparatus configured to process a stream of instructions from an instruction set specifying registers from an architectural set of registers. The apparatus including a physical set of registers configured to store data values being processed by the processing apparatus. Register renaming circuitry is configured to receive a stream of operations from an instruction decoder and to map registers that are to be written to by the stream of operations to physical registers within the physical set of registers that are currently available. The register renaming circuitry comprises register release circuitry configured to release the physical registers that have been mapped to the registers when a first set of conditions have been met, and to release the physical registers that have been mapped to the additional registers when a second set of conditions have been met.