Abstract: A relational model may be used to encode primitives for each of a plurality of threads in a multi-core processor. The primitives may include tasks and parameters, such as buffers. The relationships may be linked to particular tasks. The tasks with the coding, which indicates the relationships, may then be used upon user selection to display a visualization of the functional relationships between tasks.

Abstract: A method and apparatus of a device that captures a stackshot of an executing process is described. In an exemplary embodiment, the device detects an interrupt of the process occurring during the execution of the process, where the process execution can be in a kernel space and user space, and the interrupt occurs during the user space. The device further determines whether to capture a stackshot during the interrupt using a penalty function. If the stackshot is to be captured, the device captures the stackshot and saves the stackshot.

Abstract: A system and method for request processing management that includes receiving requests for tasks from a plurality of sources; reviewing the requests by a review group comprising representatives from different functional areas; and identifying at least one functional area for each request for handling the associated request. The requests for tasks from the plurality of sources are received at a single entry point.

Abstract: A measurement sampling facility takes snapshots of the central processing unit (CPU) on which it is executing at specified sampling intervals to collect data relating to tasks executing on the CPU. The collected data is stored in a buffer, and at selected times, an interrupt is provided to remove data from the buffer to enable reuse thereof. The interrupt is not taken after each sample, but in sufficient time to remove the data and minimize data loss.

Abstract: An information processing apparatus includes a first preservation unit configured to preserve execution request information for information processing; an execution unit configured to execute one or more types of the information processing; an execution control unit configured to have the execution unit being capable of executing one of the types of the information processing execute the information processing of the execution request information preserved by the first preservation unit; and a second preservation unit configured to preserve a stop command of the execution unit. If the execution unit does not execute the information processing, the execution control unit checks the second preservation unit if the second preservation unit preserves the stop command to have the execution unit execute a stop procedure.

Abstract: A segmented subsystem, for use within an automated test platform, includes a first subsystem segment configured to execute one or more instructions within the first subsystem segment. A second subsystem segment is configured to execute one or more instructions within the second subsystem segment. The first subsystem segment includes: a first functionality, a second functionality, and a status polling engine. The status polling engine is configured to: determine a first status for the first functionality and a second status for the second functionality, and generate a consolidated status indicator for the first subsystem segment based, at least in part, upon the first status for the first functionality and the second status for the second functionality.

Abstract: Systems and methods herein provide for a compiler to create executable programs for a compound instruction based processor directly from flowcharts. In one embodiment, a system receives one or more flowchart diagram files that represent a computer program for a Compound CISC (CCISC) processor. The system identifies a flowchart symbol in the one or more flowchart diagram files, identifies a computing category for the flowchart symbol, and generates one or more CCISC instructions based on the computing category for execution by the CCISC processor. Further, the one or more CCISC instructions generated by the flowchart compiler direct the CCISC processor to access and operate on at least two data values in a multi-channel memory during the same clock cycle.

Abstract: A Reduced Instruction Set Computing (RISC) processor is capable of emulating operation of a floating-point register stack. The RISC processor may include a floating-point register file containing a plurality of floating-point registers, a decoding section for decoding operation instructions, and a floating-point operation section. The RISC processor may also include a control register for controlling status of floating-point registers, and for controlling the decoding section and the floating-point operation section, to thereby emulate a floating-point register stack using the floating-point register file. The decoding section may include a pointer register for maintaining a stack operation pointer, and for storing a value of the stack operation pointer.

Abstract: A method is provided for verification of a logic design for a processor execution unit which includes an instruction pipeline with one or more pipeline stages. The method includes: creating a design under test using at least a first and a second instance of the logic design; initializing the instruction pipeline using the first instance of the design under test with the same value in each instruction pipeline stage and the second instance with random values in its pipeline stages; selecting an instruction of the processor execution unit out of a plurality of instructions and simultaneously issuing the instruction to each instance of the design under test; providing a comparison between the outputs of the instruction pipeline executing the instruction for each instance; and if the instruction is verifiable by formal model checking, approving the correctness of the logic design if the comparison result is true.

Abstract: A trace unit for generating items of trace data indicative of processing activities of a processor executing a stream of instructions, the unit includes trace circuitry for monitoring a behaviour of the processor; storage circuitry for storing current trace control data for controlling the trace circuitry; a data store for storing at least some of the trace control data; the trace circuitry being configured to store the trace control data in the data store in response to detection of execution of the group of instructions, wherein the trace circuitry is responsive to detecting the at least one processor cancelling at least one group of the speculatively executed instructions to retrieve at least some of the trace control data stored in the data store for the group of instructions executed before the cancelled speculatively executed instructions and to store the retrieved trace control data in the storage circuitry.

Abstract: This invention describes an apparatus, computer architecture, method, operating system, compiler, and application program products for MPEs as well as virtualization in a symmetric MCP. The disclosure is applied to a generic microprocessor architecture with a set (e.g., one or more) of controlling elements (e.g., MPEs) and a set of groups of sub-processing elements (e.g., SPEs). Under this arrangement, MPEs and SPEs are organized in a way that a smaller number MPEs control the behavior of a group of SPEs. The apparatus enables virtualized control threads within MPEs to be assigned to different groups of SPEs for controlling the same. The apparatus further includes a MCP coupled to a power supply coupled with cores to provide a supply voltage to each core (or core group) and controlling-digital elements and multiple instances of sub-processing elements.

Abstract: A system and method for testing whether a computer processor is capable of executing a requested instruction set. The system includes a computer processor configured to receive an encoded conditional branch instruction in a form of machine code executable directly by the computer processor, and implement the encoded conditional branch instruction unconditionally, based on underlying hardware architecture of the computer processor. The Method for testing whether a computer processor is capable of executing a requested instruction set, the method including, receiving an encoded conditional branch instruction in a form of machine code executable directly by the computer processor, and implementing the encoded conditional branch instruction unconditionally, based on underlying hardware architecture of the computer processor.

Abstract: Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution model with interrupts can be maintained in a highly parallel scalable pipelined array processing containing multiple processing elements and distributed memories and register files. When an interrupt occurs, interface signals are provided to all PEs to support independent interrupt operations in each PE dependent upon the local PE instruction sequence prior to the interrupt. Processing/element exception interrupts are supported and low latency interrupt processing is also provided for embedded systems where real time signal processing is required. Further, a hierarchical interrupt structure is used allowing a generalized debug approach using debug interrupts and a dynamic debut monitor mechanism.

Abstract: In some embodiments, a method for improving reliability in a processor is provided. The method can include replicating input data for first and second lanes of a processor, the first and second lanes being located in a same cluster of the processor and the first and second lanes each generating a respective value associated with an instruction to be executed in the respective lane, and responsive to a determination that the generated values do not match, providing an indication that the generated values do not match.

Abstract: A sandbox architecture that isolates and identifies misbehaving plug-ins (intentional or unintentional) to prevent system interruptions and failure. Based on plug-in errors, the architecture automatically disables and blocks registration of the bad plug-in via a penalty point system. Publishers of bad plug-ins are controlled by disabling the bad plug-ins and registering the publisher in an unsafe list. Isolation can be provided in multiple levels, such as machine isolation, process isolation, secure accounts with limited access rights, and application domain isolation within processes using local security mechanisms. A combination of the multiple levels of isolation achieves a high level of security. Isolation provides separation from other plug-in executions and restriction to system resources such as file system and network IP.

Abstract: A method for online testing pipeline systems comprising a succession of stages separated by buffers each associated with an idle signal, or idle signal, and/or at least one status bit, comprising: detecting values of the idle signal and/or the corresponding status bits indicating the availability of a cycle or the abrupt interruption of the flow of operations in a pipeline, and indicating that a valid operation, executed by a stage in the pipeline, is followed by an unused cycle; maintaining the state of the buffer in order to allow said valid operation to be re-executed during the unused cycle indicated by said idle signal; re-executing, during the unused cycle, the valid operation, in order to obtain at least a first version and a second version of said valid operation; memorizing, at the output of the pipeline, the results that correspond to the first version of said repeated or re-executed operation, in order to compare with the results of said second version of the same repeated or re-executed operation;

Abstract: The invention provides, in one aspect, a digital data processor-based test data generator, that includes a digital data processing system with one or more digital data processors that are coupled for communications. A scenario creator executes on the digital data processing system and accepts, for each of one or more entities (“domains”), a plurality of parameters, including a hierarchical relationship between that entity and one or more other entities, a priority-of-test-data-creation relationship between that entity and one or more entities, and one or more attributes of that entity. The scenario creator generates a parameter set that defines a test data set specifying the aforesaid entities, relationships and attributes. The test generator further includes an engine that enumerates values for the entities and their attributes in an order determined by the aforesaid relationships.

Abstract: A program processing device comprises a CPU for carrying out predetermined processing according to a program; an internal memory storing the program and data generated by the CPU by carrying out the program, and a data acquiring circuit connected to an external program processing device, for acquiring the program from the external program processing device to write into the internal memory, wherein the CPU, the internal memory, a debug processing circuit, and the data acquiring circuit are integrally mounted on the same semiconductor substrate.

Abstract: To provide a multi-processor system that efficiently debugs operations of one processor and operations of another processor. The multiprocessor system has a first processor and a second processor that executes processing by receiving notification from the first processor. The first processor: sequentially specifies instructions to be executed from an instruction queue; sends a notification based on a processing request instruction to the second processor when an instruction that is specified is the processing request instruction; executes the instruction that is specified when the instruction that is specified is not the processing request instruction; and determines whether or not a debug mode is set.

Abstract: In one embodiment, a processor comprises a programmable map and a circuit. The programmable map is configured to store data that identifies at least one instruction for which an architectural modification of an instruction set architecture implemented by the processor has been defined, wherein the processor does not implement the modification. The circuitry is configured to detect the instruction or its memory operands and cause a transition to Known Good Code (KGC), wherein the KGC is protected from unauthorized modification and is provided from an authenticated entity. The KGC comprises code that, when executed, emulates the modification. In another embodiment, an integrated circuit comprises at least one processor core; at least one other circuit; and a KGC source configured to supply KGC to the processor core for execution. The KGC comprises interface code for the other circuit whereby an application executing on the processor core interfaces to the other circuit through the KGC.

Abstract: A multi-core processor system includes a multi-core processor that has plural core groups; and a storage device that stores a constraint on execution time for each application. A first identified core of the multi-core processor is configured to identify a constraint on execution time of a given application that is among the applications and for which an invocation instruction is received; determine whether the identified constraint meets a performance drop condition; assign the given application to a predetermined core of the multi-core processor, upon determining that the identified constraint meets the performance drop condition; and notify a second identified core of a core group among the core groups, of an assignment instruction for the given application, upon determining that the identified constraint does not meet the performance drop condition.

Abstract: A system and method is provided for performing deterministic processing on a non-deterministic computer system. In one example, the system forces execution of one or more computer instructions to execute within a constant execution time. A deterministic engine, if necessary, waits a variable amount of time to ensure that the execution of the computer instructions is performed over the constant execution time. Because the execution time is constant, the execution is deterministic and therefore may be used in applications requiring deterministic behavior. For example, such a deterministic engine may be used in automated test equipment (ATE) applications.

Abstract: A data processing apparatus for performing data processing operations in response to execution of program instructions and debug circuitry for performing operations. The data processing apparatus includes a data store for storing a current debug exception mask value. The data processing circuitry is configured to set the mask value to a first value in the data store in response to executing critical code and on termination of execution of the critical code to reset the mask value to not store the first value. The data processing circuitry is configured, in response to receipt of a control signal indicating a debug exception is to be taken, to allow the exception to be taken if the mask value is not set to the first value and not to allow said exception to be taken if the mask value is set to the first value.

Abstract: A bus monitoring and debugging system operating independently without impacting the normal operation of the CPU and without adding any overhead to the application being monitored. Users are alerted to timing problems as they occur, and bus statistics that are relevant to providing insight to system operation are automatically captured. Logging of relevant events may be enabled or disabled when a sliding time window expires, or alternatively by external trigger events.

Abstract: A data processing system includes a plurality of data processors, debug logic, and linking logic. The debug logic is coupled to each data processor of the plurality of data processors, and is for providing an instruction for exiting debug mode to the plurality of data processors. The linking logic is coupled to the debug logic and to each of the plurality of data processors. The linking logic is for linking selected ones of the plurality of data processors with each other and to the debug logic. The debug logic provides the instruction for exiting the debug mode when the selected ones of the plurality of data processors are linked in parallel by the linking logic.

Abstract: Tracing command execution in a data processing system having a host processor and a co-processor. The host processor maintains a record of a plurality of commands for the co-processor, storing each of the plurality of commands is stored in a command queue. Hardware trace logic is provided to store one or more events based, at least in part, on transfer of the plurality of commands to a small memory. Software is executed to store the one or more events to a main memory, wherein the one or more events are aggregated into a single memory trace within the main memory.

Abstract: A method for performing trace based measurement for a plurality of CPUs in parallel includes receiving a signal to perform a CPU parallel trace mode and enabling a parallel trace mode multiplexer to output all trace data, representing all data writes to the local memory, to a single observation unit. In one embodiment, the single observation unit is a processor observation block (POB), and in another embodiment, a bus observation block (BOB). If the single observation unit is a BOB, then the parallel trace mode multiplexer first routes the local memory data trace through a BOB adaptation layer to convert the CPU trace output data to data which is understood by the BOB.

Abstract: A method, computer program product, and device are provided for detecting and identifying priority inversion. A higher priority thread and a lower priority thread are received. A debugging application for debugging is executed. The lower priority thread requests and holds a resource. A break point is hit by the lower priority thread. The lower priority thread is preempted by the higher priority thread, and debugging stops until the higher priority thread completes. The higher priority thread requests the resource being held by the lower priority thread. It is determined whether priority inversion occurs.

Abstract: Systems and methods for detecting resource leaks in a program using static analysis are disclosed. Dynamically adjustable sets of must-access paths can be employed for aliasing purposes to track resources intra- and inter-procedurally through a program. Actionable reports are also disclosed, in which resource leaks are prioritized, filtered and clustered to improve utility.

Abstract: A processor link that couples a first processor and a second processor is selected for validation and a plurality of communication parameter settings associated with the first and the second processors is identified. The first and the second processors are successively configured with each of the communication parameter settings. One or more test data pattern(s) are provided from the first processor to the second processor in accordance with the communication parameter setting. Performance measurements associated with the selected processor link and with the communication parameter setting are determined based, at least in part, on the test data pattern as received at the second processor. One of the communication parameter settings that is associated with the highest performance measurements is selected. The selected communication parameter setting is applied to the first and the second processors for subsequent communication between the first and the second processors via the processor link.

Abstract: A data processing apparatus is provided comprising prediction circuitry for predicting a response of the data processing circuitry at at least one given execution point to execution of a program instruction; tracing circuitry for tracing operation of the data processing apparatus for outputting a prediction indicator indicating whether or not the predicted response is correct; a data store configured to store information relating to the predicted response of said data processing circuitry at the given execution point for use by at least one of said prediction logic and said tracing circuitry a later execution point; and a history buffer configured to store historical information with regard to one or more entries of the data store at a corresponding execution point previous to the given execution point to enable restoration of said data store to a state corresponding to said previous execution point.

Abstract: A method and system are disclosed for sampling instructions executing on a computer processor. A computer processor determines a number of times a specified event has occurred within a specified temporal window. The computer processor determines to mark an instruction to be executed for monitoring based on the number of times the specified event has occurred within the temporal window, and in response, the computer processor marks the instruction.

Abstract: State machine engines are disclosed, including those having an instruction insertion register. One such instruction insertion register may provide an initialization instruction, such as to prepare a state machine engine for data analysis. An instruction insertion register may also provide an instruction in an attempt to resolve an error that occurs during operation of a state machine engine. An instruction insertion register may also be used to debug a state machine engine, such as after the state machine experiences a fatal error.

Abstract: A post-silicon testing apparatus, method, and computer program product provide for runtime coverage measurement methodology to measure the architectural events in hardware. Measurement of all architectural events discernable from the instructions and architectural state changes are tracked and recorded. A mechanism to ensure capturing of maskable events is also provided. A feedback driven test-generation approach is enabled by the runtime coverage measurement. The runtime coverage measurement system presents a live view of the comprehensive architectural event coverage to the user/tester. The methodology can be implemented on an operating system environment and also as a standalone/bare-metal tool.

Abstract: An instruction for parsing a buffer to be utilized within a data processing system including: an operation code field, the operation code field identifies the instruction; a control field, the control field controls operation of the instruction; and one or more general registers, wherein a first general register stores an argument address, a second general register stores a function code, a third general register stores length of an argument-character buffer, and the fourth of which contains the address of the function-code data structure.

Abstract: A method, system and program product for executing a multi-function instruction in an emulated computer system by specifying, via the multi-function instruction, either a capability query or execution of a selected function of one or more optional functions, wherein the selected function is an installed optional function, wherein the capability query determines which optional functions of the one or more optional functions are installed on the computer system.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for selecting native code instructions. One of the methods includes receiving an initial machine language instruction for execution by a processor in a first execution mode; determining that a portion of the initial machine language instruction, when executed by the processor in a second execution mode, satisfies one or more risk criteria; generating one or more alternative machine language instructions to replace the initial machine language instruction for execution by the processor in the first execution mode, wherein the one or more alternative machine language instructions, when executed by the processor in the second execution mode, mitigate the one or more risk criteria; and providing the one or more alternative machine language instructions.

Abstract: A cross-logical entity group is created that includes one or more accelerators to be shared by a plurality of logical entities. Instantiated on the accelerators are functions that are common across multiple logical entities. The functions to be instantiated are determined, for instance, dynamically during run-time.

Abstract: A microprogrammable electronic device has a first code memory storing instructions, and is configured to execute each instruction in the first code memory at a respective instruction cycle. The system comprises binary code generating means, and a tracing device. The binary code generating means form part of the device, and are configured to generate and output on a single pin of the device binary codes, each of which indicates a corresponding execution-related event, is generated and outputted at a corresponding instruction cycle, and has N bits, where N is an integer >=2. The tracing device is coupled with the single pin to receive the binary codes, and has a second code memory in which the instructions are stored. The tracing device is configured to trace instructions executed by the device, on the basis of the received binary codes and of the instructions stored in the second code memory.

Abstract: A debugging mechanism receives arithmetic operation data inputs for causing an arithmetic unit to perform an arithmetic operation, and a control signal used for the arithmetic operation. The debugging mechanism includes a debug control unit which includes (1) a counter that performs a counting operation cyclically according to the processor clock operation, and (2) an OR circuit that receives the control signal and a counter signal that is output when the counter value becomes a specific value, and outputs an output signal generated by performing a logical OR operation of the control signal and the counter signal. The debugging mechanism also includes a debug storage unit which stores the arithmetic operation data, the counter value, and the control signal when the output of the OR circuit is valid.

Abstract: A disassembler receives instructions and disassembles them into a plurality of separate opcodes. The disassembler creates a table identifying boundaries between each opcode. Each opcode is written to memory in an opcode-by-opcode manner by atomically writing standard blocks of memory. Debug break point opcodes are appended to opcode to create a full block of memory when needed. The block of memory may be thirty-two or sixty-four bits long, for example. Long opcodes may overlap two or more memory blocks. Debug break point opcodes may be appended to a second portion of the long opcode to create a full block of memory. A stream fault interceptor identifies when a requested data page is not available and retrieving the data page.

Abstract: A microprocessor is provided with a reset logic flag and corresponding reset microcode that selectively enables the reset microcode to set up and enable debug logic before the microprocessor subsequently fetches and executes user instructions. When the reset logic flag is set to a debug mode, the reset microcode configures and enables the microprocessor's debug logic before the microprocessor subsequently fetches and executes user instructions. When the reset logic flag is set to a normal mode, the reset microcode refrains from configuring and enabling the microprocessor's debug logic. The reset logic flag is indicated by an alterable fuse or a debugger-programmable scan register. Debug configuration initialization values are also provided by several alternative structures, including the reset microcode itself, alterable fuses, and debugger-programmable scan registers. Corresponding methods are also provided for configuring the debug logic of a microprocessor.

Abstract: During a pipeline stall in an out of order processor, until a next to complete instruction group completes, a monitoring unit receives, from a completion unit of a processor, a next to finish indicator indicating the finish of an oldest previously unfinished instruction from among a plurality of instructions of a next to complete instruction group. The monitoring unit receives, from a plurality of functional units of the processor, a plurality of finish reports including completion reasons for a plurality of separate instructions. The monitoring unit determines at least one stall reason from among multiple stall reasons for the oldest instruction from a selection of completion reasons from a selection of finish reports aligned with the next to finish indicator from among the plurality of finish reports.

Abstract: There is described a method for monitoring a cyclic user program which is executed on an automation device by means of a programming device connected to communicate with the automation device, with a monitoring task being sent from the programming device to the automation device and the monitoring task containing command numbers of the commands to be monitored as well as the associated variables. With the method rarely run branches of the user program can also be easily observed by an execution of a command, by the data associated with the variables with corresponding command number and a first counter value, which assigns the data directly or indirectly to a cycle of the user program, being stored by the automation device in a recording buffer, by the old recording of the associated data including the first counter value being overwritten on renewed execution of the command and by the recording buffer being able to be output at the request of the programming device by the automation device.

Abstract: A data processing apparatus and method of data processing are provided. The data processing apparatus comprises execution circuitry configured to execute a sequence of program instructions. Checkpoint circuitry is configured to identify an instance of a predetermined type of instruction in the sequence of program instructions and to store checkpoint information associated with that instance. The checkpoint information identifies a state of the data processing apparatus prior to execution of that instance of the predetermined type of instruction, wherein the predetermined type of instruction has an expected long completion latency.

Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing Real Time Instruction Tracing compression of RET instructions For example, in one embodiment, such means may include an integrated circuit having means for initiating instruction tracing for instructions of a traced application, mode, or code region, as the instructions are executed by the integrated circuit; means for generating a plurality of packets describing the instruction tracing; and means for compressing a multi-bit RET instruction (RETurn instruction) to a single bit RET instruction.

Abstract: One embodiment of the present invention provides a method for supporting the development of a parallel/distributed application, wherein the development process comprises a design phase, an implementation phase and a test phase. A script language can be provided in the design phase for representing elements of a connectivity graph and the connectivity between them. In the implementation phase, modules can be provided for implementing functionality of the application, executors can be provided for defining a type of execution for the modules, and process-instances can be provided for distributing the application over several computing devices. In the test phase, abstraction levels can be provided for monitoring and testing the application.

Abstract: Disclosed herein is a system and method for executing a series of instructions on a circuit. The system comprises an encoder that receives event data corresponding to the executed instructions. The encoder groups the event data into one or more groups and outputs the highest priority event for each such group.

Abstract: A method for controlling a control station (H1) includes the steps of performing wireless connection processing (204) with a terminal station (D1) and when a wireless connection is established, sending, to the wirelessly-connected terminal station (D1), a capture request signal (205) for causing the terminal station to capture a control signal (202) sent by another station (H2) and to return (207) information regarding the captured control signal.

Abstract: A method and system are disclosed for executing a machine instruction in a central processing unit. The method comprise the steps of obtaining a perform floating-point operation instruction; obtaining a test bit; and determining a value of the test bit. If the test bit has a first value, (a) a specified floating-point operation function is performed, and (b) a condition code is set to a value determined by said specified function. If the test bit has a second value, (c) a check is made to determine if said specified function is valid and installed on the machine, (d) if said specified function is valid and installed on the machine, the condition code is set to one code value, and (e) if said specified function is either not valid or not installed on the machine, the condition code is set to a second code value.