Abstract: A channel-less system and method are provided for multithreaded communications with a direct memory access (DMA) controller. The method accepts a plurality of DMA command messages directed to a fixed port address. The DMA command messages are arranged in a first-in first-out (FIFO) queue, in the order in which they are received. The DMA command messages are supplied to a DMA controller from the FIFO queue, and in response to the DMA command message, data transfer operation are managed by the DMA controller. Following the completion of each data transfer operation, a transfer complete message indicating completion is sent. In one aspect, DMA command messages are arranged in a plurality of parallel FIFO queues, and CD sets are stored in a plurality of context memories, where each context memory is associated with a corresponding FIFO queue.

Abstract: A method and device for monitoring functions of a computer system having at least two execution units, a switchover unit being provided, and switchover operations being carried out between at least two operating modes, and a comparison unit being provided, a first operating mode corresponding to a comparison mode and a second operating mode corresponding to a performance mode, and a first function being monitored by a second function, the second function being executed in the comparison mode on at least two execution units, and each of these two second functions, which are executed on at least two execution units, monitoring the same first function.

Abstract: Heterogeneous processors can cooperate for distributed processing tasks in a multiprocessor computing system. Each processor is operable in a “compatible” mode, in which all processors within a family accept the same baseline command set and produce identical results upon executing any command in the baseline command set. The processors also have a “native” mode of operation in which the command set and/or results may differ in at least some respects from the baseline command set and results. Heterogeneous processors with a compatible mode defined by reference to the same baseline can be used cooperatively for distributed processing by configuring each processor to operate in the compatible mode.

Abstract: A system, apparatus and method for multithread handling on a multithread processing device are described herein. Embodiments of the present invention provide a multithread processing device for multithread handling including a plurality of registers operatively coupled to an instruction dispatch block, including thread-control registers for selectively disabling threads. In various embodiments, the multithread processing device may include a thread-operation register for selectively providing a lock to a first thread to prevent a second thread from disabling the first thread while the first thread has the lock. In still further embodiments, the multithread processing device may be configured to atomically disable and release a lock held by a thread. Other embodiments may be described and claimed.

Abstract: The invention resides in a flexible data pipeline structure for accommodating software computational instructions for varying application programs and having a programmable embedded processor with internal pipeline stages the order and length of which varies as fast as every clock cycle based on the instruction sequence in an application program preloaded into the processor, and wherein the processor includes a data switch matrix selectively and flexibly interconnecting pluralities of mathematical execution units and memory units in response to said instructions, and wherein the execution units are configurable to perform operations at different precisions of multi-bit arithmetic and logic operations and in a multi-level hierarchical architecture structure.

Abstract: A method and apparatus for operating a memory mapped register file. The method includes: receiving a source index input having a length of T?1 bits, the source index input identifying one of a plurality of unbanked registers; receiving a processor mode input to identify one of P processor modes, where P is greater than two; generating an encoded address having a length of T bits based on the source index input and the processor mode input; and identifying one of the plurality of unbanked registers associated with one of the P processor modes using the encoded address.

Abstract: A processor for performing floating-point operations includes an array of processing elements arranged to enable a floating-point operation. Each processing element includes an arithmetic logic unit to receive two input values and perform integer arithmetic on the received input values. The processing elements in the array are connected together in groups of two or more processing elements to enable floating-point operation.

Abstract: A computer implemented method for managing an execution mode for a parallel processor is provided. A monitor identifies a first efficiency rate for a first contested resource of the parallel processor operating in a first operating mode. Responsive to identifying the first efficiency rate for the first contested resource, the monitor identifies whether the first efficiency rate for the contested resource of the parallel processor operating in the first operating mode exceeds a threshold. Responsive to identifying that the efficiency rate for the contested resource exceeds the threshold, an operation of the parallel processor is changed to a second operating mode.

Abstract: A computer. A processor pipeline alternately executes instructions coded for first and second different computer architectures or coded to implement first and second different processing conventions. A memory stores instructions for execution by the processor pipeline, the memory being divided into pages for management by a virtual memory manager, a single address space of the memory having first and second pages. A memory unit fetches instructions from the memory for execution by the pipeline, and fetches stored indicator elements associated with respective memory pages of the single address space from which the instructions are to be fetched. Each indicator element is designed to store an indication of which of two different computer architectures and/or execution conventions under which instruction data of the associated page are to be executed by the processor pipeline.

Abstract: Mechanisms are provided for processing an instruction in a processor of a data processing system. The mechanisms operate to receive, in a processor of the data processing system, an instruction, the instruction including power/performance tradeoff information associated with the instruction. The mechanisms further operate to determine power/performance tradeoff priorities or criteria, specifying whether power conservation or performance is prioritized with regard to execution of the instruction, based on the power/performance tradeoff information. Moreover, the mechanisms process the instruction in accordance with the power/performance tradeoff priorities or criteria identified based on the power/performance tradeoff information of the instruction.

Abstract: Embodiments include a device and a method. In an embodiment, a method applies a first resource management strategy to a first resource associated with a first processor and executes an instruction block in a first processor. The method also applies a second resource management strategy to a second resource of a similar type as the first resource and executes the instruction block in a second processor. The method further selects a resource management strategy likely to provide a substantially optimum execution of the instruction group from the first resource management strategy and the second resource management strategy.

Abstract: There is a need to provide a microcomputer capable of eliminating an external terminal for endian selection. Flash memory includes a user boot area for storing a program executed in user boot mode and corresponding endian information and a user area for storing a program executed in user mode and corresponding endian information. A data transfer circuit reads endian information stored in the user boot area or the user area in accordance with operation mode and supplies the endian information to a CPU before reset release of the CPU. Accordingly, an external terminal for endian selection can be eliminated.

Abstract: The data processing apparatus has processing logic for performing data processing operations and a register bank for storing data associated with the processing logic. The register bank has at least one register group, each register group having a plurality of register sets. The processing logic has an operating state associated with each register group defining how that register group is used, a first operating state being a state in which each register set in the register group is used to support an independent execution thread of the processing logic, and a second operating state being a state in which the register sets of the register group are collectively used to support a single execution thread of the processing logic. Control logic is provided to control how the register sets of each register group are used dependent on the operating state associated with that register group.

Abstract: A system, apparatus and method for handling switching among threads within a multithread processor are described herein. Embodiments of the present invention provide a method for multithread handling that includes fetching and issuing one or more instructions, corresponding to a first instruction execution thread, to an execution block for execution during a cycle count associated with the first instruction execution thread and when the instruction execution thread is in an active mode. The method further includes switching a second instruction execution thread to the active mode when the cycle count corresponding to the first instruction execution thread is complete, and fetching and issuing one or more instructions, corresponding to the second instruction execution thread, to the execution block for execution during a cycle count associated with the second instruction execution thread.

Abstract: A reconfigurable array is provided. The reconfigurable array includes a Very Long Instruction Word (VLIW) mode and a Coarse-Grained Array (CGA) mode. When the VLIW mode is converted to the CGA mode, instead of sharing a central register file between the VLIW mode and the CGA mode, live data to be used in the CGA mode is copied from the central register file to local register files.

Abstract: A central processing unit (CPU) adapted for use in a computing system, such as a personal computer or other processing apparatus. The CPU is implemented to perform hyper-threading (HT), and further enables switching between HT-enabled and HT-disabled modes on the fly (without rebooting the apparatus) based on, for example, performance measurements or entries into a local library.

Abstract: Various technologies and techniques are disclosed for transforming a sequential loop into a parallel loop for use with a transactional memory system. Open ended and/or closed ended sequential loops can be transformed to parallel loops. For example, a section of code containing an original sequential loop is analyzed to determine a fixed number of iterations for the original sequential loop. The original sequential loop is transformed into a parallel loop that can generate transactions in an amount up to the fixed number of iterations. As another example, an open ended sequential loop can be transformed into a parallel loop that generates a separate transaction containing a respective work item for each iteration of a speculation pipeline. The parallel loop is then executed using the transactional memory system, with at least some of the separate transactions being executed on different threads.

Abstract: This invention provides with a semiconductor integrated circuit, comprising a register map that makes correspondence between a register to which a CPU accesses and an address which specifies the register, wherein the register map includes a plurality of register maps in which assignments of address bits are rearranged in correspondence with each of a plurality of modes, and wherein any of the register maps is selected from the plurality of register maps according to the respective modes.

Abstract: Memory address space is divided into domains and instruction access control circuitry is used to detect when the memory address from which an instruction to be executed is fetched has crossed a domain boundary and changed and in such cases to conduct a check to ensure that the instruction within the new domain is a permitted instruction of a permitted form. The permitted instruction can be arranged to be a no operation instruction other than in respect of the instruction access control circuitry, in order to assist backward compatibility.

Abstract: A processing system features a first processing core to operate in a first node, a second processing core to operate in a second node, and random access memory (RAM) responsive to the first and second processing cores. The processing system also features control logic to perform operations such as (a) automatically updating a resident set size (RSS) counter to correspond to the RSS for the thread on the first node in response to allocation of a page frame for a thread in the first node, and (b) using the RSS counter to predict migration overhead when determining whether the thread should be migrated from the first processing core to the second processing core. Other embodiments are described and claimed.

Abstract: A processor in a digital system executes instructions in an instruction execution pipeline. The processor detects a pipeline protection directive while executing instructions and sets a pipeline protection mode in accordance with the directive. The processor then continues to fetch and execute instructions in an unprotected manner if the pipeline protection mode is off and continues to fetch and execute instruction in a protected manner if the pipeline protection mode is on.

Abstract: An apparatus comprises register means for storing a return context upon initiation of a supervisor call instruction and restoring means to restore a privilege level and status register upon execution of a supervisor return instruction. The supervisor call instruction can be called from all contexts.

Abstract: A processor 4 is provided with reset circuitry 48 which generates a reset signal to reset a plurality of state parameters. Partial reset circuitry 50 is additionally provided to reset a proper subset of this plurality of state parameters. The reset circuitry triggers a redirection of program flow. The partial reset circuitry permits a continuation of program flow. The partial reset circuitry may be used to place processors into a known state with a low latency before switching from a split mode of operation into a locked mode of operation.

Abstract: Processor resource management devices and methods are disclosed. In some implementations, a device includes a processor, a hardware resource, and a resource manager operable to compare a first execution of one or more instructions pursuant to an optimistic resource management policy and a second execution of one or more instructions pursuant to a pessimistic resource management policy, the optimistic resource management policy assuming that less than an optimistic level of at least one error will occur during the first execution, and the pessimistic resource management policy assuming that greater than a pessimistic level of the at least one error will occur during the second execution. Based at least partially on the comparison, the resource manager selects a resource management policy from between the optimistic and pessimistic resource management policies, and associates the selected resource management policy with the one or more instructions.

Abstract: A processor device having a reservation station (RS) is concerned. In case the processor device has plural RS, the RS is associated with an arithmetic pipeline, and two RS make a pair. When one RS of the pair cannot dispatch an instruction to an associated arithmetic pipeline, the other RS dispatches the instruction to that arithmetic pipeline, or delivers its held instruction to the one RS. In case one RS is equipped, plural entries in the RS are divided into groups, and by dynamically changing this grouping according to the dispatch frequency of the instruction to the arithmetic pipelines or the held state of the instructions, the arithmetic pipelines are efficiently utilized. Incidentally, depending on the grouping of the plural entries in the RS, a configuration as if the plural RS were allocated to each arithmetic pipeline may be realized.

Abstract: A computing device has a hardware device employed to provide a hardware service to the computing device and a plurality of virtual machines including a host virtual machine (VM-H) to which the hardware device is assigned, and a client virtual machine (VM-C) that can consume the hardware service by way of the VM-H. The VM-C includes an emulating stack and an enlightened stack. The emulating stack interfaces an application requesting the hardware service with a trap in a virtualization layer of the computing device which re-directs the request to the VM-H. The enlightened stack interfaces the application with the VM-H and bypasses the virtualization layer. The emulating stack includes a shunt driver that shunts to the enlightened stack each request from the application directed to the emulating stack.

Abstract: A hardware wake-and-go mechanism is provided for a data processing system. The wake-and-go mechanism looks ahead in the instruction stream of a thread for programming idioms that indicates that the thread is waiting for an event. The wake-and-go mechanism updates a wake-and-go array with a target address associated with the event for each recognized programming idiom. When the thread reaches a programming idiom, the thread goes to sleep until the event occurs. The wake-and-go array may be a content addressable memory (CAM). When a transaction appears on the symmetric multiprocessing (SMP) fabric that modifies the value at a target address in the CAM, the CAM returns a list of storage addresses at which the target address is stored. The wake-and-go mechanism associates these storage addresses with the threads waiting for an even at the target addresses, and may wake the one or more threads waiting for the event.

Abstract: A system and method for enhancing performance of a computer which includes a computer system including a data storage device. The computer system includes a program stored in the data storage device and steps of the program are executed by a processer. The processor processes instructions from the program. A wait state in the processor waits for receiving specified data. A thread in the processor has a pause state wherein the processor waits for specified data. A pin in the processor initiates a return to an active state from the pause state for the thread. A logic circuit is external to the processor, and the logic circuit is configured to detect a specified condition. The pin initiates a return to the active state of the thread when the specified condition is detected using the logic circuit.

Abstract: A resource-constrained device comprises a processor configured to execute multiple instruction streams comprising multiple instructions having an opcode and zero or more operands. Each of the multiple instruction streams is associated with one of multiple instruction execution modes having an instruction set comprising multiple instruction implementations. At least one of the multiple instruction implementations is configured to change the processor from a first instruction execution mode to a second instruction execution mode. The processor comprises an instruction fetcher configured to fetch an instruction from one of the multiple instruction streams based at least in part upon a current instruction execution mode.

Abstract: A resource-constrained device comprises a processor configured to execute multiple instruction streams comprising multiple instructions having an opcode and zero or more operands. Each of the multiple instruction streams is associated with one of multiple instruction execution modes having an instruction set comprising multiple instruction implementations. At least one of the multiple instruction implementations is configured to change the processor from a first instruction execution mode to a second instruction execution mode. The processor comprises an instruction fetcher configured to fetch an instruction from one of the multiple instruction streams based at least in part upon a current instruction execution mode.

Abstract: Allocation of resources in a heterogeneous computing environment is facilitated. A resource manager of the heterogeneous computing environment obtains information that describes which nodes of the heterogeneous computing environment are capable of supporting additional operating systems and platforms over and above their native operating systems and platforms. This information is then used by the resource manager in allocating resources to satisfy a particular job.

Abstract: A processor having multiple distinct instruction sets is disclosed where one set, a default set, is always available for execution while a second set is only available once a valid control code is externally supplied to the processor to effectively “unlock” and enable the second set. Once the second set is so unlocked, then the instructions in both sets are available for subsequent execution by the processor to provide enhanced functionality only available through use of the second set, such as accessing on-line services and content information. Multiple unlockable instruction sets can also be similarly provided, each being separately unlocked and enabled through entry of an corresponding externally supplied control code.

Abstract: A configurable execution unit comprises operators capable of being dynamically configured by an instruction at the level of processing multi-bit operand values. The unit comprises one or more dynamically configurable operator modules, the or each module being connectable to receive input operands indicated in an instruction, and a programmable lookup table connectable to receive dynamic configuration information determined from an opcode portion of the instruction and capable of generating operator configuration settings defining an aspect of the function or behavior of a configurable operator module, responsive to the dynamic configuration information in the instruction.

Abstract: An apparatus and method is described herein for avoiding inefficient core hopping and providing hardware assisted power state selection. Future idle-activity of cores is predicted. If the residency of activity patterns for efficient core hop scenarios is predicted to be large enough, a core is determined to be efficient and allowed. However, if efficient activity patterns are not predicted to be resident for long enough—inefficient patterns are instead predicted to be resident for longer—then a core hop request is denied. As a result, designers may implement a policy for avoiding core hops that weighs the potential gain of the core hop, such as alleviation of a core hop condition, against a penalty for performing the core hop, such as a temporal penalty for the core hop. Separately, idle durations associated with hardware power states for cores may be predicted in hardware. Furthermore, accuracy of the idle duration prediction is determined.

Abstract: A method and a secure mode controller are provided for controlling context switching between secure and user modes in a processing system including a processor and a memory management unit. The method comprises monitoring the memory management unit to detect a non-cache access to an entry point address that contains a secure mode entry instruction, verifying, in response to detection of the entry point address, that the secure mode entry point instruction is executed by the processor, and enabling context switching from the user mode to the secure mode in response to verifying that the secure mode entry instruction is executed by the processor. Each cache line of an instruction cache and a data cache may have a tag containing a secure bit to identify a secure cache line or a non-secure cache line.

Abstract: Systems and methods for recording instruction sequences in a microprocessor having a dynamically decoupleable extended instruction pipeline. A record instruction including a record start address is sent to the extended pipeline. The extended pipeline thus begins recording the subsequent instruction sequence at the specified address until an end record instruction is encountered. The end record instruction is recorded as the last instruction in the sequence. The main pipeline may then call the instruction sequence by sending a run instruction including the start address for the desired sequence to the extended pipeline. This run instruction causes the extended pipeline to begin autonomously executing the recorded sequence until the end record instruction is encountered. This instruction causes the extended pipeline to cease autonomous execution and to return to executing instructions supplied by the main pipeline.

Abstract: A method, system, and computer program product for reduced overhead address mode change management in a pipelined, recycling microprocessor are provided. The recycling microprocessor includes logic executing thereon. The microprocessor also includes an instruction fetch unit (IFU) supporting computation of address adds in selected address modes and reporting non-equal comparison of the computation to the logic. The microprocessor further includes a fixed point unit determining whether the mode has changed and reporting changes to the logic. Upon determining the comparison yields an equal result but the mode has changed, a recycle event is triggered to ensure subsequent ofetches are relaunched in the correct mode and that no execution writebacks occur from work performed in an incorrect mode.

Abstract: An electronic system includes a pipeline having a first number of pipeline stages coupled in series, a pipeline control unit, and a logic engine, wherein each pipeline stage in the pipeline is for outputting data to a next pipeline stage at each cycle of a clock signal. The pipeline control unit is for changing the first number of pipeline stages in the pipeline to a second number of pipeline stages. The logic engine is for performing operations of the electronic system in a first mode by utilizing the pipeline having the first number of pipeline stages and for performing operations of the electronic system in a second mode by utilizing the pipeline having the second number of pipeline stages. A frequency control unit and a voltage control unit, coupled to the pipeline and the logic engine, respectively adjust the frequency and voltage of the electronic system accordingly.

Abstract: In one embodiment, a processor can operate in multiple modes, including a direct execution mode and an emulation execution mode. More specifically, the processor may operate in a partial emulation model in which source instruction set architecture (ISA) instructions are directly handled in the direct execution mode and translated code generated by an emulation engine is handled in the emulation execution mode. Embodiments may also provide for efficient transitions between the modes using information that can be stored in one or more storages of the processor and elsewhere in a system. Other embodiments are described and claimed.

Abstract: Handling parallelism in transactions. One embodiment includes a method that includes beginning a cache resident transaction. The method further includes encountering a nested structured parallelism construct within the cache resident transaction. A determination is made as to whether the transaction would run faster serially in cache resident mode or faster parallel in software transactional memory mode for the overall transaction. In the software transactional memory mode, cache resident mode is used for one or more hierarchically lower nested transactions. The method further includes continuing the transaction in the mode determined.

Abstract: A data processing device has a processor (10) operable at selectable ones of a plurality of performance levels. The processor generates a workload data vector indicating a workload of the processor as a function of time. A memory stores a set of reference workload vectors. A pattern matcher (18) detects whether there is a matching reference workload data vector. A performance level controller (19) selects the performance level of the processor based on control information that is stored in combination with the matching workload data vector.

Abstract: A processor having one or more processor cores includes execution logic that may execute instructions including one or more processes. Each process may include one or more execution threads. The processor also includes a profiling mechanism that includes monitor logic and a monitor process. The monitor logic may monitor the one or more processes and provide access to performance data associated with the one or more processes without interrupting a flow of control of the one or more processes being monitored. The monitor process may gather the performance data. In addition, the monitor process may include program instructions executable by the one more processor cores while operating in user mode.

Abstract: Real time provisioning and management of fabric-backplane enterprise servers includes monitoring system status and configuration, displaying monitoring results, accepting user commands, and providing hardware and software management and configuration commands to the system. In one embodiment, an event is generated when a pluggable module is inserted into the system. In response to the event, the availability of the pluggable module is displayed to a system operator, and the operator enters a command to provision a server that includes the pluggable module. The server provisioning command is processed, resulting in a hardware configuration command being issued to the system, and an event indicating a status associated with processing the command is returned. The recognition of the inserted module, the display to the operator, and the processing of the server provisioning command occur in real time.

Abstract: A processor according to the present invention cyclically executes a plurality of threads, for each time period allocated thereto. The processor stores, for each thread, configuration information of operation cells. Each of the threads (i) causes the execution of a different predetermined number of operation cells in series, and successively reconfigures an operation cell that has completed a last operation thereof in the time period allocated to a current thread, based on a stored piece of configuration information of the operation cell that corresponds to a next thread, and (ii) causes concurrent execution of an operation cell having a configuration for the current thread and an operation cell having a configuration for the next thread.

Abstract: An apparatus for processing data includes a processor operable in a plurality modes including at least one secure mode being a mode in a secure domain and at least one non-secure mode being a mode in a non-secure domain. When the processor is executing a program in a secure mode the program has access to secure data which is not accessible when the processor is operating in a non-secure mode. The processor is responsive to one or more exception conditions for triggering exception processing using an exception handler. The processor is operable to select the exception handler from among a plurality of possible exception handlers in dependence upon whether the processor is operating in the secure domain or the non-secure domain.

Abstract: A method and system for executing 32-bit flat address programs during a System Management Interrupt. The system provides a 16-bit SMI routine that is given control when an SMI occurs. That routine initially saves the state of the processor and then executes an instruction to switch to protected mode. When in protected mode, the routine transfers control to 32-bit code. The 32-bit code uses a global descriptor table that is different from that used by the interrupted operating system. When the 32-bit code completes, it restores the saved processor state and returns from the interrupt by executing an RSM instruction.

Abstract: Brings the response time of a Web server and the like closer to a targeted value. A controller controlling the average response time elapsed between reception by information processing apparatus of a processing request and response of information processing apparatus to the processing request. The controller including: a section for obtaining a response time goal which is a target value of the average response time; a section for calculating a predicted response time which is a predicted value of the average response time at the time point when a predetermined reference period has elapsed from setting an operation mode in the information processing apparatus, the operation mode being any of a plurality of operation modes which provide different throughputs; and a section for setting the operation mode in the information processing apparatus if predicted response time calculated by the predicted response time calculating section is less than goal.

Abstract: Within a data processing system including a register renaming mechanism, register renaming for some conditional instructions which are predicted as not-executed is suppressed. The conditional instructions which are subject to such suppression of renaming may not be all conditional instructions, but may be those which are known to consume a particularly large number of physical registers if they are subject to renaming A conditional load multiple instruction in which multiple registers are loaded with new data values taken from memory in response to a single instruction is an example where the present technique may be used, particularly when one of the registers loaded is the program counter and accordingly the instruction is a conditional branch.

Abstract: A data processing apparatus and method are provided for handling instructions to be executed by processing circuitry. The processing circuitry has a plurality of processor states, each processor state having a different instruction set associated therewith. Pre-decoding circuitry receives the instructions fetched from the memory and performs a pre-decoding operation to generate corresponding pre-decoded instructions, with those pre-decoded instructions then being stored in a cache for access by the processing circuitry. The pre-decoding circuitry performs the pre-decoding operation assuming a speculative processor state, and the cache is arranged to store an indication of the speculative processor state in association with the pre-decoded instructions.

Abstract: An image processing device includes an operating unit and a plurality of control units each configured to control the operating unit in order to execute a function on image data. The plurality of control units include at least a first control unit and a second control unit. When a first mode is selected, the control units control the operating unit to execute the function in cooperation with each other. When a second mode is selected, at least the second control unit controls the operating unit to execute the function without cooperating with the first control unit.