Abstract: The present disclosure is directed to a high-capacity training and prediction machine learning platform that can support high-capacity parameter models (e.g., with 10 billion weights). The platform implements a generic feature transformation layer for joint updating and a distributed training framework utilizing shard servers to increase training speed for the high-capacity model size. The models generated by the platform can be utilized in conjunction with existing dense baseline models to predict compatibilities between different groupings of objects (e.g., a group of two objects, three objects, etc.).

Abstract: Methods and apparatus to manage and execute action in computing environments are disclosed. An example system includes a virtual machine resource platform to host a virtual compute node and a resource manager to: in response to a user request associated with the virtual compute node: determine a type of the virtual compute node; determine if an installed adapter identifies a type associated with the type of the virtual compute node; and when the adapter identifies the type associated with the type of the virtual compute node, present a user selectable identification of the adapter.

Abstract: A method of updating at least two interconnected devices in a local network, a local network comprising at least two interconnected devices and a method of operating a remote management client and a device in this local network are provided. A resource location information of an update archive is communicated from a remote management client in the local network to the other devices in said network. The devices participating in the update communicate participation acknowledgement messages to the remote management client. The participating devices determine whether a next one of a predefined sequence of update statuses is reached. They notify the other participating devices that this update status has been reached and pause until all other participating devices have notified that they also have reached the same update status.

Abstract: A method maintains power usage prediction information for one or more functional units in branch prediction logic for a processing unit such that the power consumption of a functional unit may be selectively reduced in association with the execution of branch instructions when it is predicted that the functional unit will be idle subsequent to the execution of such branch instructions.

Abstract: The present invention discloses a method for executing an SQL operator on compressed data chunk. The method comprising the step of: receiving SQL operator, accessing compressed data chunk blocks, receive e full set of derivatives of the compression scheme, check compression rules based on the compression scheme and relevant operator for approving SQL operation on compressed data and in case of approval applying respective SQL operator on relevant compressed data chunks.

Abstract: A circuit arrangement maintains power usage prediction information for one or more functional units in branch prediction logic for a processing unit such that the power consumption of a functional unit may be selectively reduced in association with the execution of branch instructions when it is predicted that the functional unit will be idle subsequent to the execution of such branch instructions.

Abstract: A wireless local area network system establishes a PASSPOINT™ connection between a mobile station and a hotspot using an enhanced single SSID method or an enhanced dual SSID method. In the dual SSID method, an access point associates and authenticates a mobile device to a secondary SSID of the access point during enrollment and provisioning. After enrollment, the access point authenticates the mobile station to a primary SSID of the access point using the credential that the mobile station received from an online sign-up (“OSU”) server in connection with the secondary SSID. In the single SSID method, an access point performs two levels of authentication. During authentication, communications are limited to an 802.1x controlled port running on the mobile station and access point. After a first authentication, communications between the OSU server and the mobile station are unblocked. After the second authentication, all traffic from the mobile station is unblocked.

Abstract: A mobile terminal device receives a request for a sensing operation from an application program, specifies candidate processors that are to perform condition determination to determine whether an event output from a sensor performing the sensing operation of the received request satisfies conditions for notification, the conditions being designated by the application program, calculates an evaluation value of electricity consumed by each of the candidate processors in the condition determination, using frequency of the event of the sensing operation of the received request in frequency data, the frequency data linking an event output from a sensor to frequency of generation of the event, and selects a candidate processor having an optimal evaluation value.

Abstract: Embodiments of the present invention provide efficient systems and methods for processing large data sets using a composite function. Embodiments of the present invention can be used to compute a broad range of composite functions in a single map-reduce job. Each mapper computes an additive function G on a set of specified data partitions, and then passes the results to one or more reducers. The one or more reducers can then compute a function F, using the aggregate results of function G and data from a single partition.

Abstract: A software emulator for emulating a handheld video game platform such as GAME BOY®, GAME BOY COLOR® and/or GAME BOY ADVANCE® on a low-capability target platform (e.g., a seat-back display for airline or train use, a personal digital assistant, a cell phone) uses a number of features and optimizations to provide high quality graphics and sound that nearly duplicates the game playing experience on the native platform. Some exemplary features include use of bit BLITing, graphics character reformatting, modeling of a native platform liquid crystal display controller using a sequential state machine, and selective skipping of frame display updates if the game play falls behind what would occur on the native platform.

Abstract: A computational device maintains a spinlock for exclusive access of a resource by a process of a plurality of processes. In response to determining by the process that a turn for securing the spinlock has not arrived for the process, a sleep duration is determined for the process, prior to making a next attempt to secure the spinlock.

Abstract: A method of processing multimedia data includes: separating a defined application kernel into a data patch kernel and a data processing kernel; requesting, by the data processing kernel, access to patch data of the multimedia data, from the data patch kernel; performing, by the data patch kernel, an operation that is independent of the request and preparing data for the data access based on the request; and performing, by the data processing kernel, an arithmetic operation on work items of the prepared data when the data has been prepared by the data patch kernel.

Abstract: A method of enhancing performance of an application executing in a parallel processor and a system for executing the method are disclosed. A block size for input to the application is determined. Input is partitioned into blocks having the block size. Input within each block is sorted. The application is executed with the sorted input.

Abstract: Systems and methods for improving the time and cost to calculate connected components in a distributed graph are disclosed. One method includes reducing a quantity of map-reduce rounds used to determine a cluster assignment for a node in a large distributed graph by alternating between two hashing functions in the map stage of a map-reduce round and storing the cluster assignment for the node in a memory. Another method includes reducing a quantity of messages sent during map-reduce rounds by performing a predetermined quantity of rounds to generate, for each node, a set of potential cluster assignments, generating a data structure in memory to store a mapping between each node and its potential cluster assignment, and using the data structure during remaining map-reduce rounds, wherein the remaining map-reduce rounds do not send messages between nodes. The method can also include storing the cluster assignment for the node in a memory.

Abstract: A semiconductor device may include a first processor transferring a plurality of command data sets, a mailbox receiving and storing the plurality of command data sets, and a second processor receiving command data sets of the mailbox, wherein the first processor may transfer at least one abort slot number to the mailbox, and wherein the mailbox may search and abort a command data set having a slot number which is identical to an abort slot number among the plurality of command data sets.

Abstract: A data processing system includes a plurality of transaction masters, each with an associated local cache memory and coupled to coherent interconnect circuitry. Monitoring circuitry within the coherent interconnect circuitry maintains a state variable (flag) in respect of each of the transaction masters to monitor whether an exclusive store access state is pending for that transaction master. When a transaction master is to execute a store-exclusive instruction, then a current value of the subject state variable for that transaction master is compared with a previous value of that variable stored when the exclusive store access was setup. If there is a match, then store-exclusive instruction is allowed to proceed and the state variables of all other transaction masters for which there is a pending exclusive store access state are changed. If there is not a match, then the execution of the store-exclusive instruction is marked as failing.

Abstract: In a typical embodiment, a parallel processor is provided that includes: A plurality of parallel processing units that are interconnected to provide a flexible hardware programmable, scalable and re-configurable parallel processor that executes different functions in a parallel processor space domain instead of a processor (serial processor) time domain. Each parallel processing unit includes a flexible processing engine with its inputs and outputs connected to MDDP-RAM blocks. The MDDP-RAM blocks provide the processing engine with different channels' data and coefficients. The processing engine and the MDDP-RAM blocks are controlled by a system processor (or other control scheme hardware) via the parameter blocks to enable high hardware flexibility and software programmability.

Abstract: One embodiment of the present invention sets forth a technique for managing the allocation and release of resources during multi-threaded program execution. Programmable reference counters are initialized to values that limit the amount of resources for allocation to tasks that share the same reference counter. Resource parameters are specified for each task to define the amount of resources allocated for consumption by each array of execution threads that is launched to execute the task. The resource parameters also specify the behavior of the array for acquiring and releasing resources. Finally, during execution of each thread in the array, an exit instruction may be configured to override the release of the resources that were allocated to the array. The resources may then be retained for use by a child task that is generated during execution of a thread.

Abstract: A method, article of manufacture, and apparatus for managing data. In some embodiments, this includes an initial instruction for a file stored in a first storage system, determining that the initial instruction is not supported by the first storage system, identifying a combination of instructions to the first storage system after determining that the initial instruction is not supported by the first storage system, wherein the combination of instructions is based on the initial instruction, performing the identified combination of instructions on the file stored in the first storage system, and storing results of the performed identified combination of instructions.

Abstract: A method, article of manufacture, and apparatus for managing data. In some embodiments, this includes an initial instruction for a file stored in a first storage system, determining that the initial instruction is not supported by the first storage system, identifying a combination of instructions to the first storage system after determining that the initial instruction is not supported by the first storage system, wherein the combination of instructions is based on the initial instruction, performing the identified combination of instructions on the file stored in the first storage system, and storing results of the performed identified combination of instructions.

Abstract: An array data processor employs a plurality of address generators for communicating between groups of the data processors and external devices. In another aspect, the data processor employs a buffer system having a plurality of pointers that allow for retransmission of data from the buffer upon transfer failure.

Abstract: The present invention relates to the field of real-time executives and their adaptation for secure execution on a multicore processor. There is defined, in addition to the level of certification intrinsic to each task, a level of security relating to the criticality of the execution of the instance of the task in its context and by a method of sequencing distributed over the various cores which make it possible to exchange, during each time interval, the information relating to the level of certification and to the level of security of each of the tasks getting ready to be launched. A decision is then taken on each core for launching the task envisaged as a function of the relevant information received from the other cores.

Abstract: High speed reading of fiscal information from memory is enabled while complying with financial regulations. Including fiscal memory 10 that stores fiscal information, a first control unit 5 that controls communication with the host computer 2 and operates at a first processing speed, and a second control unit 7 that controls operation of the fiscal memory 10 and operates at a second processing speed that is lower than the first processing speed, the second control unit 7 performs a write process writing fiscal information received from the host computer 2 to fiscal memory 10, and the first control unit 5 executes a read process reading the fiscal information stored in the fiscal memory 10 without involving processing by the second control unit 7.

Abstract: A memory system includes a non-volatile memory, a compressor capable of compressing data, an encryptor which encrypts data, a decryptor which decrypts data, and a data flow controller. The data flow controller is configured to perform first and second processes. In the first process, the data flow controller causes the encryptor to encrypt user data received from a host in a non-compressed state, and causes the encrypted user data to be written into the non-volatile memory via the second area. In the second process, the data flow controller causes the encrypted user data to be read out from the non-volatile memory, causes the decryptor to decrypt the encrypted user data, causes the compressor to compress the decrypted user data, causes the encryptor to encrypt the compressed user data, and causes the encrypted and compressed user data to be written into the non-volatile memory.

Abstract: Provided are a method and apparatus for migrating a task in a multi-core platform including a plurality of cores. The method includes transmitting codes of the task that is being performed in a first core among the plurality of cores to a second core among the plurality of cores, the transmitting of the codes being performed while performing the task at the first core, and resuming performing of the task in the second core based on the transmitted codes.

Abstract: According to at least one example embodiment, a method and corresponding processor device comprise maintaining a translation data structure mapping uncompressed process context identifiers to corresponding compressed identifiers, the uncompressed process context identifiers and the corresponding compressed identifiers being associated with address spaces or corresponding computer processes. The compressed identifiers are employed to probe, or access, one or more structures of the processor device in executing an operation associated with a computer process.

Abstract: Methods and apparatus for client-allocatable bandwidth pools are disclosed. A system includes a plurality of resources of a provider network and a resource manager. In response to a determination to accept a bandwidth pool creation request from a client for a resource group, where the resource group comprises a plurality of resources allocated to the client, the resource manager stores an indication of a total network traffic rate limit of the resource group. In response to a bandwidth allocation request from the client to allocate a specified portion of the total network traffic rate limit to a particular resource of the resource group, the resource manager initiates one or more configuration changes to allow network transmissions within one or more network links of the provider network accessible from the particular resource at a rate up to the specified portion.

Abstract: A data stream processing unit (DPU) and method for use are provided. A DPU includes a number of processing elements arranged in a sequence, and each datum in the data stream visits each processing element in sequence. Each processing element has a memory circuit, data and metadata input and output channels, and a computing circuit. The metadata input represents a partial computational state that is associated with each datum as it passes through the DPU. The computing circuit for each processing element operates on the data and metadata inputs as a function of its position in the sequence, producing an altered partial computational state that accompanies the datum. Each computing circuit may be modeled, for example, as a finite state machine, and the collection of processing elements cooperate to perform the computation. The computing circuits may be collectively programmed to perform any desired computation.

Abstract: A processing device includes an execute processor configured to execute data processing instructions; and an access processor configured to be coupled with a memory system to execute memory access instructions; wherein the execute processor and the access processor are logically separated units, the execute processor having an execute processor input register file with input registers, and a data processing instruction is executed as soon as all operands for the respective data processing instruction are available in the input registers.

Abstract: A data processing apparatus includes multiple processing means that are connected in a ring shape via corresponding communication means respectively. Each communication means includes a reception means for receiving data from a previous communication means, and a transmission means for transmitting data to a next communication means. Connection information is assigned to each of the reception means and the transmission means. The communication means, when receiving a packet that has same connection information as one assigned to its reception means, causes the corresponding processing means to perform data processing on the packet, sets the connection information assigned to its transmission means to the packet, and transmits the packet to the next communication means, and when receiving a packet that has connection information that is not same as one assigned to its reception means, transmits the packet to the next communication means without changing the connection information of the packet.

Abstract: Controlling access to a resource in a distributed computing system that includes nodes having a status field, a next field, a source data buffer, and that are characterized by a unique node identifier, where controlling access includes receiving a request for access to the resource implemented as an active message that includes the requesting node's unique node identifier, the value stored in the requesting node's source data buffer, and an instruction to perform a reduction operation with the value stored in the requesting node's source data buffer and the value stored in the receiving node's source data buffer; returning the requesting node's unique node identifier as a result of the reduction operation; and updating the status and next fields to identify the requesting node as a next node to have sole access to the resource.

Abstract: Illustrated is a system and method that includes a processor and service processor co-located on a common socket, the service processor to aggregate data from a distributed network of additional service processors and processors both of which are co-located on an additional common socket. The system and method also includes a first sensor to record the data from the processor. The system and method also includes a second sensor to record the data from a software stack. The system and method further includes a registry to store the data.

Abstract: A packet processor implemented in hardware. The packet processor includes a processing pipeline including a plurality of processing elements. The plurality of processing elements are configured to process a first data packet transferred sequentially through the plurality of processing elements. The first data packet includes information indicating a period of time that at least a first processing element of the plurality of processing elements uses to process the first data packet. The first processing element is prevented from processing other data packets due to performing processing on the first data packet during the period of time. A packet rate shaper is configured to, prior to the first data packet entering the processing pipeline, read the information in the first data packet, selectively increment and decrement a token value, and selectively grant the first data packet access to the processing pipeline based on the information and based on the token value.

Abstract: A method, apparatus, and system in which an integrated circuit comprises an initiator Intellectual Property (IP) core, a target IP core, an interconnect, and a tag and thread logic. The target IP core may include a memory coupled to the initiator IP core. Additionally, the interconnect can allow the integrated circuit to communicate transactions between one or more initiator Intellectual Property (IP) cores and one or more target IP cores coupled to the interconnect. A tag and thread logic can be configured to concurrently perform per-thread and per-tag memory access scheduling within a thread and across multiple threads such that the tag and thread logic manages tags and threads to allow for per-tag and per-thread scheduling of memory accesses requests from the initiator IP core out of order from an initial issue order of the memory accesses requests from the initiator IP core.

Abstract: A management unit causes a plurality of processing units to execute a calculation process. A determining unit determines whether a communication time for a communication process of exchanging a calculation result obtained from the calculation process is longer than a calculation time for the calculation process, the communication process being executed between a first computational node including the processor and a second computational node being a different computational node from the first computational node. A control unit limits number of processing units when the determining unit has determined that the communication time is longer than the calculation time.

Abstract: A medium, method, and apparatus are disclosed for eliding superfluous function invocations in a vector-processing environment. A compiler receives program code comprising a width-contingent invocation of a function. The compiler creates a width-specific executable version of the program code by determining a vector width of a target computer system and omitting the function from the width-specific executable if the vector width meets one or more criteria. For example, the compiler may omit the function call if the vector width is greater than a minimum size.

Abstract: Methods, devices, and systems for automatically determining how an application program may be partitioned and offloaded for execution by a general purpose applications processor and an auxiliary processor (e.g., a DSP, GPU, etc.) within a mobile device. The mobile device may determine the portions of the application code that are best suited for execution on the auxiliary processor based on pattern-matching of directed acyclic graphs (DAGS). In particular, the mobile device may identify one or more patterns in the code, particularly in a data flow graph of the code, comparing each identified code pattern to predefined graph patterns known to have a certain benefit when executed on the auxiliary processor (e.g., a DSP). The mobile device may determine the costs and/or benefits of executing the potions of code on the auxiliary processor, and may offload portions that have low costs and/or high benefits related to the auxiliary processor.

Abstract: Techniques are described for transmitting predicted output data on a processing element in a stream computing application instead of processing currently received input data. The stream computing application monitors the output of a processing element and determines whether its output is predictable, for example, if the previously transmitted output values are within a predefined range or if one or more input values correlate with the same one or more output values. The application may then generate a predicted output value to transmit from the processing element instead of transmitting a processed output value based on current input values. The predicted output value may be, for example, an average of the previously transmitted output values or a previously transmitted output value that was transmitted in response to a previously received input value that is similar to a currently received input value.

Abstract: Mobile computing devices may be configured to intelligently select, compile, and execute portions of a general purpose software application in an auxiliary processor (e.g., a DSP) of a multiprocessor system. A processor of the mobile device may be configured to determine whether portions of a software application are suitable for execution in an auxiliary processor, monitor operating conditions of the system, determine a historical context based on the monitoring, and determine whether the portions that were determined to suitable for execution in an auxiliary processor should be compiled for execution in the auxiliary processor based on the historical context. The processor may also be configured to continue monitoring the system, update the historical context information, and determine whether code previously compiled for execution on the auxiliary processor should be invoked or executed in the auxiliary processor based on the updated historical context information.

Abstract: Techniques are described for transmitting predicted output data on a processing element in a stream computing application instead of processing currently received input data. The stream computing application monitors the output of a processing element and determines whether its output is predictable, for example, if the previously transmitted output values are within a predefined range or if one or more input values correlate with the same one or more output values. The application may then generate a predicted output value to transmit from the processing element instead of transmitting a processed output value based on current input values. The predicted output value may be, for example, an average of the previously transmitted output values or a previously transmitted output value that was transmitted in response to a previously received input value that is similar to a currently received input value.

Abstract: Increasing the energy scale of a quantum processor improves its performance. Energy scale of a quantum processor may be increased by increasing the coupling strength of communicatively coupled superconducting devices comprised in the quantum processor. Configuring the physical dimensions of communicatively coupled superconducting devices such that an intentional direct coupling is induced between a pair of superconducting devices communicatively coupled by a coupling device may controllably add an additional mutual inductance to the mutual inductance of the pair of superconducting devices. Furthermore, reducing the beta parameter of a coupling device may improve the tunability of the coupling device. The combined effects of improved tunability of the coupling devices and the increased coupling strength between superconducting devices communicatively coupled by respective coupling devices comprised in the quantum processor may thus improve the performance of the quantum processor.

Abstract: A processing arrangement having a first processing component and a second processing component is provided. The first component has a first output memory and a second output memory and a control device using the first memory storing a value to be output and the second memory stores a value that is based according to a prescribed function on the value. The control device stores a new value in the first memory whenever the second component has read a value stored in the first memory. The second component has a reading device reading the values stored in the first and second memories, and a processing device that checks whether the value read from the second memory is based according to the prescribed function on the value read from the first memory and, depending on the result, to process the value read from the first memory.

Abstract: There is provided a method of, and apparatus for, processing a computation on a computing device comprising at least one processor and a memory, the method comprising: storing, in said memory, plural copies of a set of data, each copy of said set of data having a different compression ratio and/or compression scheme; selecting a copy of said set of data; and performing, on a processor, a computation using said selected copy of said set of data. By providing such a method, different compression ratios and/or compression schemes can be selected as appropriate. For example, if high precision is required in a computation, a copy of the set of data can be chosen which has a low compression ratio at the expense of processing time and memory transfer time. In the alternative, if low precision is acceptable, then the speed benefits of a high compression ratio and/or lossy compression scheme may be utilised.

Abstract: For flexibly setting up an execution environment according to contents of processing to be executed while taking stability or a security level into consideration, the multiple processor system includes the execution environment main control unit 10 which determines CPU assignment at the time of deciding CPU assignment, the execution environment sub control unit 20 which controls starting, stopping and switching of an execution environment according to an instruction from the execution environment main control unit 10 to synchronize with the execution environment main control unit 10, and the execution environment management unit 30 which receives input of management information or reference refusal information of shared resources for each CPU 4 or each execution environment 100 to separate the execution environment main control unit 10 from the execution environment sub control units 20a through 20n, or the execution environment sub control units 20a through 20n from each other.

Abstract: A method and system of efficient use and programming of a multi-processing core device. The system includes a programming construct that is based on stream-domain code. A programmable core based computing device is disclosed. The computing device includes a plurality of processing cores coupled to each other. A memory stores stream-domain code including a stream defining a stream destination module and a stream source module. The stream source module places data values in the stream and the stream conveys data values from the stream source module to the stream destination module. A runtime system detects when the data values are available to the stream destination module and schedules the stream destination module for execution on one of the plurality of processing cores.

Abstract: A reconfigurable tree apparatus with a bypass mode and a method of using the reconfigurable tree apparatus are disclosed. The reconfigurable tree apparatus uses a short-circuit register to selectively designate participating agents for such operations as barriers, multicast, and reductions. The reconfigurable tree apparatus enables an agent to initiate a barrier, multicast, or reduction operation, leaving software to determine the participating agents for each operation. Although the reconfigurable tree apparatus is implemented using a small number of wires, multiple in-flight barrier, multicast, and reduction operations can take place. The method and apparatus have low complexity, easy reconfigurability, and provide the energy savings necessary for future exa-scale machines.

Abstract: Systems and methods for managing reconfigurable processor cores. An example processing system comprises a plurality of processor cores; a control register including a plurality of state bits, each state bit indicating a state of a corresponding processor core, the control register further including a plurality of inhibit bits, each inhibit bit indicating whether a corresponding processor core is allowed to merge with other processor cores; and a core management logic configured to merge a first processor core and a second processor core, responsive to determining that a first state bit corresponding to the first processor core is set, a first inhibit bit corresponding to the first processor core is cleared, a second state bit corresponding to the second processor core is cleared, and a second inhibit bit corresponding to the second processor core is cleared.

Abstract: Methods, systems, and media are provided for a dynamic batch strategy utilized in parallelization of online learning algorithms. The dynamic batch strategy provides a merge function on the basis of a threshold level difference between the original model state and an updated model state, rather than according to a constant or pre-determined batch size. The merging includes reading a batch of incoming streaming data, retrieving any missing model beliefs from partner processors, and training on the batch of incoming streaming data. The steps of reading, retrieving, and training are repeated until the measured difference in states exceeds a set threshold level. The measured differences which exceed the threshold level are merged for each of the plurality of processors according to attributes. The merged differences which exceed the threshold level are combined with the original partial model states to obtain an updated global model state.

Abstract: A method, device, system, or article of manufacture is provided for low-power management of multiple sensor chip architecture. In one embodiment, a method comprises, at a computing device that includes a first processor, a second processor and a third processor, performing, by the second processor, a first scan at a first scan rate for first location data using a sensor; receiving, at the second processor, from the sensor, the first location data; determining, by the second processor, a first location using the first location data; receiving, by the second processor, a modality of the computing device; in response to determining the first location, determining, by the second processor, that the modality corresponds to a predetermined state; and in response to determining that the modality corresponds to the predetermined state, performing, by the second processor, a second scan at a second scan rate for second location data using the sensor.

Abstract: A method, device, system, or article of manufacture is provided for low-power management of multiple sensor chip architecture. In one embodiment, a method comprises, at a computing device that includes a first processor, a second processor and a third processor, receiving, at the first processor, first sensor data from a first sensor; determining, at the first processor, a motion state of the computing device using the first sensor data; in response to determining that the motion state corresponds to a predetermined motion state, activating the second processor; receiving, at the second processor, second sensor data from a second sensor; determining, by the second processor, that the motion state corresponds to the predetermined motion state using the second sensor data; and, in response to determining that the motion state corresponds to the predetermined motion state using the second sensor data, sending the motion state to the third processor.