Abstract: In one embodiment, a processor comprises execution circuitry and a translation lookaside buffer (TLB) coupled to the execution circuitry. The execution circuitry is configured to execute a store instruction having a data operand; and the execution circuitry is configured to generate a virtual address as part of executing the store instruction. The TLB is coupled to receive the virtual address and configured to translate the virtual address to a first physical address. Additionally, the TLB is coupled to receive the data operand and to translate the data operand to a second physical address. A hardware accelerator is also contemplated in various embodiments, as is a processor coupled to the hardware accelerator, a method, and a computer readable medium storing instruction which, when executed, implement a portion of the method.

Abstract: A semiconductor device including a multi-layer interconnection substrate having a signal distribution interconnection and a power supply line and semiconductor circuit blocks installed on the multi-layer interconnection substrate for performing required operations. The multi-layer substrate includes a third interconnection layer having interconnections extending in a first direction, a second interconnection layer having interconnections extending in a second direction which is different to the first direction, and a first interconnection layer having interconnections extends in a direction orthogonal to the first direction.

Abstract: The present invention is directed to a method and a device for memory share by a plurality of processors. The portable terminal according to an embodiment of the present invention comprises a main memory; a sub-control unit coupled to the main memory through bus #1, the sub-control unit processing and storing raw data in accordance with a process order, the raw data being stored in the main memory, the main memory being accessed through bus #1; and a main control unit coupled to the main memory through bus #2 and coupled to the sub-control unit independently through bus #3, the main control unit transmitting said process order to the sub-control unit through bus #3. The present invention can prevent the weakening of processing power or the bottleneck problem during the process of information transmission between the memory and a plurality of processors.

Abstract: In one embodiment, a method is contemplated. Access to a hardware accelerator is requested by a user-privileged thread. Access to the hardware accelerator is granted to the user-privileged thread by a higher-privileged thread responsive to the requesting. One or more commands are communicated to the hardware accelerator by the user-privileged thread without intervention by higher-privileged threads and responsive to the grant of access. The one or more commands cause the hardware accelerator to perform one or more tasks. Computer readable media comprises instructions which, when executed, implement portions of the method are also contemplated in various embodiments, as is a hardware accelerator and a processor coupled to the hardware accelerator.

Abstract: The invention is a method of managing application (AP) execution in an electronic token (ET) comprising at least a first and a second microprocessors (MP1, MP2). One of the microprocessor is the master microprocessor when it has responsibility for application (AP) execution. Said method comprises the step of: selecting (E1) the first microprocessor as master microprocessor, then the step of starting (E2) application (AP) execution by the first microprocessor, then the step of transferring (E4, E12) the responsibility for application (AP) execution to the second microprocessor during the application (AP) execution.

Abstract: Task and data management systems methods and apparatus are disclosed. A processor event that requires more memory space than is available in a local storage of a co-processor is divided into two or more segments. Each segment has a segment size that is less than or the same as an amount of memory space available in the local storage. The segments are processed with one or more co-processors to produce two or more corresponding outputs. The two or more outputs are associated into one or more groups. Each group is less than or equal to a target data size associated with a subsequent process.

Abstract: This invention describes a baseband dual-core signal processing in mobile communication systems operating according to GSM, GPRS, or EDGE comprising a first digital signal processor adapted to perform tasks on a first time basis and a second digital signal processor adapted to perform tasks on a second time basis. The second time basis is an integer multiple of the first time basis.

Abstract: A coprocessor (14) may be used to perform one or more specialized operations that can be off-loaded from a primary or general purpose processor (12). It is important to allow efficient communication and interfacing between the processor (12) and the coprocessor (14). In one embodiment, a coprocessor (14) generates and provides instructions (200, 220) to an instruction pipe (20) in the processor (12). Because the coprocessor (14) generated instructions are part of the standard instruction set of the processor (12), cache (70) coherency is easy to maintain. Also, circuitry (102) in coprocessor (14) may perform an operation on data while circuitry (106) in coprocessor (14) is concurrently generating processor instructions (200, 220).

Abstract: In a multi-processor system (100), when a first processor interrupt generation unit (24) has executed a call command or a jump command in a main routine being executed, it generates an interrupt to a second processor. Upon reception of the interrupt from the interrupt generation unit (24), the second processor saves the return address for returning to the main routing upon completion of the subroutine processing called by the call command in a main memory area (54) other than the first processor or generates a call destination address and a jump destination address and reports it to the first processor. Thus, the first processor can be a small-size circuit capable of flexibly performing processing.

Abstract: A high-assurance system for processing information is disclosed. The high-assurance system comprising first and second processors, a task matching circuit, and first and second outputs. The task matching circuit configured to determine a software routine is ready for execution on the first processor, and delay the first processor until the second processor is ready to execute the software routine. The first output of the first processor configured to produce a first result with the software routine. The second output of the second processor configured to produce a second result with the software routine, where the first result is identical to the second result.

Abstract: A method and controller for supporting out of order execution of instructions is described. A microprocessor is coupled to a coprocessor via a controller. Instructions are received by the microprocessor and the controller. Indices respectively associated with the instructions are generated by the microprocessor, and the instructions are popped from the first queue for execution by the coprocessor. The controller includes a first queue and a second queue. The instructions and the indices are queued in the first queue, and this first queuing includes steering the instructions and the indices associated therewith to respective first register locations while maintaining association between the instructions and the indices. The instructions may be popped off the first queue out of order with respect to an order in which the instructions are received into the first queue.

Abstract: A hardware accelerator is used to execute a floating-point byte-code in an information processing device. For a floating-point byte-code, a byte-code accelerator BCA feeds an instruction stream for using a FPU to a CPU. When the FPU is used, first the data is transferred to the FPU register from a general-purpose register, and then an FPU operation is performed. For data, such as a denormalized number, that cannot be processed by the FPU, in order to call a floating-point math library of software, the processing of the BCA is completed and the processing moves to processing by software. In order to realize this, data on a data transfer bus from the CPU to the FPU is snooped by the hardware accelerator, and a cancel request is signaled to the CPU to inhibit execution of the FPU operation when corresponding data is detected in a data checking part.

Abstract: A plurality of digital signal processors (10), each contains a signal processing core (22), a memory (20) coupled to the processing core (22) and a multiplexed data input (16) coupled to the memory (20). Each digital signal processor has a plurality of outputs for outputting data from the signal processing core (22). A remote write only structure (14a-d) couples outputs of respective groups of the digital signal processors (10) each to the multiplexed data input (16) of respective particular digital signal processor (10), the respective group for the particular digital signal processor (10) not including the particular digital signal processor (10). Thus, each processor (10) writes data for other processors directly from the processor, without storing the data in memory first for handling by an I/O processor, and reads data from other processors (10) via memory, where it is received via an input that does not share resources with the output of the processor (10).

Abstract: A companion chip for a microcontroller has a microprocessor bus domain and a peripheral module bus domain, which are connected to each other via a bus bridge. The microprocessor bus domain includes at least one microprocessor core, and the peripheral module bus domain includes at least one global time-management module as well as modules for communication with the outside world and for signal processing. The companion chip further includes at least one FIFO module for transmitting data within the chip, and between the chip and the microcontroller, and a management module connected to the FIFO module, which ensures the consistency of the data by associating a respective time value and/or an angle of rotation.

Abstract: A multi-mode parallel graphics rendering and display system supporting real-time graphics rendering and display operations using a graphics hub device. The system includes a CPU memory space, one or more CPUs for executing graphics-based applications, and a multi-mode parallel graphics rendering system (MPGRS) supporting multiple modes of parallel operation including object division, image division, and time division. The MMPGRS includes a plurality of graphic processing pipelines (GPPLs) that support a parallel graphics rendering process employing one or more modes of parallel operation.

Abstract: A data processing apparatus and method are provided for processing data under control of a program having program instructions including sequences of individual program instructions corresponding to computational subgraphs identified within the program. Each computational subgraph has a number of input operands and produces one or more output operands. The apparatus comprises an operand store for storing the input and output operands, and processing logic for executing individual program instructions from the program. Also provided is configurable accelerator logic which, in response to reaching an execution point within the program corresponding to a sequence of individual program instructions corresponding to a computational subgraph, evaluates one or more output functions associated with the computational subgraph.

Abstract: A storage unit retains processing target data, a data processing circuit processes the data retained in the storage unit, a connection unit is connected to a processing device that executes a computer program, and a control unit invalidates, when a predetermined condition is detected, the data processing by the data processing circuit and requests a processing device connected to the connection unit for the data processing.

Abstract: A system and method for processing data is disclosed. In one embodiment, a data moving processor comprises a code memory coupled to a code fetch circuit and a decode circuit coupled to the code fetch circuit. An address stack is coupled to the decode circuit and configured to store address data. A general purpose stack is coupled to the decode circuit and configured to store other data. The data moving processor uses data from the general purpose stack to perform calculations. The data moving processor uses address data from the address stack to identify source and destination memory locations. The address data may be used to drive an address line of a memory during a read or write operation. The address stack and general purpose stack are separately controlled using bytecode.

Abstract: A system includes an abstract machine instruction stream, an execution trace buffer storing information to facilitate dynamic compilation, a virtual machine coprocessor configured to receive an instruction from the abstract machine instruction stream and to generate one or more native machine instructions in response to the received instruction, and a processor coupled to the virtual machine coprocessor and operable to execute the native machine instructions generated by the virtual machine coprocessor. The virtual machine coprocessor updates the execution trace buffer as instructions from the abstract machine instruction stream are processed. In addition, a method for facilitating dynamic compilation includes receiving an instruction to be processed, determining that the instruction marks entry into a basic block, and updating an execution trace buffer.

Abstract: In a multiprocessor system, a task control processor may be placed in the path connecting each execution processor to a system bus. Such task control processors may detect the completion of a first task on an associated execution processor and, responsively, generate commands to lead to the initiation of a second task on the same, or another, execution processor. Such task completion detection and task initiation by the task control processors removes, from a central processor or the execution processors, the burden of performing such tasks, thereby improving the efficiency of the entire system.

Abstract: A processor unit and a coprocessor unit are disclosed. In one embodiment, the processor unit includes a functional unit that receives a set of instructions in an instruction stream and provides the set of instructions to the coprocessor unit. The coprocessor executes the instructions and initiates transmission of a set of execution results corresponding to the set of instructions to the processor unit's functional unit. The processor functional unit may be coupled to the coprocessor unit through a shared bus circuit implementing a packet-based protocol. The processor unit and the coprocessor unit may share a coherent view of system memory. In various embodiments, the functional unit may alter entries in a translation lookaside buffer (TLB) located in the coprocessor unit, resume and suspend a thread executing on the coprocessor unit, etc.

Abstract: A method of providing physics data within a game program or simulation using a hardware-based physics processing unit having unique architecture designed to efficiently calculate physics related data.

Abstract: The present invention provides a configurable domain specific abstract core (DSAC) for implementing applications within any domain. The DSAC comprises at least one function specific abstract module (FSAM) configurable at a plurality of stages for implementing a predetermined function belonging to one or more applications in the domain. The FSAM comprises a function specific abstract logic (FSAL) for implementing functional logic and a micro state engine (MSE) for generating and monitoring one or more control signals, at least one of the control signals being generated by execution of a dynamic script for controlling the FSAL.

Abstract: A system for limiting the size of a local storage of a processor is provided. A facility is provided in association with a processor for setting a local storage size limit. This facility is a privileged facility and can only be accessed by the operating system running on a control processor in the multiprocessor system or the associated processor itself. The operating system sets the value stored in the local storage limit register when the operating system initializes a context switch in the processor. When the processor accesses the local storage using a request address, the local storage address corresponding to the request address is compared against the local storage limit size value in order to determine if the local storage address, or a modulo of the local storage address, is used to access the local storage.

Abstract: One embodiment of the present includes a heterogenous, high-performance, scalable processor having at least one W-type sub-processor capable of processing W bits in parallel, W being an integer value, at least one N-type sub-processor capable of processing N bits in parallel, N being an integer value smaller than W by a factor of two. The processor further includes a shared bus coupling the at least one W-type sub-processor and at least one N-type sub-processor and memory shared coupled to the at least one W-type sub-processor and the at least one N-type sub-processor, wherein the W-type sub-processor rearranges memory to accommodate execution of applications allowing for fast operations.

Abstract: A device may include a data processing logic cell field and one or more sequential CPUs. The logic cell field and the CPUs may be configured to be coupled to each other for data exchange. The data exchange may be in block form using lines leading to a cache memory. In a method for operating a reconfigurable unit having runtime-limited configurations, the configurations may be able to increase their maximum allowed runtime, e.g., by triggering a parallel counter. An increase in configuration runtime by the configurations may be suppressed in response to an interrupt.

Abstract: A co-processor is provided that comprises one or more application engines that can be dynamically configured to a desired personality. For instance, the application engines may be dynamically configured to any of a plurality of different vector processing instruction sets, such as a single-precision vector processing instruction set and a double-precision vector processing instruction set. The co-processor further comprises a common infrastructure that is common across all of the different personalities, such as an instruction decode infrastructure, memory management infrastructure, system interface infrastructure, and/or scalar processing unit (that has a base set of instructions). Thus, the personality of the co-processor can be dynamically modified (by reconfiguring one or more application engines of the co-processor), while the common infrastructure of the co-processor remains consistent across the various personalities.

Abstract: An information-processing device that executes a specific process more frequently than other processes among a variety of processes is provided. The information-processing device includes a first processor capable of executing an instruction set corresponding to the variety of processes, and a second processor capable of executing a portion of or the entire instruction set, the second processor being capable of executing a part of the instruction set corresponding to the specific process more efficiently than the first processor, wherein the second processor executes the specific process whereas the first processor executes the other processes. Accordingly, the information-processing device can execute a variety of instructions efficiently.

Abstract: Disclosed is a method for processing multimedia data at a mobile communication terminal having at least one sub processor besides a main processor, including the steps of analyzing information of multimedia data to be processed at the main processor, selecting a processor at the main processor for processing the multimedia data according to analyzed result of the information, calling codec needed for the data processing at the selected processor, and processing the multimedia data at the selected processor by using the called codec.

Abstract: A method for reducing electromagnetic emissions in an electronic device having a multiple micro-controllers includes identifying the number of micro-controllers installed in the electronic device. An operating frequency range of the electronic device is determined based on the operating frequency range of each micro-controller. A frequency spacing for each micro-controller within the operating frequency range of the electronic device is then calculated, and an operating frequency is assigned to each micro-controller. The operating frequency of each micro-controller is separated from the operating frequency of each other micro-controller by at least the frequency spacing. Then, the operating frequency of each micro-controller is set at the assigned operating frequency.

Abstract: A configurable coprocessor interface between a central processing unit (CPU) and a coprocessor is provided. The coprocessor interface has an instruction transfer signal group for transferring different instruction types from the CPU to the coprocessor, sequentially or in parallel, a busy signal group, for allowing the coprocessor to signal the CPU that it cannot receive a transfer of one or more of the different instruction types, and an instruction order signal group for indicating to the coprocessor a relative execution order for multiple instructions that are transferred in parallel. In addition, the coprocessor interface includes separate data transfer signal groups for data being transferred from the CPU to the coprocessor, and for data being transferred from the coprocessor to the CPU, along with a data order signal group for indicating a relative order of data (if transferred out-of-order).

Abstract: In accordance with exemplary implementations, application computation operations and communications between operations on a host processing platform may be adapted to conform to the memory capacity of a parallel accelerator. Computation operations may be split and scheduled such that the computation operations fit within the memory capacity of the accelerator. Further, the operations may be automatically adapted without any modification to the code of an application. In addition, data transfers between a host processing platform and the parallel accelerator may be minimized in accordance with exemplary aspects of the present principles to improve processing performance.

Abstract: A system comprises a master processor and at least one slave processor. A state of the master processor comprises a first plurality of variables and a state of the slave processor comprises a second plurality of variables. The system comprises a parallel mode of operation wherein data are processed by the master processor and the slave processor and a serial mode of operation wherein data are processed by the master processor. In case of an interrupt or exception occurring in the parallel mode of operation, the system performs the steps of saving at least a portion of the first plurality of variables and the second plurality of variables to a buffer memory and switching the system to the serial mode of operation. If the interrupt or exception is occurring in the slave processor, at least one of the first plurality of variables is set to a value of at least one of the second plurality of variables.

Abstract: A circuit to detect position signals in a mobile station includes a general-purpose processor to generate instructions for execution of at least one signal detection algorithm and to carry out at least one other function not associated with the signal detection algorithm, special-purpose hardware blocks responsive to the instructions of the general-purpose processor to execute the at least one signal detection algorithm, and at least one of the general-purpose processor and the special-purpose hardware blocks configured to execute at least one efficiency process to optimize performance of the at least one signal detection algorithm. Methods and machine-readable medium implementing the method steps are also disclosed.

Abstract: The invention includes an apparatus and the associated method to digitally process data communicated through a communication channel between a transceiver pair. A global control element and programmable algorithm control elements are used to implement an algorithm using a datapath. The control signal outputs of at least one programmable algorithm control element are coupled to the datapath. The datapath may use the control signals to drive transmission data down a computation path that implements the desired algorithm. The datapath may be duplicated to meet the requirements of a particular device and operate on a larger subset of data using the same control signals that are provided by the programmable algorithm control elements.

Abstract: An apparatus is provided for processing data under control of a program having program instructions and subgraph suggestion information identifying respective sequences of program instructions corresponding to computational subgraphs identified within the program. A memory stores a program formed of separate program instructions. Processing logic executes respective separate program instructions from said program. Accelerator logic, in response to reaching an execution point within the program associated with a subgraph suggestion, executes a sequence of program instructions corresponding to the subgraph suggestion as an accelerated operation instead of executing the sequence of program instructions as respective separate program instructions with the processing logic.

Abstract: An array type processor comprises a data path unit to execute processing, and a state management unit to control the state of the data path unit in accordance with a command that specifies processing on the data. An input DMA circuit reads from a memory information and data to be processed including a command corresponding to the data. The input DMA circuit first transfers the command to the state management unit, and then transfers the data to be processed to the data path unit.

Abstract: Method and apparatus for communication between hardware blocks and a processor in a programmable logic device is described. A shared memory is provided along with a memory controller for controlling access to the shared memory. An interface is configured to receive auxiliary instructions from the processor, select the hardware blocks for the requested tasks in response to the auxiliary instructions, notify the hardware blocks of those tasks, and arbitrate access to the memory controller among the hardware blocks.

Abstract: Methods and apparatus for calculating Single-Instruction-Multiple-Data (SIMD) complex arithmetic. A coprocessor instruction has a format identifying a multiply and subtract instruction to generate real components for complex multiplication of first operand complex data and corresponding second operand complex data, a cross multiply and add instruction to generate imaginary components for complex multiplication of the first operand complex data and the corresponding second operand complex data, an add-subtract instruction to add real components of the first operand to imaginary components of the second operand and to subtract real components of the second operand from imaginary components of the first operand, and a subtract-add instruction to subtract the imaginary components of the second operand from the real components of the first operand and to add the real components of the second operand to the imaginary components of the first operand.

Abstract: A single-instruction multiple-data processor comprises at least two multiply-accumulator units and associated coefficient memories and data memories. Coefficient memory addresses are formed from a base address and data samples stored in the data memories.

Abstract: A processor includes a coprocessor interface unit that couples a coprocessor that executes instructions in-program order to an execution unit that executes instructions out-of-program order. The coprocessor interface unit includes a coprocessor store data queue. If data stored in a register of the coprocessor is to be stored in a register file of the execution unit, the data is transferred from the coprocessor to the coprocessor store data queue. A graduation unit coupled to the coprocessor is also provided. The graduation unit provides a signal to the coprocessor that determines whether an instruction executed by the coprocessor is permitted to alter an architectural state of the processor.

Abstract: The present invention provides an equalizer processing module within a wireless terminal having an equalizer interface that receives an incoming baseband signal from a baseband processor operably coupled to the equalizer processing module and outputs soft decisions. A processor or advanced reduced instruction set computer (RISC) machine (ARM) couples to the equalizer interface while an equalizer accelerator module operably couples to the processor or ARM. Processing of the incoming baseband signal to produce soft decisions is performed by the combination of the processor and equalizer accelerator module. A sample capture buffer and an equalizer output buffer which may or may not be within the equalizer processing module allow data to be sampled and serves as the input and output for the equalizer processing module. This equalizer accelerator may specifically perform compute intensive operations such as Trellis computations for MAP equalization or MLSE equalization.

Abstract: The present invention provides a data processing apparatus realizing reduced load on a host CPU and improved performance. An arithmetic unit includes an SIMD processor for processing a plurality of pieces of data by a single instruction, and a second CPU coupled to the SIMD processor via an arithmetic unit bus and controlling the SIMD processor. A host system includes a host CPU for controlling the entire data processing apparatus, a built-in memory and a peripheral circuit coupled to the host CPU via a first bus, and a peripheral circuit coupled to a second bus. The second CPU accesses an external flash/ROM via the arithmetic unit bus and the first bus, and the SIMD processor accesses an external memory via the second bus. Therefore, the load on the host CPU can be reduced, and the performance of the entire apparatus can be improved.

Abstract: A processor for processing data is provided. The processor comprises an address generator, which is operative to generate an address based on a base address and a fractional step (?).

Abstract: A system and method for accelerated processing of streams of dependent instructions, such as those encountered in the G.726 codec, in a microprocessor or microprocessor-based system/chip. In a preferred implementation, a small RISC-like special purpose processor is implemented within a larger general purpose processor for handling the streams of dependent instructions.

Abstract: In the host, an IP issues CCW, and a CH encodes the CCW and a CCW chain by the encode program to create a code including the description of controlling a conditional branch with the DKC and transmits the code to a PORT in the DKC. In the DKC, the PORT decodes the code by the decode program, and a CP sequentially processes each command obtained by the decoding and returns a return code representing the end state of the processing. The host receives the return code to recognize the end state of the processing.

Abstract: An abstraction layer is comprised in the operating system that represents the particulars of the PPMs. The abstractions in the abstraction layer are differentiated from one another by parameters representing the characteristics of the PPMs. The dispatcher uses the abstraction to balance processing loads when assigning execution threads to the PPMs. The assigning of the execution threads and the balancing of the processing loads is performed while taking account of the characteristics of the PPMs, such as shared resources and clock speed.

Abstract: A method and apparatus for processing data received and transmitted on a TCP connection is described. An offload unit processes received data for which a special case does not exist, to produce payload data, which is uploaded directly to application memory. The offload unit partially processes received data for which a special case does exist and uploads the partially processed received data to a buffer stored in system memory. The partially processed received data is then further processed by a TCP stack to produce payload data, which is copied to application memory.

Abstract: An information processing apparatus having a multi-processor unit including a plurality of processors. The multi-processor unit includes: a main-processor element including a main processor; and at least one sub-processor element having a sub-processor, a local memory corresponding to each of the processors, and a memory flow controller (MFC) executing data input from and data output to the local memory by DMA (Direct Memory Access), wherein the memory flow controller (MFC) inputs data from the outside of the multi-processor unit, stores the data into the local memory by DMA processing, and further outputs the data stored in the local memory to an external memory of the multi-processor unit or a device by DMA processing.

Abstract: A processor architecture supports an electrical interface for coupling the processor core to one or more coprocessor extension units executing computational instructions, with a split-instruction transaction employed to provide operands and instructions to an extension unit and retrieve results from the extension unit. The generic instructions for sending an operation and data to the extension unit and/or retrieving data from the extension unit allow new computational instructions to be introduced without regeneration of the processor architecture. Support for multiple extension units and/or multiple execution pipes within each extension unit, multi-cycle execution latencies and different execution latencies between or within extension units, extension unit instruction predicates, and for handling processor core stalls and result save/restore on interrupt is included.