Abstract: The invention relates to exchangeable memory or PC-cards with several integrated circuits for personal computers. These PC-cards are used as a large capacity mass memory for replacing floppy disks and other exchangeable magnetic supports. To protect the content of these PC-cards against unauthorized use, the invention proposes the incorporation into the card (CC) of a specific security integrated circuit chip (MPS), which performs a clearance function for access to the memory chips (MEM). A microcontroller (MPC) also placed in the card communicates with the computer and with the security circuit. It makes the security chip validate a confidential code introduced from the computer, while also supplying memory chip control signals as a function of the validation result.

Abstract: In the CIS installation area of a PC card, the A region contains the basic attribute information of the card, the B region contains data of CIS1 for a modem, and the C region contains CIS2 for an ATA memory. The PC card is provided with a selection signal input means which selectively designates the CIS. A selection signal discriminator receives a signal from the selection signal input means and determines the selective designation of the CIS. When CIS1 and CIS2 are selectively designated together, a CIS switch setting element sets the start of the CIS read-in by a personal computer to the leading address of CIS1, and when CIS2 only is selectively designated, it switchably sets the start of the CIS read-in by the personal computer to the leading address of CIS2.

Abstract: To accelerate read operations, or the operations that modify the operating parameters of a microcontroller, an interface is provided with three registers—an address register, an instruction and data register, and an auxiliary register. The instruction and data register supports the auxiliary register by indirect addressing. The address register is furthermore provided with an incrementation circuit mechanism for indirect incrementation. With the indirect addressing and the automatic incrementation, the number of external operations are reduced for continuous read or write operations.

Abstract: A CPU performs read access to a plurality of resources. A plurality of buffers connect the plurality of resources to the CPU, respectively. The CPU causes one of the plurality of buffers connected to one of the plurality of resources to be in an active state so that the CPU can perform read access to the one of the plurality of resources via the one of the plurality of buffers, the one of the plurality of resources being given priority.

Abstract: A first memory of a large storage capacity is connected to a DQ pad for inputting and outputting an information signal through a bus interface unit. A first bidirectional transfer circuit and a second bidirectional transfer circuit for bidirectionally transmitting an information signal are provided between a high-speed memory and the memory of the large storage capacity. The first bidirectional transfer circuit is connected with the large storage capacity memory through a common bus, and the high-speed memory is interconnected with the second transfer circuit through a fifth bus. This second bidirectional transfer circuit is connected to an instruction register and a data register through a sixth bus. A processor is arranged in proximity to this instruction register and the data register, so that the processor processes an instruction from the instruction register and data from the data register and stores a processing result in the data register again.

Abstract: An electronic system and a processing unit supporting a flexible microcode space and Basic Input/Output System (BIOS) space. The electronic system features a first circuit board having a connector interconnected to a processing unit. The processing unit includes a second circuit board having an embedded controller and an on-substrate memory. The non-substrate memory is coupled to the embedded controller via a communication line routed through or placed on the second circuit board. In one embodiment, during a boot procedure and upon executing an instruction requesting data to be obtained from the on-substrate memory, the embedded controller obtains at least one microcode instruction from the on-substrate memory via the communication line.

Abstract: On a microprocessor chip mounting a central processing unit (CPU) for controlling the entire operation of electronic equipment and a digital signal processor (DSP) for processing a specific signal in the electronic equipment, an instruction cache for temporarily storing a DSP program and a cache controller are additionally mounted, and the DSP program and a CPU program are stored in an externally provided instruction memory. The cache controller controls the DSP to wait and interrupts the CPU when a cache miss occurs. The CPU executes a predetermined interrupt processing routine so as to supplement an instruction block including the instruction code from the instruction memory to the instruction cache. Thus, an on-chip memory used for storing instruction codes to be decoded and executed by the DSP can be reduced.

Abstract: A single chip integrated circuit device includes a bus system for effecting communication of parallel data on chip, functional circuitry connected to the bus system for executing an operation in response to parallel data received from the bus system, an external port, and a serial to parallel data packet converter interconnecting the parallel bus system and the external port. The external port includes a serial data input connector and a serial data output connector for supplying serial data packets between an external device and the integrated circuit device. The serial data packets each include a packet identifier indicating the length of the data packet and information defining an operation to be executed by the functional circuitry.

Abstract: A microcomputer has a first external terminal for receiving an external control signal that indicates a test mode of peripheral circuits, and a second external terminal connected to a data bus. A CPU of the microcomputer provides a bus control signal in response to the external control signal passed through the first external terminal, to write data passed through the second external terminal into the peripheral circuits. Upon receiving the external control signal, a bus controller of the CPU stops a bus cycle requested by an execution controller of the CPU and starts a bus cycle requested by the external control signal, to test the peripheral circuits.

Abstract: A memory request protocol allows a memory request to be withdrawn or "cancelled" without penalty so no memory resource is wasted in doing so during an assigned "cancel window". When the memory card starts to process a command from the memory controller, for a predefined number of cycles a period of time is available where the memory card can't accept another command due to a resource conflict. This provides an opportunity to re-balance requests to the memory controller in this period of time or "cancel window".

Abstract: A computer system includes first and second integrated circuits. The first integrated circuit provides a first input/output bus operating in accordance with a first protocol, such as ISA. The first input/output bus includes a plurality of address and data lines respectively providing address and data information. The second integrated circuit includes a plurality of second functional blocks at least some of which interface to legacy devices. The first integrated circuit includes a host controller circuit, coupled to the first input/output bus and for coupling to a register access bus which includes a register data out and a register data in signal line. The register access bus connects the first and second integrated circuits. The host controller circuit receives address and data information from the input/output bus and serially provides the address and data information to the data out line. A target controller circuit on the second integrated circuit is coupled to the register access bus.

Abstract: A processor architecture scheme which allows for encoding multiple addressing modes and which has multiple sources for generating a bank address value. The processor architecture scheme has a Central Processing Unit (CPU) for executing an instruction set. A data memory is coupled to the CPU. The data memory is used for storing and transferring data to and from the CPU. The data memory is divided into a plurality of banks wherein one of the plurality of banks is a dedicated bank for general and special purpose registers. A selection circuit is coupled to the data memory. The selection circuit is used for selecting one of the multiple sources for generating the bank address value. A bank select register is coupled to the selection circuit. The bank select register is used for supplying a bank address value for an instruction to be executed in a direct short addressing mode.

Abstract: To improve the efficiency of delayed transactions in bus-to-bus bridge systems which include at least one interface to a PCI bus, a bridge system is disclosed including at least a primary interface and an interface to a secondary subsystem for interconnecting a primary PCI bus system and the secondary subsystem. The system comprises a delayed transaction mechanism for enabling a transaction source attached to the primary PCI bus system to effect delayed transactions with a target in the secondary subsystem. This system has a programmable delay transaction timer which provides a degree of flexibility in the configuration of PCI systems. This flexibility can be exploited to provide considerable efficiency gains, albeit at the expense of some deviation of the strict requirements of the PCI Specification.

Abstract: A communication control device has a central processing unit (3), an input data buffer (14), an output data buffer (15), a readout reload register (17), an output reload register (18), and a timer (19) located between an input terminal (1) and an output terminal (2). The timer (19) reads count values stored in both the reload registers (17, 18) alternately, that have already been set by the central processing unit (3) according to a protocol to be processed, and performs a counting operation based on the count values. Communication data items stored in both the data buffers (14, 15) are latched based on a time out output from the timer (19).

Abstract: An information processor comprises a program storage unit and a control unit, the control unit includes a procedure insertion table in which information regarding an embedding point in a program and information regarding an insertion procedure to be inserted in the embedding point are described in correlation with each other, and a program dynamically changing unit for saving an instruction at an embedding point of the program held in the program storage unit in a predetermined instruction saving region with reference to the procedure insertion table, rewriting the last instruction of an insertion procedure into a branch instruction to branch to an instruction subsequent to a saved instruction, and writing the branch instruction to branch to the insertion procedure at the embedding point, thereby, at the time of execution of the insertion procedure, executing the instruction saved in the instruction saving region immediately before executing the last branch instruction.

Abstract: A processor performs data transactions. For a first data transfer between the processor and a first external device which uses non-multiplexed data transactions, a first address is placed on an (external) address bus and first data is transferred on an (external) address/data bus. A second data transaction is performed between the processor and a second external device which uses multiplexed data transactions. In an address phase of the second data transaction, a second address is placed on the address/data bus. In a data phase of the second transaction, second data is transferred on the address/data bus.

Abstract: A memory access method in a microcomputer for a CPU to fetch an instruction code from a memory when an instruction queue buffer does not contain the instruction code, comprising the steps of fetching the instruction code from a high-speed memory directly to the CPU, if the instruction code is in the high speed memory, or fetching the instruction code from a low-speed memory to the instruction queue buffer, if the instruction code is in the low-speed memory, then fetching the instruction code from the instruction queue buffer to the CPU.