Abstract: A method and system for moving data from a source memory to a destination memory by a processor is disclosed herein. The destination memory stores a sequence of instructions and the sequence of instructions comprises one or more load instructions and one or more store instructions. The processor initially moves the one or more store instructions from the destination memory to the source memory. The processor then executes the one or more load instructions from the destination memory. On executing the one or more load instructions, the data is loaded from the source memory to at least one register in the processor. The processor further initiates execution of the one or more store instructions stored in the source memory. On executing the one or more store instructions from the source memory, the processor stores the data from the at least one register to the destination memory.

Abstract: There is provides an operation module, which includes a memory, a register unit, a dependency relationship processing unit, an operation unit, and a control unit. The memory is configured to store a vector, the register unit is configured to store an extension instruction, and the control unit is configured to acquire and parse the extension instruction, so as to obtain a first operation instruction and a second operation instruction. An execution sequence of the first operation instruction and the second operation instruction can be determined, and an input vector of the first operation instruction can be read from the memory. The operation unit is configured to convert an expression mode of the input data index of the first operation instruction and to screen data, and to execute the first and second operation instruction according to the execution sequence, so as to obtain an extension instruction.

Abstract: A computer system is configured to: obtain, from each of a plurality of processing applications, a communication index for evaluating data transmission and reception performance of the each of the plurality of processing applications, the plurality of processing applications each being configured to: obtain data from a source object; execute predetermined processing on the data; and transmit a result of the processing to a destination object; calculate a link allowable value indicating processing performance of each of the plurality of processing applications based on the communication index; generate a transmission plan relating to an amount of data to be allocated to each of the plurality of processing applications based on the link allowable value; and control transmission of the data to each of the plurality of processing applications based on the transmission plan.

Abstract: Examples of the present disclosure provide apparatuses and methods for direct data transfer. An example method comprises transferring data between a first device and a second device, wherein the first device is a bit vector operation device, and transforming the data using a data transform engine (DTE) by rearranging the data to enable the data to be stored on the first device when transferring the data between the second device and first memory device.

Abstract: A communication system includes a central, zone ECUs capable of communicating with the central ECU via a communication bus, and zone ECUs capable of communicating with the central ECU via a communication bus. The central ECU periodically transmits, to the communication buses, a count signal including a count value counted up every time the count signal is transmitted, transmits a control signal including a start count value and control content to the communication buses, and sets a transmission priority of the count signal to be higher than a transmission priority of the control signal. The zone ECUs receive the count signal and the control signal, after the control signal is received, when the count value included in the received count signal becomes equal to the start count value included in the control signal, an operation corresponding to the control content included in the control signal is started.

Abstract: A processor and a method are disclosed that mitigate side channel attacks (SCAs) that exploit store-to-load forwarding operations. In one embodiment, the processor detects a translation context change from a first translation context (TC) to a second TC and responsively disallows store-to-load forwarding until all store instructions older than the TC change are committed. The TC comprises an address space identifier (ASID), a virtual machine identifier (VMID), a privilege mode (PM) or a combination of two or more of the ASID, VMID and PM, or a derivative thereof, such as a TC hash, TC generation value, or a RobID associated with the last TC-updating instruction. In other embodiments, TC generation values of load and store instructions are compared or RobIDs of the load and store instructions are compared with the RobID associated with the last TC-updating instruction. If the instructions' RobIDs straddle the TC boundary, store-to-load forwarding is not allowed.

Abstract: A method to be performed by a processor includes determining whether an application software has called an application programming interface, upon determination that the application software has called the application programming interface, determining whether one or more floating-point errors are recorded in a floating-point status register, and upon determination that one or more floating-point errors are recorded in the floating-point status register, performing a predefined action for each type of floating-point error recorded in the floating-point status register.

Abstract: An aspect of behavior of an embedded system may be determined by (a) determining a baseline behavior of the embedded system from a sequence of patterns in real-time digital measurements extracted from the embedded system; (b) extracting, while the embedded system is operating, real-time digital measurements from the embedded system; (c) extracting features from the real-time digital measurements extracted from the embedded system while the embedded system was operating; and (d) determining the aspect of the behavior of the embedded system by analyzing the extracted features with respect to features of the baseline behavior determined.

Abstract: Techniques are described herein for distributed data stream programming and processing. The techniques include sending a request indicating one or more regions of a program code to access a stream in a stream pool and to execute on a processing node in a processing nodes pool. The techniques also include accessing the stream defined in the one or more regions of the program code to service the request. Thereafter, the processing node is selected to use for execution of the one or more regions of the program code and the processing node executes one or more instances of the one or more regions of the program code.

Abstract: A system including a machine learning accelerator (MLA) hardware configured to perform machine-learning operations according to native instructions; an interpreter computing module configured to: generate, based on virtual instructions, machine language instructions configured to be processed by a processing hardware implementing the interpreter computing module; and cause the processing hardware to perform machine-learning operations according to the machine language instructions; and a compiler computing module associated with the MLA hardware, the compiler computing module configured to: receive instructions for performing an inference using a machine-learning model; based on the received instructions: generate the native instructions configured to be processed by the MLA hardware, the native instructions specifying first machine-learning operations associated with performing the inference; and generate the virtual instructions configured to be processed by the interpreter computing module, the virtual ins

Abstract: Disclosed embodiments include a method for combining a BATCH application programming interface (API) and a QUEUEABLE API on a SALESFORCE platform to process records. The method can include accessing a programming environment associated with an add-on application for a SALESFORCE platform, obtaining records via the add-on application to be processed on the SALESFORCE platform in accordance with a job type, calling a BATCH API to process the records by batching the records to create job records, and calling a QUEUEABLE API to process the job records in QUEUEABLES including parallel QUEUEABLES such that at least some job records included in the parallel QUEUEABLES are processed in parallel in accordance with the job type.

Abstract: Apparatuses, systems, and methods for hierarchical memory systems are described. A hierarchical memory system can leverage persistent memory to store data that is generally stored in a non-persistent memory, thereby increasing an amount of storage space allocated to a computing system at a lower cost than approaches that rely solely on non-persistent memory. An example method includes receiving a request to access data via an input/output (I/O) device, determining whether the data is stored in a non-persistent memory device or a persistent memory device, and redirecting the request to access the data to logic circuitry in response to determining that the data is stored in the persistent memory device.

Abstract: Nodes of a weighted tree each have their own weight. A normalized weight of a node, relative to other nodes in the tree, is determined based on a proportional weight of the node and a lesser unique sum of the node, as well as those of the node's parents and grandparents, up to a root of the tree. The proportional weight and lesser unique sum of a given node depend only on the unique weights of the sibling group including the given node. Thus, if a weight is modified, the normalized weight can be updated without necessarily recalculating the entire tree.

Abstract: The described methods and systems enable process control devices to transmit and receive device variable values in a manner that enables the receiving device to verify the integrity of the received values on a variable-by-variable basis. To facilitate verification of integrity, any desired number of variables in a message may have a data integrity check in the message. For each received value that has a data integrity check, the receiving device can calculate its own data integrity check based on the received value and a seed (known to both the transmitting and receiving devices), which it can then compare to the received data integrity check to verify if the received value has been altered during communication.

Abstract: An embodiment of a semiconductor package apparatus may include technology to generate a first output from a physically unclonable function (PUF) based on a challenge, modify the challenge based on the first output, and generate a response based on the modified challenge. Some embodiments may additionally or alternatively include technology to change a read sequence of the PUF based on an output of the PUF. Some embodiments may additionally or alternatively include technology to vary a latency of a linear feedback shift register based on an output from the PUF. Other embodiments are disclosed and claimed.

Abstract: Described herein are a processor and a method of operating the processor to simulate a many-core target machine. The processor includes a plurality of processing cores arranged in a predetermined manner and a global target clock counter (GTCC) configured to count a number of simulated clock cycles in the target machine. A global stall controller (GSC) configured to halt execution of all the processing cores based on a determination of at least one processing core being in a fault condition; and wherein the processor acquires a base clock per instruction (CPI) of a target machine, the CPI corresponding to an average number of clock cycles required by the target machine to execute a single instruction, translates an application of the target machine to a compact executable trace to be executed by the processor, and adjusts a speed of simulation by adjusting an update rate of the global target clock counter.

Abstract: A method for testing. The method includes sending a single instruction over a JTAG interface to a JTAG controller to select a first internal test data register of a plurality of data registers. The method includes programming the first internal test data register using the JTAG interface to configure mode control access and state control access for a test controller implementing a sequential scan architecture to test a chip at a system level.

Abstract: Exemplary systems, methods and computer-readable mediums can assign, from the circuit, at least two scan cells as at least two interface registers, and generate at least one bidirectional scan path between the at least two interface registers of the at least one portion of the circuit. The at least two interface registers can be disposed in neighboring positions, and the assigning can include a partitioning procedure that can iteratively merge the scan cells of the at least one portion of the circuit into a plurality of regions.

Abstract: A method for delocalizing an error checking on a data in a pipelined processor from the data checked. A first check-data is generated at a first location on a first data. A second location receives the first data and the first check-data. A second check-data is generated on the first data and the first check-data is compared with the second check-data at the second location. A second data is generated from the first data and a third check-data is generated on the second data at the second location. A third check-data is generated on the second data at the second location and the second data is transferred to a third location. The third check-data is transferred to a fourth location. A fourth check-data is generated on the second data and is transferred to the fourth location. The fourth check-data and the third check-data are compared at the fourth location.

Abstract: The present patent document relates to a method to compact trace data generated by emulation processors during emulation of a circuit design, and a hardware functional verification system that compacts trace data. Compaction logic within emulation processor clusters accumulated data bits output from the emulation processors and compacts them into trace data bytes in registers based on enable bits identifying valid trace data according to a compaction scheme. Trace data bytes are further accumulated and compacted into larger trace data bytes in higher level processor clusters of the emulation chip according to a compaction hierarchy, with the compacted trace data bytes stored into a trace array of the emulation chip.

Abstract: A computing machine is disclosed having a memory system for storing a collection of execution nodes, a head for reading a sequence of symbols in the execution nodes in the memory system, and writing a sequence of symbols in the memory system. The machine is configured to execute a computation with a collection of pairs of execution nodes. Each pair of execution nodes represents a machine instruction. One execution node in the pair represents input of the machine instruction represented by the execution nodes. Another execution node in the pair represents output of the machine instruction represented by the execution nodes. Each execution node has a state of the machine, a sequence of symbols and a number.

Abstract: A data processing apparatus includes multiple processing means that are connected in a ring shape via corresponding communication means respectively. Each communication means includes a reception means for receiving data from a previous communication means, and a transmission means for transmitting data to a next communication means. Connection information is assigned to each of the reception means and the transmission means. The communication means, when receiving a packet that has same connection information as one assigned to its reception means, causes the corresponding processing means to perform data processing on the packet, sets the connection information assigned to its transmission means to the packet, and transmits the packet to the next communication means, and when receiving a packet that has connection information that is not same as one assigned to its reception means, transmits the packet to the next communication means without changing the connection information of the packet.

Abstract: A packet processor implemented in hardware. The packet processor includes a processing pipeline including a plurality of processing elements. The plurality of processing elements are configured to process a first data packet transferred sequentially through the plurality of processing elements. The first data packet includes information indicating a period of time that at least a first processing element of the plurality of processing elements uses to process the first data packet. The first processing element is prevented from processing other data packets due to performing processing on the first data packet during the period of time. A packet rate shaper is configured to, prior to the first data packet entering the processing pipeline, read the information in the first data packet, selectively increment and decrement a token value, and selectively grant the first data packet access to the processing pipeline based on the information and based on the token value.

Abstract: Technologies are generally described herein for determining a profitability of direct fetching in a multicore processor. The multicore processor may include a first and a second tile. The first tile may include a first core and a first cache. The second tile may include a second core, a second cache, and a fetch location pointer register (FLPR). The multicore processor may migrate a thread executing on the first core to the second core. The multicore processor may store a location of the first cache in the FLPR. The multicore processor may execute the thread on the second core. The multicore processor may identify a cache miss for a block in the second cache. The multicore processor may determine whether a profitability of direct fetching of the block indicates direct fetching or directory-based fetching. The multicore processor may perform direct fetching or directory-based fetching based on the determination.

Abstract: A multiprocessor system maintains cache coherence among processors in a coherent domain. Within the coherent domain, a first processor can receive a command to perform a cache maintenance operation. The first processor can determine whether the cache maintenance operation is a coherent operation. For coherent operations, the first processor sends a coherent request message for distribution to other processors in the coherent domain and can cancel execution of the cache maintenance operation pending receipt of intervention messages corresponding to the coherent request. The intervention messages can reflect a global ordering of coherence traffic in the multiprocessor system and can include instructions for maintaining a data cache and an instruction cache of the first processor. Cache maintenance operations that are determined to be non-coherent can be executed at the first processor without sending the coherent request.

Abstract: A device and a method for fetching instructions. The device includes a processor adapted to execute instructions; a high level memory unit adapted to store instructions; a direct memory access (DMA) controller that is controlled by the processor; an instruction cache that includes a first input port and a second input port; wherein the instruction cache is adapted to provide instructions to the processor in response to read requests that are generated by the processor and received via the first input port; wherein the instruction cache is further adapted to fetch instructions from a high level memory unit in response to read requests, generated by the DMA controller and received via the second input port.

Abstract: A data processing device and method are provided. The data processing device includes a code storage unit storing an original code to be translated into a machine language code, a code analyzer analyzing the original code stored in the code storage unit, a register allocator allocating a predesignated register for a command included in the original code based on the result of analysis, and a code executor executing a machine language code generated using the allocated register.

Abstract: Systems and methods for implementing a zero overhead loop in a microprocessor or microprocessor based system/chip are disclosed. The systems and methods include the use of a breakpoint mechanism, and modification of parameters at runtime, with the breakpoint mechanism being additionally used in debugging, in order to provide some of the looping functionality.

Abstract: Systems and methods for implementing a zero overhead loop in a microprocessor or microprocessor based system/chip are disclosed. The systems and methods include the use of a breakpoint mechanism which is additionally used in debugging in order to provide some of the looping functionality.

Abstract: An instruction preload instruction executed in a first processor instruction set operating mode is operative to correctly preload instructions in a different, second instruction set. The instructions are pre-decoded according to the second instruction set encoding in response to an instruction set preload indicator (ISPI). In various embodiments, the ISPI may be set prior to executing the preload instruction, or may comprise part of the preload instruction or the preload target address.