Abstract: A power switching circuitry and ethernet apparatus using the same is provided. The power switching circuitry comprises an external power socket for receiving external power, an ethernet power supply pin for receiving power over ethernet, a sensing circuitry, and a power output decision module, and determines whether the power over ethernet is applied to an internal circuit in accordance with position variations of the socket pins of the external power socket.

Abstract: Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. For example, an integrated circuit device may be configured to execute instructions with matrix operands and configured with random access memory that includes multiple memory groups having independent power modes. The random access memory is configured to store data representative of parameters of an Artificial Neural Network and representative of instructions executable by the Deep Learning Accelerator to perform matrix computation to generate an output of the Artificial Neural Network. During execution of the instructions, a power manager may adjust grouping of memory addresses mapped into the memory groups and adjust power modes of the memory groups to reduce power consumption and to avoid performance impact.

Abstract: A device capable of self-detecting and self-allocating additional power and associated method are disclosed. The device includes a first module to route current from first power pins to a voltage rail having the first voltage level. The device includes a second module coupled to second power pins associated with a second voltage level. The second module routes current from the second power pins to the voltage rail having the first voltage level via a connecting voltage rail. The method includes determining, by the device, whether or not a presence of unused power pins is detected. Based on the detection, the method includes calculating a total amount of available additional power, repurposing the unused power pins as actively used power pins, and updating a power budget value based on the total amount of available additional power. The device may dynamically allocate power to accelerators based on a power allocation table and the power budget value.

Abstract: Various embodiments may include methods and systems for power management of multiple chiplets within a system-on-a-chip (SoC). Various systems may include a power management integrated circuit (PMIC) configured to supply power to a first chiplet and a second chiplet across a shared power rail. The first chiplet may be configured to obtain first sensory information throughout the first chiplet. The second chiplet may be configured to obtain second sensory information throughout the second chiplet, and may be configured to transmit a voltage change message to the first chiplet based on the second sensory information. The first chiplet may be configured to transmit a power rail adjustment message to the PMIC based on the first sensory information and the voltage change message. The PMIC may be configured to adjust the voltage of at least one of the first chiplet and the second chiplet.

Abstract: An electronic device is provided. The electronic device includes a battery, a power management integrated circuit (PMIC), that is electrically connected to the battery, adjusts at least part of power received from the battery, and outputs a controlled power, a processor electrically connected to the PMIC, at least one power sensor that is one of electrically connected between the battery and the PMIC and constitutes a part of the PMIC, and a control circuit electrically connected to the at least one power sensor. The control circuit acquires at least one of a current value and a power value input into the PMIC from the battery, determines whether at least one of the acquired current value and power value is greater than or equal to a threshold, and generates a first signal for controlling at least one of the PMIC and the processor, at least partially based on the determination.

Abstract: An electronic system has a plurality of power domains, and each domain includes a subset of one or more processor clusters, first memory, PMIC, and second memory. A plurality of power sensors are distributed on the electronic system and configured to collect a plurality of power samples from the power domains. A power management engine is configured to process the power samples based on locations of the corresponding power sensors to generate one or more power profiles and a plurality of power throttling thresholds. The power manage engine is configured to implement a global power control operation by determining power budgets of the power domains on a firmware level and enabling operations of the power domains accordingly. The power manage engine is also configured to enable a plurality of local power control operations to be directly implemented on the power domains based on the power throttling thresholds.

Abstract: A method for analyzing power quality events in an electrical system includes processing electrical measurement data from or derived from energy-related signals captured by at least one of a plurality of metering devices in the electrical system to generate or update a plurality of dynamic tolerance curves. Each of the plurality of dynamic tolerance curves characterizes a response characteristic of the electrical system at a respective metering point of a plurality of metering points in the electrical system. Power quality data from the plurality of dynamic tolerance curves is selectively aggregated to analyze power quality events in the electrical system.

Abstract: Devices and techniques are disclosed herein to control recovery of a memory device from a reduced power state. A memory controller can include a detection circuit configured to monitor the power supply voltage to an array of memory cells during the reduced power state. Control circuitry an initialization procedure for recovery of the memory device from the reduced power state, based on the state of the detection circuit.

Abstract: A terminal software upgrade method can be applied to a terminal that is installed with a near-field communication sensing circuit. The terminal software upgrade method can include: in response to a distance between a near-field communication instruction writing circuit and the terminal reaching an effective communication distance of a near-field communication, writing instruction information sent by the near-field communication instruction writing circuit into the near-field communication sensing circuit, wherein the instruction information comprises at least boot-up instruction information and upgrade configuration information; and controlling the terminal to boot up via the near-field communication sensing circuit, based on the boot-up instruction information, and upgrading software of the terminal based on the upgrade configuration information.

Abstract: An information handling system includes a power supply unit having a power train configured to convert electrical energy received by the power supply unit into electrical energy usable by the information handling system and a microcontroller that includes non-volatile memory holding a line status register. The microcontroller is configured to set or reset the power supply unit for high line only operation, and the information handling system is configured to notify the power supply unit microcontroller to set or reset the power supply unit for high line only operation.

Abstract: A system, topology, and methods for multiplexing a plurality of POE ports at a POE switch via a single standard wired connection to the downstream where the multiplexed signals and power may be demultiplexed to a plurality of ports.

Abstract: A data storage system with multi-core processors dynamically enables and disables processor cores in order to manage power consumption while maintaining performance. One or more active processor cores are disabled responsive to determining that the current workload can be serviced with fewer active processor cores than are currently enabled while maintaining performance. One or more inactive processor cores are enabled responsive to determining that the current workload cannot be serviced with the currently active processor cores while maintaining performance. Separate utilization thresholds may be implemented for enabling inactive processor cores and disabling active processor cores to promote stability.

Abstract: Methods and systems for testing memory systems are disclosed. A refresh rate for a test system including a number of memory devices may be controlled based on estimated power scenario of a memory system design. In response to performance of a number of refresh operations on the memory devices and based on the refresh rate, one or more conditions of the test system may be monitored to generate estimated performance data for the memory system design.

Abstract: A universal serial bus (USB) dock includes USB ports, each configured to connect to a respective USB element. The USB dock includes a circuit communicatively coupled to the USB ports and configured to determine a first temperature measurement in the USB dock, determine a power demand for each USB element connected to the USB ports, determine an allocation of power for the USB elements, and, based on the first allocation of power, provide less than the power demand for one or more of the USB elements based upon a total power demand by the USB elements and the first temperature measurement.

Abstract: Embodiments of systems and methods for platform framework arbitration are described. In some embodiments, an Information Handling System (IHS) may include a processor and a memory coupled to the processor, the memory having program instructions stored thereon that, upon execution, cause the IHS to: provide, from a platform framework to an arbitration object via an Application Programming Interface (API), a plurality of runtime objects; receive, by the platform framework from the arbitration object via the API, an indication of an arbitration result with respect to the plurality of objects; and convey, from the platform framework to a participant via the API, the indication of the arbitration result.

Abstract: A system for controlling a fan is provided, which includes a processor, a driver, a power supply module, an instruction output module and a level control module. The power supply module is configured to supply power to the level control module when the server is started up and when the server is shut down. The instruction output module is configured to output a mode control instruction. The level control module is configured to output a first level to the PWM pin and output a second level to the TACH pin based on the mode control instruction and then control the power supply module to supply power to the processor and the driver. The processor is configured to determine a mode of the fan based on the first level and the second level and control a rotation speed of the fan based on the mode of the fan.

Abstract: A recording control apparatus configured to access a plurality of recording media, includes a control unit configured to set a temperature threshold of each of first and second recording media, a functional restriction being imposed on the recording medium at the temperature threshold, wherein the control unit is configured to, in recording data read from the first recording medium into the second recording medium, make a first setting for the first recording medium and a second setting for the second recording medium, where the first setting includes setting the temperature threshold of the recording medium at which the functional restriction is imposed on the recording medium to a default value of the recording medium, and the second setting includes setting the temperature threshold of the recording medium at which the functional restriction is imposed on the recording medium to a value greater than the default value of the recording medium.

Abstract: A power sequence in a power-delivery (PD) mechanism (interaction between host system components and a charger) and a firmware sequence during power contract negotiation reduces the host system power consumption at or below the pSnkStdby power limit to improve user experience and battery life. The power sequence uses USB Type-C PD protocol and timing specification to implement a synchronous trigger or interrupt and interface mechanism. The synchronous trigger or interrupt and interface mechanism between a PD controller and an embedded controller firmware controls the power consumption dynamically during the boot flow sequence to be less than or equal to pSnkStdby power limit while implementing a predictable boot sequence and optimizing boot time. The power negotiating sequence is also applicable when a source (e.g., a charger) is connected to a SoC host system which is in active state (e.g., S0) and when there is an indication of low battery capacity.

Abstract: A master-slave interchangeable power supply device, a power supply method, a host with the master-slave interchangeable power supply device, and a computer-readable storage medium for use in execution of the power supply method are provided. Upon receipt of a start command, a power control module and a power supply unit of the power supply device operate in a master mode and a slave mode respectively, and then the power supply device provides a working power to a master device to effect related configuration of the power supply device, so as to allow the power control module to switch to the slave mode and allow the working power to be provided to the master device. Therefore, given compliance with a specification of a communication bus, the power control module and the power supply unit, which function as peripheral devices, can perform a communicative function.

Abstract: A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.

Abstract: Platform power management includes boosting performance in a platform power boost mode or restricting performance to keep a power or temperature under a desired threshold in a platform power cap mode. Platform power management exploits the mutually exclusive nature of activities and the associated headroom created in a temperature and/or power budget of a server platform to boost performance of a particular component while also keeping temperature and/or power below a threshold or budget.

Abstract: Battery powered devices are provided with electrically isolated outputs. One exemplary battery device comprises at least one battery; and control electronics configured to provide a plurality of outputs from one of the at least one battery, wherein the plurality of outputs comprise at least one output that is electrically isolated from at least one other output of the plurality of outputs that each provide power to one or more of a plurality of loads. In another exemplary battery device, the control electronics are configured to provide a plurality of outputs from one of the at least one battery, and further comprises a housing assembly comprising (i) at least two surfaces, wherein the at least two surfaces have a space therebetween configured to house the control electronics and the at least one battery; or (ii) a tubular structure configured to house the control electronics and the at least one battery.

Abstract: Controlling server power usage in a data center is provided. Power usage among a plurality of server racks in active mode processing a set of workloads in the data center is managed. It is detected that a new server rack in standby mode is being added to the plurality of server racks. It is ensured that the new server rack in the standby mode is properly controlled and monitored prior to transitioning the new server rack to the active mode. It is determined whether power safety criteria are met to safely join the new server rack to the plurality of server racks prior to transitioning the new server rack from the standby mode to the active mode. The new server rack is transitioned to the active mode in without exceeding a power budget for the plurality of server racks in response to determining that the power safety criteria are met.

Abstract: Application link scaling method, apparatus and system are provided. The method includes obtaining an application link, the application link being a path formed by at least two associated applications for a service scenario; determining information of target resources required by capacity scaling for all applications in the application link; allocating respective resources to the applications according to the information of the target resources; and generating instances for the applications to according the respective resources. From the perspective of services, the method performs capacity assessment for related applications on a link as a whole, and capacity scaling of the entire link, thus fully utilizing resources, and preventing the applications from being called by other applications which results in insufficient resources.

Abstract: The present invention discloses a series circuit and a computing device, including: a power supply terminal for providing voltage for a plurality of chips disposed on the computing device; a ground terminal disposed at one end of each of the plurality of chips relative to the power supply terminal; and a first connection line for separately connecting a first predetermined number of chips of the plurality of chips in series, wherein a communication line is connected between adjacent chips of the first predetermined number of chips, a portion of the communication line is connected to a target connection point, which is disposed on the first connection line and adapted to the adjacent chips, via a third connection line, and the voltage at the target connection point is greater than or equal to the minimum voltage required for communication between the adjacent chips.

Abstract: A power meter or other electrical device is provided having two independent and communicatively isolated Ethernet ports. The first Ethernet port is addressable by a first unique identifier and is configured for enabling full access to the power meter via an internal LAN. This enables a LAN operator to remotely access the power meter via the internal LAN for performing metering functions, such as full telemetry, control and programming. The second Ethernet port is addressable by a second unique identifier and is configured for being connected to the Internet. Since the second Ethernet port is communicatively isolated from the first Ethernet port, a user can access the power meter via the Internet, but cannot access the internal LAN by connecting to the power meter via the Internet.

Abstract: Memory devices might include a plurality of memory cell pairs each configured to be programmed to store a digit of data; and control circuitry configured to cause the memory device to compare the stored digit of data of each memory cell pair to a received digit of data, determine whether a match condition or a no-match condition is indicated between the stored digit of data of each memory cell pair and the received digit of data, and deem a match condition to be met between the received digit of data and the stored digits of data of the plurality of memory cell pairs in response to a match condition being determined for a majority of memory cell pairs of the plurality of memory cell pairs.

Abstract: Systems and methods are provided for controlling power down of an integrated dual rail memory circuit. The power down system is configured to power down the power rail for input and logic components (VDD) while maintaining power to the power rail for the memory cells (VDDM). The power down system includes two voltage rails, a clock generator, and a power detector for detecting the power on VDD. The power detector generates an isolated power signal when voltage on VDD is below a voltage threshold. The isolated power signal is configured to disable the clock generator and thus reduce dynamic power as the read/write cycle is not triggered during power down.

Abstract: A semiconductor integrated circuit includes a first circuit connected to a power supply line, a determination portion configured to determine whether a voltage drop in the power supply line affects an operation of the first circuit, and a power supply voltage control portion configured to control change of a power supply voltage value on the basis of a determination result of the determination portion.

Abstract: A computer-implemented method includes: learning, by a computer device, a delivery for response content in view of types of queries; awakening, by the computer device, in response to receiving an activation command; receiving, by the computer device, a query; determining, by the computer device, a context of the query; determining, by the computer device, a digestibility of a response to the query; and determining, by the computing device, to output a response to the query as one of an audio response, a displayed response, and an audio response and a displayed response to the user, wherein the determining is based on the learning, the determined context of the query, the determined digestibility of the response, and the preferences of the user for receiving the response.

Abstract: A Computational Digital Low Dropout (CDLDO) regulator is described that computes a required solution for regulating an output supply as opposed to traditional feedback controllers. The CDLDO regulator is Moore's Law friendly in that it can scale with technology nodes. For example, CDLDO regulator of some embodiments uses a digital approach to voltage regulation, which is orders of magnitude faster than traditional digital LDOs and enables regulation at GHz speeds, making fast dynamic DVFS a reality. The CDLDO also autonomously tunes out the effects of process-voltage-temperature (PVT) and other non-idealities making the settling time totally variation tolerant.

Abstract: Various systems and methods for adapting a computer based on user attentiveness are described herein. A system for attention-based gesture recognition includes processing circuitry to: access an image of a user, the user proximate to a computing device; determine, based on the image, whether user is attentive to the computing device; and selectively enable or disable a function of the computing device depending on whether the user is attentive.

Abstract: The disclosure describes artificial reality (AR) systems and techniques that enable hierarchical power management of multiple devices within a multi-device AR system. For example, a multi-device AR system includes a device comprising one of a peripheral device configured to generate artificial reality content for display or a head-mounted display unit (HMD) configured to output artificial reality content. The device comprises a System on a Chip (SoC) that includes a host subsystem and plurality of subsystems. Each subsystem includes a child energy processing unit configured to manage power states for the subsystem. The host subsystem includes a parent energy processing unit configured to direct power management of each of the child energy processing units of the plurality of subsystems.

Abstract: Hybrid wire-fiber data networks that include wire-fiber transceivers protected against environmental interferences. In some embodiments, a hybrid-wire-fiber data network of this disclosure provides a fiber-optic link between portions of one or more wired networks. In some embodiments, a hybrid wire-fiber data network of this disclosure includes a fiber-optic link that relies only on message-priority arbitration performed on wired portions of one or more wired networks. In some embodiments, a wire-fiber transceiver of this disclosure includes electromagnetic environment (EME) protective circuitry for one or both of input power and input signals. In some embodiments, a wire-fiber transceiver of this disclosure is configured for use with a controlled area network media-access protocol (CAN) and/or a derivative of CAN. Various data communication and other methods are also disclosed in addition to hybrid wire-fiber data networks and components thereof.

Abstract: A passive cable adaptor for connecting a data source device with a display device is described. The adaptor has a packet-based interface connector at one end, the connector having a positive main link pin, a negative main link pin, a positive auxiliary channel pin, and a negative auxiliary channel pin. At the other end is a micro serial interface connector, wherein multimedia content is transmitted over the cable adaptor and electrical power is supplied over the cable adaptor simultaneously. The cable adaptor has an auxiliary and hot plug detect (HPD) controller utilized to map the auxiliary channel and HPD signals of the packet-based digital display to the micro serial interface ID signal.

Abstract: In one embodiment, a processor includes a minimum energy point (MEP) controller to: generate a change in thermal tracking information, based at least in part on prior and current thermal information; generate a change in activity tracking information, based at least in part on prior activity information and current activity information; and determine a MEP performance state based at least in part on the change in thermal tracking information and the change in activity tracking information. Other embodiments are described and claimed.

Abstract: Methods and systems for power management are disclosed. The disclosed power management method and systems may improve the likelihood of data processing systems providing desired computer implemented services while meeting power budget goals and/or other types of goals regarding power consumption, use, and/or provisioning. To improve the likelihood of the power budgets being met, the system may dynamically update power allocations to various components of data processing systems. The power allocations may be dynamically allocated by predicting how changes in existing power allocations may impact the ability of the data processing system to service power allocation requests. If it appears that changes in one or more existing power allocations may allow a power allocation request to be serviced, then the power allocations may be dynamically reallocated to free allocable power. The freed allocable power may be used to service the power allocation.

Abstract: The transmission device with external power includes a first USB type-C connector, a second USB type-C connector, a power transmission cable, a data transmission cable and a switching unit. The first USB type-C connector and the second USB type-C connector are connected to the first electronic device and the second electronic device. The power transmission cable is connected to the first USB type-C connector and the second USB type-C connector, so that the first electronic device supplies power to the second electronic device through the power transmission cable according to charging information of the second electronic device. The switching unit is connected to a power input end and the second USB type-C connector through the power transmission cable. When the first electronic device supplies power to the second electronic device, the switching unit is turned on and the power input end supplies power to the second electronic device.

Abstract: A method of securing functionalities of an integrated subscriber identification module (iSIM) on an information handling system may include with an embedded controller (EC), detecting a powering-up process at the information handling system and determine a chain of trust access keys during bootup; with the execution of the EC, detecting and activating a wireless wide area network (WWAN) module; with the execution of the EC, detecting and accessing an integrated subscriber identity module (iSIM); with the execution of the EC, authenticating access to iSIM content including authorization information and carrier profile information with the chain of trust access keys generated from encryption keys based on digital signatures; and sending the authorization information and carrier profile information form the iSIM to the WWAN module for authentication, wirelessly, with a switched multimegabit data service (SM-DS) server associated with the carrier profile.

Abstract: Emergency power control systems enable Power-over-Ethernet (PoE) devices to be powered by primary and emergency power sources.

Abstract: A Power over Ethernet (PoE) Powered Device (60) is described herein that includes an auxiliary processor (62) that negotiates a power level with a PoE Power Sourcing Equipment using a first link layer (650), means for holding the PoE Powered Device in a low power state, and a second link layer (50) that allows the main processor to communicate over the Ethernet.

Abstract: A power supply circuit includes a power supply which supplies DC power to a load, a switch which is selectively operable to (i) cause a short-circuit to occur between a DC power supply and an input terminal of the power supply and (ii) open a connection between the DC power supply and the input terminal of the power supply, a sensor which measures a temperature and a processor configured to control the switch to open the connection in response to a decision that the DC power is not being supplied to the load even when the switch is being controlled to cause the short-circuit to occur, and control the switch to cause the short-circuit to occur after a predetermined time elapses after controlling the switch to open the connection in response to the decision. The predetermined time is set based on the temperature measured by the sensor.

Abstract: A storage device may include a connector comprising a power management pin, a detector circuit configured to detect a transition of a power management signal received on the power management pin, and a power management circuit capable of configuring power to at least a portion of the storage device based, at least in part, on the detector circuit detecting a transition of the power management signal. The connector may further include a port enable pin, and the power management circuit may be configured to be disabled based, at least in part, on a state of the port enable pin. A storage device may include a connector comprising a power management pin, a nonvolatile memory, and a power management circuit configured to operate in a first power management mode based on determining a first state of the nonvolatile memory.

Abstract: Power management for an integrated circuit. At least one example embodiment is a method of operating an integrated circuit on a semiconductor substrate, the method comprising: measuring, by a body voltage controller, a signal indicative of power consumption of devices on the semiconductor substrate, the body voltage controller implemented on the semiconductor substrate; creating, by the body voltage controller, a value indicative of a modified body voltage, the creating based on the signal indicative of power consumption; and modifying, by a body voltage converter on the semiconductor substrate, a body voltage applied to a plurality of transistors on the semiconductor substrate, the modification responsive to the value indicative of the modified body voltage.

Abstract: A system and a method for predicting a battery consumption of an electric vehicle are disclosed. The battery consumption prediction system of the electric vehicle predicts the battery consumption considering an overall state of the electric vehicle and an external environment of the electric vehicle. The battery consumption prediction system of the electric vehicle may be associated with an artificial intelligence module, a robot, an augmented reality (AR) device, a virtual reality (VR) device, devices related to 5G services, and the like.

Abstract: A power management arrangement (10) for a device connection system 5 is described. The power management arrangement comprises a processing module (30) connected to data communication lines (35) for exchanging data with one or more peripherals (100), an interrupt interface (20) connected to interrupt channels (25) for sending an interrupt to and from one or more of the peripherals (100), and a local storage (50) connected to the processing module (30) for storing of logic operations relating to communication with and operation of the plurality of peripherals (100).

Abstract: Data center mechanical infrastructure is incrementally deployed and commissioned to support incremental changes in computing capacity in a data center while mitigating interaction between infrastructure being commissioned and installed computer systems. Incremental mechanical infrastructure commissioning can be concurrent with incremental electrical infrastructure commissioning and includes operating mechanical infrastructure to remove heat generated as a result of operating electrical infrastructure to support simulated electrical loads as part of electrical infrastructure commissioning. Incremental mechanical infrastructure deployment can be based on the power support capacity provided by incrementally deployed electrical infrastructure.

Abstract: In one embodiment, a method includes transmitting multi-phase pulse power from power sourcing equipment to a powered device in a data center, wherein the multi-phase pulse power comprises multiple phases of power delivered in a sequence of pulses defined by alternating low direct current voltage states and high direct current voltage states, and synchronizing the pulses at the power sourcing equipment with the pulses at the powered device.

Abstract: A disclosed technique includes triggering a change for a first set of one or more functional elements and for a second set of one or more functional elements from a high-power state to a low-power state; saving first state of the first set of one or more functional elements via a first set of one or more save-state elements; saving second state of the second set of one or more functional elements via a second set of one or more save-state elements; powering down the first set of one or more functional elements and the second set of one or more functional elements; and transmitting the first state and the second state to a memory.

Abstract: Power over Ethernet system having multiple power source devices comprising a control device that controls power distribution to a plurality of communication ports. In the control device, a master controller provides a power supply to power consumption look-up-table to a plurality of control circuits in various manners via a series bus. When one power source device shuts down, each control circuit can rapidly shut off selected port switches connected thereto.