Abstract: A supply and demand control device includes: a first communication unit which communicates, via a communication network, with an electrical device which belongs to a customer and consumes power from a power system; and a control unit which obtains a frequency of the power system, and start observation control if the obtained frequency falls below a lower limit of a predetermined frequency range, in which in the observation control, the control unit determines start time for reducing power consumption by the electrical device via the first communication unit, based on a rate of change in frequency obtained after the observation control is started, and starts reducing the power consumption at the start time if the obtained frequency does not return to within the predetermined frequency range within an observation duration which is a duration from start of the observation control to the start time.

Abstract: Embodiments relate to power down processing including control path power adjustment. An aspect includes receiving, by a power down engine, chip layout data corresponding to a chip design. Another aspect includes determining a confluence point of a data path and a control path in the chip layout data. Another aspect includes determining the presence of a positive slack window in the control path of the confluence point. Yet another aspect includes powering up the control path to reduce the positive slack window.

Abstract: Methods and apparatuses relating to transactional power management are described. In one embodiment, a hardware apparatus includes a hardware processor having a core, a plurality of power domains to transition to one of a plurality of power states in response to a power management command for each power domain, and a power transaction unit to assign a first power management command as a first power transaction and a second power management command as a second power transaction for concurrent execution, perform a commit of the first power transaction and the second power transaction when there is no conflict between the first power transaction and the second power transaction, and perform an abort of the first power transaction and a commit of the second power transaction when there is a conflict between the first power transaction and the second power transaction.

Abstract: A controlled apparatus periodically transmits state information indicating the state of the apparatus, and when the state has been changed, transmits state information indicating the state after the change. Upon receiving state information from the controlled apparatus, a control apparatus, when not requesting a change of state in the controlled apparatus, returns the state information to the controlled apparatus, and when requesting a change of the state in the controlled apparatus, changes state parameters in the state information that correspond to the state to be changed to required values and transmits the state information after the change to the controlled apparatus as a control command. The controlled apparatus, upon receiving the control command from the control apparatus, changes to a state in accordance with the state parameters that follow the change and transmits the state information indicating the state after the change to the control apparatus.

Abstract: Embodiments relate to power down processing including control path power adjustment. An aspect includes receiving, by a power down engine, chip layout data corresponding to a chip design. Another aspect includes determining a confluence point of a data path and a control path in the chip layout data. Another aspect includes determining the presence of a positive slack window in the control path of the confluence point. Yet another aspect includes powering up the control path to reduce the positive slack window.

Abstract: A rack-style computer system is provided. The computer system includes a first server, a second server, and a power distribution unit (PDU). The PDU supplies power to the first server and the second server and monitors the power supplied to the first server and the second server and obtains a power sum value. The first server determines whether the power sum value exceeds a predetermined threshold, and if the determination is affirmative, the first server performs a power throttling.

Abstract: A system and method for adaptive thermal and performance management in electronic devices are disclosed. A particular embodiment includes: providing a processor with a plurality of selectable performance levels and a sensor in an electronic device; receiving sensor information from the sensor, the sensor information including information for determining if the electronic device is positioned proximately to an active airflow; determining a device context from the sensor information; and dynamically modifying the performance level of the processor by implementing one of a plurality of selectable performance levels of the processor based on the device context.

Abstract: An electricity saving method and apparatus for a USB data transmission system are provided, wherein the USB data transmission system includes a USB device and a host device which performs data transmission by using a mass storage protocol with the USB device. The above-mentioned method includes: a host device detecting a detection instruction sent by the host device to a USB device, wherein the detection instruction is used for detecting whether the USB device has already been connected to the host device; in a situation that the detection instruction is detected and there is no specified data transmission between the host device and USB device, the host device replacing the USB device to analyze and respond to the detection instruction; when a duration during which there is no data transmission between the host device and USB device exceeds a predetermined duration, the host device notifying the USB device to suspend.

Abstract: In an embodiment, a processor includes at least one core and energy performance gain (EPG) logic to determine an EPG frequency based on a first value of an EPG. The EPG is based upon energy consumed by the processor and upon performance of the processor. The processor also includes a clock generator to generate a frequency of operation of the at least one core based on the EPG frequency. Other embodiments are described and claimed.

Abstract: An apparatus for monitoring operation of a design under test (DUT) comprises a plurality of inputs comprising: an incoming clock edge input connected to detect active clock edges provided to a monitored clock gate; an outgoing clock edge input connected to detect active clock edges sent from the monitored clock gate; an enable input connected to detect enable signals provided to the monitored clock gate and any leaf clock gates connected to receive clock edges through the monitored clock gate; and a protocol input connected to receive protocol signals specifying when the monitored clock gate is required to output active clock edges. The apparatus also comprises a memory in communication with the inputs for storing values from the inputs, and a processor in communication with the memory and the inputs, the processor programmed to determine protocol compliance and to calculate energy consequences of dropping of active clock edges.

Abstract: Embodiments are described for a method of reducing power consumption in source synchronous bus systems by reducing signal transitions in the system. Instead of sending clock and data valid signals, only the start and end of valid data packets are marked by clock signal transitions, or only a number of clock pulses that corresponds to number of data words is sent, or only a number transitions on clock signals are sent. The clock signal transitions may comprise either clock pulses or exclusively rising edge or falling edge transitions of the clock signal.

Abstract: An adaptive clock distribution (ACD) system with a voltage tracking clock generator (VTCG) is disclosed. The ACD system includes a tunable-length delay (TLD) circuit, to generate a TLD clock by adding a preselected delay to a root clock, and a voltage droop detector for detecting a voltage droop in a supply voltage. The VTCG is configured to generate a VTCG clock, wherein a frequency of the VTCG clock is finely tuned to one of two or more values to correspond to a magnitude of the supply voltage during the voltage droop. A clock selector selects the VTCG clock as an ACD clock to be provided to an electronic circuit during the voltage droop and the TLD clock as the ACD clock when there is no voltage droop detected.

Abstract: In one example a controller comprises logic, at least partially including hardware logic, configured to define a control relationship between a first control loop associated with a first heat source and a second control loop associated with a second heat source and enforce the control relationship during throttling operations of the first heat source and the second heat source. Other examples may be described.

Abstract: A method, an integrated circuit and a system for implementing a secure chain of trust is disclosed. While executing secure boot code in a secure boot mode, less-secure boot code may be authenticated using a secret key. A secure key may also be calculated or generated during the secure boot mode. After control is turned over to the authenticated less-secure boot code, at least one application may be authenticated using the secure key. Once authenticated in the less-secure boot mode, the application may be executed by the programmable integrated circuit. In this manner, a secure chain of trust may be implemented for the programmable integrated circuit.

Abstract: Function resources/memory resources and an associated resource controller configured to assign a first portion of the function resources/memory resources to at least one processing element in response to an access request from the processing element. The resource controller changes a power mode of the first portion of the function resources/memory resources as a function of the first portion assignment, and leaves an unassigned portion of the function resources/memory resources in a power down mode in a self-governing nature. The resource controller enables the processing element to access the first portion of the function resources/memory resources in response to the access request received from the processing element. The function resources/memory resources, resource controllers and one or more processing elements may comprise a system on a chip (SoC).

Abstract: The present invention relates to a method and apparatus for disconnecting a bias current circuitry (140) in a way that there is no bias current flowing anymore for the transmit output of a network controller (110), e.g. Ethernet controller. Also, the data connection, e.g., TX+ and TX? lines in or at an Ethernet connector (120), are connected to a control circuitry (130) to simulate an active connection by taking over supply of link activation pulses, e.g., link integrity test (LIT) pulses. These two measures will allow the user to save the bias current on the transmit output and maintain the link activation signals to keep the link up towards a network controller (110).

Abstract: An information processing apparatus includes a plurality of processing units each configured to execute predetermined processing on input data in parallel and calculate an evaluation value based on the executed processing, an estimation unit configured to perform estimation of a processing time required for each of the plurality of the processing units to perform the predetermined processing based on the evaluation values calculated by the relevant processing unit and at least one other processing unit of the plurality of the processing units, and a clock control unit configured to, with respect to each of the processing units, determine a frequency of a clock signal to be supplied to the relevant processing unit in response to the estimated processing time of the relevant processing unit and supply the clock signal having the determined frequency.

Abstract: The disclosed embodiments provide a system that facilitates power management in a multi-core processor. During operation, the system detects a change related to a number of active processor cores in the multi-core processor. (Within this system, a given processor core can reside in an active state, wherein the given processor core can draw an active power, or alternatively in a constrained state, wherein the given processor core can draw a constrained power, which is less than the active power.) In response to detecting the change, the system computes a new current limit ICCMAX for the multi-core processor based on the number of active and constrained processor cores. Finally, the system communicates ICCMAX to a power-management mechanism within the multi-core processor. This enables the power-management mechanism to use ICCMAX to account for power saved by the constrained processor cores when the multi-core system is subsequently determining whether to change its operating frequency.

Abstract: In an embodiment, a processor includes a first logic to calculate a scalability value for a processor domain based at least in part on an active state residency, a stall duration, and a memory bandwidth of the domain, and to determine an operating frequency update for the domain based at least in part on a current operating frequency of the domain and the scalability value. Other embodiments are described and claimed.

Abstract: An apparatus includes a distribution network that includes circuitry configured to receive first power from a first voltage source and second power from a second voltage source, and to deliver power to each of a plurality of electronic circuitry blocks (ECBs), including to deliver first ECB power to a first ECB and second ECB power to a second ECB. The first ECB power includes a first portion of the first power and a first portion of the second power. The apparatus also includes power management logic to dynamically adjust the power to be provided to each ECB. Responsive to a change in a first activity level of the first ECB, the power management logic is to change the first ECB power by adjustment of the first portion of the first power and adjustment of the first portion of the second power. Other embodiments are described and claimed.

Abstract: A clock frequency is controlled by determining a cumulative duty cycle according to a ratio of a cumulative time, during an interval, that the clock frequency has a frequency greater than or equal to a design frequency threshold value to a duration of the interval. A frequency of the clock frequency is controlled to be a first frequency value when the cumulative duty cycle is less than a first duty cycle threshold; and controlled to be a second frequency value substantially less than the first frequency value when the cumulative duty cycle is greater than a second duty cycle threshold. The second duty cycle threshold is greater than or equal to the first duty cycle threshold.

Abstract: A multi-processor system with dynamic power optimization for an integrated circuit and methods thereof are described. An input rate control signal is generated responsive to at least one input data stream. An output rate control signal is generated responsive to an output of the plurality of processors. The input rate control signal and the output rate control signal are monitored. The at least one input data stream is partitioned in response to the input rate control signal. The partitioned data is distributed to at least a portion of the plurality of processors. The plurality of processors is operated in a plurality of modes responsive to the monitoring.

Abstract: The systems and methods described herein relate to the power efficient measurement of physical activity with a wearable sensor. More particularly, the systems and methods described herein enable the continuous activity tracking without compromising battery life. In some implementations, the wearable sensor detects movement and enters predefined power states responsive to the type of movement detected.

Abstract: A method includes determining a first output voltage of a battery of an electronic device. Based on the first output voltage, a first configuration file is identified. Touches on the touch-sensitive display are detected utilizing at least one parameter from the first configuration file.

Abstract: An electronic device comprises one or more functional units, each functional unit being clocked by a respective clock signal. The electronic device further comprises a monitoring unit for providing a real-time estimate of an electrical current consumed by the functional units. The monitoring unit provides the real-time estimate on the basis of characteristic signals. The characteristic signals may comprise one or more of said clock signals, or one or more clock generating signals used to generate said clock signals. The electronic device may further comprise a power regulator responsive to the real-time estimate. A method of estimating in real-time an electrical current consumed by one or more functional units is also described.

Abstract: A microphone circuit includes a microphone configured to generate a microphone signal. The microphone circuit also includes a processor configured to perform sound detection based on the microphone signal and to determine whether to enable a component based on the sound detection. For example, the processor may be a digital signal processor (DSP) of the microphone circuit and the component may be external to the microphone circuit, such as a coder/decoder (CODEC), another DSP, and/or an application processor.

Abstract: A system and a method which include one or more processors, a memory coupled to at least one of the processors, a communication link coupled to the memory, and a power management unit. The power management unit may be configured to detect an inactive state of at least one of the processors. The power management unit may be configured to disable the communication link at a time after the processor enters the inactive state, and disable the memory at another time after the processor enters the inactive state.

Abstract: A method and apparatus for providing telemetry for use in power control functions is disclosed. A system includes an integrated circuit (IC) having a first power management circuit. The IC also includes a number of functional circuit blocks within a number of different power domains. A second power management circuit is implemented external to the IC and includes a number of voltage regulators. Each of the power domains is coupled to receive power from one voltage regulators. During operation, the first power management circuit may send commands requesting the change of one or more voltages provided to the IC. The second power management circuit may respond by performing the requested voltage change(s), and may also provide telemetry data to the first power management circuit. The second power management circuit may also provide telemetry data responsive to receiving a no operation command from the first power management circuit.

Abstract: Apparatuses and methods of operating memory are described. One such method can include receiving a select command at a plurality of memory volumes of a memory device, the select command indicating a targeted memory volume of the plurality of memory volumes. In response to the select command, the method can include selecting the targeted memory volume of the memory volumes and putting at least a portion of a non-selected memory volume of the memory volumes in a particular state based, at least in part, on a previous state of the non-selected memory volume and/or a portion of an address associated with the select command.

Abstract: In one embodiment of the invention, a memory apparatus is disclosed. The memory apparatus includes a memory array, a block read/write controller, and a random access read memory controller. The memory array is block read/write accessible and random read accessible. The block read/write controller is coupled between the memory array and an external interconnect. The block read/write controller performs block read/write operations upon the memory array to access blocks of consecutive memory locations therein. The random access read memory controller is coupled between the memory array and the external interconnect in parallel with the block read/write access controller. The random access read memory controller performs random read memory operations upon the memory array to access random memory locations therein.

Abstract: A data processing system includes an interrupt controller that counts, as an interrupt processing execution count, executions of interrupt processing by threads executed by data processing devices; and a processor that is configured to select one scheduling method from among a plurality of scheduling methods, based on the interrupt processing execution count.

Abstract: An asynchronous successive approximation register analog-to-digital converter and an internal clock generator included in the same are disclosed. The internal clock generator in an SAR ADC comprises a detection unit configured to generate an up pulse or a down pulse by sensing generation time of a final internal clock and next external clock; and a delay block configured to increase or decrease delay time by controlling a bias voltage according to the generated up pulse or the generated down pulse.

Abstract: In one embodiment, the present invention includes a multicore processor having a variable frequency domain including a plurality of cores and at least a portion of non-core circuitry of the processor. This non-core portion can include a cache memory, a cache controller, and an interconnect structure. In addition to this variable frequency domain, the processor can further have a fixed frequency domain including a power control unit (PCU). This unit may be configured to cause a frequency change to the variable frequency domain without draining the non-core portion of pending transactions. Other embodiments are described and claimed.

Abstract: The present invention provides a method and a programmable timing device that includes a timing device circuit for generating at least one timing signal, a static random access memory (SRAM) coupled to the timing device circuit, a read only memory (ROM) having a first timing device configuration stored therein, a one time programmable non volatile memory (OTP NVM) for storing a second timing device configuration and selection logic. The selection logic includes an output coupled to the SRAM, a first input coupled to the ROM and a second input coupled to the OTP NVM. The selection logic is operable to receive input indicating whether SRAM is to be loaded from the ROM or the OTP NVM, and operable to load either the first timing device configuration from the ROM or the second timing device configuration from the OTP NVM based on the input.

Abstract: In one embodiment, a system includes power management control that controls a duty cycle of a processor to manage power. The duty cycle may be the amount of time that the processor is powered on as a percentage of the total time. By frequently powering up and powering down the processor during a period of time, the power consumption of the processor may be controlled while providing the perception that the processor is continuously available. For example, the processor may be a graphics processing unit (GPU), and the period of time over which the duty cycle is managed may be a frame to be displayed on the display screen viewed by a user of the system.

Abstract: A multicore processor system includes multiple processors; a device; a memory that stores information of voltage and clock frequency for minimizing power consumption in connection with a number of the processors accessing to the device; and a power control unit that controls the voltage and the clock frequency of the processors on the basis of the information stored in the memory if the number of the processors accessing to the device changes.

Abstract: According to an embodiment, there is provided with a non-transitory computer readable medium having instructions stored therein, which, when executed by a computer, causes the computer to execute steps including: calculating an access load on a memory area including a plurality of segment areas and determining, for each of the segment areas, one of a plurality of power states including a first power state and a second power state with its power consumption being lower than that of the first power state in accordance with the access load; and setting each of the segment areas to the power state determined therefor.

Abstract: A power management method in a user terminal receives a power from a power supply unit to charge a system voltage, compares the system voltage with a preset voltage, and controls a power input from the power supply unit according to the comparison result.

Abstract: A power manager (106) and method for managing the power supplied to an electronic device is provided. Furthermore, a system wherein the power supplied to an electronic device is managed is provided. The power manager (106) is operative to monitor a hardware monitor (104) during a monitoring time period. The hardware monitor (104) is coupled to an electronic device (102). The electronic device (102) has a workload during operational use. The hardware monitor is operative to indicate the workload of the electronic device (102). The power manager is operative to control power supplied to the electronic device (102) in dependency on the monitoring.

Abstract: An apparatus and method for dynamically controlling power of a device. In one embodiment, the apparatus includes a first circuit and a second circuit for generating a clock signal, wherein a frequency of the clock signal is dependent on a control voltage provided to the second circuit. A third circuit is coupled to receive the control voltage and is configured to adjust power consumed by the first circuit based on the control voltage.

Abstract: Various embodiments of methods and systems for thermally aware scheduling of workloads in a portable computing device that contains a heterogeneous, multi-processor system on a chip (“SoC”) are disclosed. Because individual processing components in a heterogeneous, multi-processor SoC may exhibit different processing efficiencies at a given temperature, and because more than one of the processing components may be capable of processing a given block of code, thermally aware workload scheduling techniques that compare performance curves of the individual processing components at their measured operating temperatures can be leveraged to optimize quality of service (“QoS”) by allocating workloads in real time, or near real time, to the processing components best positioned to efficiently process the block of code.

Abstract: A microprocessor includes functional units and control registers writeable to cause the functional units to institute actions that reduce the instructions-per-clock rate of the microprocessor to reduce power consumption when the microprocessor is operating in its lowest performance running state. Examples of the actions include in-order vs. out-of-order execution, serial vs. parallel cache access and single vs. multiple instruction issue, retire, translation and/or formatting per clock cycle. The actions may be instituted only if additional conditions exist, such as residing in the lowest performance running state for a minimum time, not running in a higher performance state for more than a maximum time, a user did not disable the feature, the microprocessor supports multiple running states and the operating system supports multiple running states.

Abstract: A power control unit 16 controls the power consumed by a system 10 having a plurality of electrical power consumption states including an active state and at least one power saving state. The system comprises a plurality of subsystems 12 each having a plurality of subsystem power states including an active state and at least one power saving state. The electrical power consumption states of the system correspond to respective different configurations of subsystem power states of the subsystems and the power control unit is arranged for signal interface with the subsystems and a power supply unit 14 of the system for controlling the subsystem power states of each of the subsystems and the power supplied to each of the subsystems by the power supply unit dependent on the required power consumption state of the system.

Abstract: A voltage and frequency scaling system for a processor is provided that may be implemented in dedicated logic or in software. The various voltage and frequency settings for the processor comprise a set of performance settings. The system includes a profiler module that maps each performance setting to a workload range for the processor. The profiler module also maps each workload range to a profiled throughput for the processor. Using a predicated average throughput from the mapping, the voltage and frequency scaling system advantageously selects from the performance settings and commands the processor to operate according to the selected performance setting.

Abstract: A data storage system includes a data storage controller, a data storage device, and a logic circuit. The logic circuit receives hard drive status information from the data storage controller. The information is communicated by a first status signal and a second status signal. The logic circuit provides a power control signal to the data storage device based on a logic state of the first status signal and a logic state of the second status signal.

Abstract: Technologies for high-speed data transmission including a network port logic having a communication lane coupled to a physical medium dependent/physical medium attachment (PMD/PMA) sublayer, a physical coding sublayer (PCS), and a media access control (MAC) sublayer. The communication lane receives serial binary data at a line speed such as 25 gigabits per second. The PMD/PMA converts the serial binary data into parallel data, and the PCS decodes that parallel data using a line code also used for a slower line speed such as 10 gigabits per second. The network port logic may include four independent communication lanes, with each communication lane coupled to a dedicated PMD/PMA, PCS, and MAC. The network port logic may also include a multi-lane PCS and multi-lane MAC to receive and transmit data striped over the four communication lanes. Other embodiments are described and claimed.

Abstract: A semiconductor device according to the present invention includes a first module that issues a first transaction from a first interface unit to be a bus master, a second module that includes a second interface unit to be a bus slave and a third interface unit to be a bus master, and issues a second transaction in response to the first transaction, a third module that receives the second transaction by a fourth interface unit to be a bus slave, a bus master stop request control unit that asserts a bus master stop request and completes an assertion process in response to assertion of a bus master stop acknowledgement, and a code addition unit that adds to the first transaction a compulsory process request code for forcing issuance of the second transaction regardless of the bus master stop request.

Abstract: Various embodiments of methods and systems for dynamically adjusting operating frequency settings of one or more processing components in a portable computing device (“PCD”) are disclosed. One such method involves receiving a request to adjust an operating frequency setting of a processing component to a required frequency (“F_req”) to process a workload. Factor readings associated with the operating capacity of the processing component may be taken. Based on the readings, performance curves associated with the processing component may be queried. The performance curves are used to determine the optimal operating frequency (“F_opt”) for the processing component. The F_opt is compared to the F_req and, if the F_req is less than F_opt, the operating frequency setting of the processing component is set to F_opt. Advantageously, as compared to F_req, at F_opt workload processing may be more efficient and a low power mode may be entered sooner.

Abstract: In an embodiment, a processor includes at least one core to execute instructions and a power controller coupled to the core. The power controller may include a power envelope control logic to receive a plurality of power envelope parameters and to enable a power consumption level of the processor to exceed a power burst threshold for a portion of a time window. This portion may be determined according to a length of the time window and a duty cycle, where the power envelope parameters are programmed for a system including the processor and include the power burst threshold, the time window, and the duty cycle. Other embodiments are described and claimed.

Abstract: An embedded megamodule and an embedded CPU enable power-saving through a combination of hardware and software. The CPU configures the power-down controller (PDC) logic within megamodule and can software trigger a low-power state of logic modules during processor IDLE periods. To wake from this power-down state, a system event is asserted to the CPU through the module interrupt controller. Thus the entry into a low-power state is software-driven during periods of inactivity and power restoration is on system activity that demands the attention of the CPU.