Abstract: The disclosure relates to detecting phase slips that may occur in a multi-lane serial datalink. Phase slips may occur when a lane experiences lane skew, which may introduce a phase slip with respect to another lane. To detect phase slippage, the system may select a reference lane from among the lanes. The system may generate a pre-deskew delta value based on a difference between the FIFO filling level of the reference lane before a deskew and the FIFO filling level of a second lane before the deskew. The system may generate a post-deskew delta value based on a difference between the FIFO filling level of the reference lane after the deskew and the FIFO filling level of the second lane after the deskew. The system may use a difference between the post-deskew delta and the pre-deskew delta to detect phase slip on the second lane relative to the reference lane.

Abstract: Distribution of a reset signal across a system-on-chip (SoC) may be the highest latency signal in the circuit. As a result, the operating frequency of the device is reduced to ensure that the reset signal reaches all intellectual property (IP) blocks during a single clock cycle. A reset synchronizer receives the clock signal and the reset signal as inputs and generates a synchronous reset signal as an output. The synchronous reset signal has a fixed timing relationship with the clock signal. The clock signal may be paused when a reset signal is received. As a result, distribution of the synchronous reset signal may be performed without regard to the latency of the signal. After the synchronous reset signal has been received by all of the IP blocks, reset is deasserted and the clock signal is resumed.

Abstract: A method and apparatus for synchronizing a timebase is disclosed. A timebase management circuit includes limit circuitry, in a first clock domain, which generates, based on a global timebase, an initial timebase limit. The timebase management circuit includes, in a second clock domain, adjustment circuitry that generates an adjusted timebase limit based on the initial timebase limit. A storage circuit in the second clock domain stores a local timebase. Update circuitry, coupled to an output of the storage circuit, generates an updated local timebase using a clock signal in the second clock domain, wherein the updated local timebase is subject to the adjusted timebase limit.

Abstract: According to some embodiments, for a memory device including a base die and a stack of memory dies including a plurality of memory dies stacked on the base die, the base die including a plurality of first input/output (i/o) terminals that are command/address and data terminals and a plurality of second i/o terminals that are direct access terminals, a method includes receiving at the plurality of first i/o terminals a command/address, a clock signal, and data; first transmitting the command/address, clock signal, and data received by the plurality of first i/o terminals from the base die to the stack of memory dies; and second transmitting at least part of one or more of the command/address, clock signal, and data received by a set of the plurality of first i/o terminals through a circuit of the base die to the plurality of second i/o terminals.

Abstract: A delay lock loop circuit includes a receiver, a delay line circuit, a clock signal generator and a phase detecting circuit. The receiver receives a clock signal and a reference voltage and generates a reference clock signal according to the clock signal and the reference voltage. The delay line circuit is coupled to the receiver and generates a delayed clock signal by delaying the reference clock signal with a delay indication signal. The clock signal generator generates an output clock signal according to the delayed clock signal. The phase detecting circuit generates a detection result by sampling the reference clock signal with a feedback clock signal generated by the output clock signal, and generates the delay indication signal according to a digital value of the detection result.

Abstract: System and method for secure time synchronization in an industrial facility, wherein a synchronization request of a facility component is transmitted to a registration service of a certificate management of the facility and the synchronization request is examined by the registration service, where the synchronization request includes a signature of the requesting facility component, and where depending on an outcome of the examination, a synchronization response is then transmitted to the requesting facility component a system time of the facility component is matched to a system time of the registration service based on the synchronization response.

Abstract: The present disclosure is directed to systems and methods directed to improving the functions of a vehicle. Systems and methods are provided that provide a custom tool that autogenerates a set of software agents that allows a system to separate processing, transmission and receiving of messages to achieve better synchronization. The disclosure herein also provides a simplified method of key provisioning by designating one client as a server and assigning a symmetric key to every other client permanently provisioned between that client and the server. Systems and method are further provided that predict faults in a vehicle. Systems and methods are also provided that preserve data in the event of a system crash. Systems and methods are also provided in which an operating system of a vehicle detects the presence of a new peripheral and pulls the related interface file for that new peripheral. Further, a data synchronization solution is provided herein which provides optimized levels of synchronization.

Abstract: A line card of a network box receives a SYNC input signal and generates a first time stamp based on receipt of the SYNC input signal. The line card generates a system clock signal in a phase-locked loop and generates a SYNC output signal by dividing the system clock signal in a divider circuit. The SYNC output signal is fed back to an input terminal as a SYNC feedback signal. A time stamp is generated based on receipt of the SYNC feedback signal. The line card determines a time between the SYNC input signal and the SYNC feedback signal based on the first time stamp and the second time stamp. The timing of the SYNC output signal is adjusted based on the time difference using a coarse time adjustment by adjusting a divide ratio of the divider circuit and using a fine time adjustment in the phase-locked loop based on a residue of a remainder of the time difference not accounted for by the coarse time adjustment.

Abstract: Electronic devices that detect their position and/or orientation with respect to earth's frame of reference are described. A coupler can removeably maintain the electronic devices in physical proximity of one another. Each electronic device can have a housing and the coupler can be included on the housing and arranged to physically connect the housing of the electronic device to the housing of at least one other electronic device. Alternatively, the coupler can be a packaging that maintains the electronic devices in physical proximity of one another. Each electronic device can be calibrated using the orientation or position information obtained by other electronic devices maintained by the coupler. Further, each electronic device can include a power source that remains inactive until the device is ready for use.

Abstract: A line card receives a SYNC input signal and a first system clock signal. The line card generates a second system clock signal in a PLL and generates a SYNC output signal by dividing the second system clock signal in a divider circuit. The SYNC output signal is fed back as a SYNC feedback signal. The line card determines determining a closest edge of the first system clock signal to a transition of the SYNC input signal and determines a time difference between the closest edge of the first system clock signal and a transition of the SYNC feedback. The SYNC output signal is adjusted based on the time difference using a coarse adjustment by adjusting a divide ratio of the divider circuit and using a fine adjustment in the PLL based on a residue of a remainder of the time difference not accounted for by the coarse time adjustment.

Abstract: Methods, systems, and devices for wireless communications are described. A first wireless device may communicate, with a second wireless device, a first set of messages of a first message type that are acknowledged according to an acknowledgement procedure. The first wireless device, the second wireless device, or both may select a first subset of messages of the first plurality of messages and a first subset of bits from each message of the first subset of messages based on the first set of messages being acknowledged and according to a sampling configuration common to both the first wireless device and the second wireless device. The first wireless device, the second wireless device, or both may generate a key using bit values of the first subset of bits from each message of the first subset of messages, encoding a message using the key, and communicate the encoded message.

Abstract: Provided herein are systems and methods for performing dynamic adaption and correction for internal delays in devices connected to a common time-multiplexed bus. The methods allow devices to operate reliably at a higher bus frequency by correcting for inherent and unknown delays within the components and in the system by measuring the actual delays using multiple readings with the bus. Intrinsic noise and jitter are used to increase the precision of the measurements, thereby essentially using these uncertainties as self-dithering for increased measurement resolution. During adaption, delays may be adjusted in multiple step sizes to speed adaption time.

Abstract: An audio signal processing graph is automatically recomposed to optimize its properties by reassigning and instantiating its nodes on available locales such that the number of inter-locale connections is minimized and latency between inputs, such a performer's live input, and outputs, such as a monitored recording mix, is minimized. The recomposition exploits associative, commutative, and decomposition properties of certain node types, including mixer nodes. A graph recomposition may decompose a mixer node into a first stage instantiated by a software plug-in hosted by a computer running a digital audio workstation in a first locale, and a second stage assigned to an audio processing device in a second locale. Automatic signal graph recomposition occurs when the system is initialized, the graph is reconfigured, a new desired behavior of the graph is specified, or the available network resources are changed.

Abstract: To efficiently collect and transfer monitoring target data in a PLC. The PLC includes a first execution engine, a holding section, and a second execution engine. Further, the PLC collects data stored in a collection target holding section according to predetermined collection setting, accumulates collected time-series data in a first buffer, and transfers the time-series data stored in the first buffer to the second execution engine via a bus. The second execution performs data processing of the transferred time series data, generates display data to be displayed on a dashboard, and provides the display data to an external computer.

Abstract: An information handling system may include a bus initiator, a plurality of bus endpoints, and a single-wire bus communicatively coupled between the bus initiator and the plurality of bus endpoints, wherein the bus comprises a multiplexer. The bus initiator may be configured to perform in-band addressing to select a communications channel through the multiplexer via an addressing protocol that uses pulse bursts for initiation of the addressing, identification of the communications channel, and termination of the addressing. Pulses of the pulse bursts may be sufficiently short in duration to pass through filters of the bus endpoints such that the pulse bursts are not processed by the bus endpoints.

Abstract: An object is to provide a traffic monitoring method, a traffic monitoring apparatus, and a program capable of efficiently merging data structures of each of the cores in a multi-core environment without reconstructing a data structure, retrieving a data structure, and adjusting the RSS function. In the traffic monitoring method according to an embodiment of the present invention, the elements of the data structures formed in the cores are compared for each item, and statistic values in the elements are brought together into any one of the elements, and the statistic values of the other elements are set to zero. Redundant elements between the data structures can be removed by ignoring elements having a statistic value of zero at the time of merging data structures.

Abstract: An image capturing device includes an image capturing unit capturing an image at a timing based on a first frame rate and outputs data corresponding to the image after a first period, an image data generation unit generating image data based on the output data and outputting the image data after a second period, a display unit displaying a display image based on the image data after the second period and at a timing based on a second frame rate, and a mode selecting unit selecting a first or second mode. The first mode prioritizes reduction in a display delay time. The second mode prioritizes image quality of the display image over reduction in the display delay time. A total period of the first and second periods is less than or equal to a first vertical synchronization period based on the first frame rate when the first mode is selected.

Abstract: A synchronized communication system includes a plurality of network communication devices, one of which is designated as a root device and the others designated as slave devices. Each network communication device includes one or more ports and communications circuitry, which processes the communication signals received by the one or more ports so as to recover a respective remote clock from each of the signals. A synchronization circuit is integrated in the root device and provides a root clock signal, which is conveyed by clock links to the slave devices. A host processor selects one of the ports of one of the network communication devices to serve as a master port, finds a clock differential between the root clock signal and the respective remote clock recovered from the master port, and outputs, responsively to the clock differential, a control signal causing the synchronization circuit to adjust the root clock signal.

Abstract: Systems and methods for intelligent synchronization of media streams are provided. A server may receive streams corresponding to an interactive session and sent over a communication network from user devices in the interactive session. A predetermined attribute may be identified as present in each of the streams, but received at different times by the server. The server may determine a time difference between a time that a predetermined attribute in a first stream of the streams was received and a time that the predetermined attribute in a second stream of the streams was received. The first stream and the second stream may then be synchronized using the time difference and provided to a recipient device.

Abstract: an orthogonal frequency division multiplexed (OFDM) output signal produced by a device in response to an OFDM input signal is accessed. The OFDM input signal includes OFDM input symbols in the time domain and the OFDM output signal includes OFDM output symbols in the time domain. The OFDM output symbols are time-aligned to the OFDM input symbols and a phase of the OFDM output signal is de-rotated with respect to the OFDM input signal. A complex equalization filter is applied to the OFDM output symbols in the time domain to obtain an estimate of the OFDM input symbols A distortion signal of the OFDM output signal is determined by subtracting the estimate of the OFDM input symbols. An error vector magnitude (EVM) is determined by dividing a root mean square of the distortion, by a root mean square of the OFDM input signal.

Abstract: A medical operation system includes an information processing apparatus, including processing circuitry configured to cause a map of an operating room to be displayed on a display, the map including an icon representing a device located in the operating room or accessible from the operating room, receive, via a user operation on the displayed map, designation information representing a designation of a change in at least one of an input source, an output destination, or an internal setting for the device, generate a control signal to control the device based on the designation information, and transmit the generated control signal to the device.

Abstract: A processing system comprising an arrangement of tiles and an interconnect between the tiles. The interconnect comprises synchronization logic for coordinating a barrier synchronization to be performed between a group of the tiles. The instruction set comprises a synchronization instruction taking an operand which selects one of a plurality of available modes each specifying a different membership of the group. Execution of the synchronization instruction cause a synchronization request to be transmitted from the respective tile to the synchronization logic, and instruction issue to be suspended on the respective tile pending a synchronization acknowledgement being received back from the synchronization logic. In response to receiving the synchronization request from all the tiles in the group as specified by the operand of the synchronization instruction, the synchronization logic returns the synchronization acknowledgment to the tiles in the specified group.

Abstract: In one embodiment, at least one processing device is configured to assign a plurality of devices of a cluster to a logical host group where at least one of the devices assigned to the logical host group has a network time parameter that is different than another of the devices assigned to the logical host group. The at least one processing device is further configured to determine a target network time parameter for the logical host group based at least in part on network time parameter related information about a given device of the plurality of devices assigned to the logical host group and to cause the plurality of devices to configure their respective network time parameters to the target network time parameter based at least in part on the assignment of the plurality of devices to the logical host group.

Abstract: An integrated circuit (IC) for clock and phase aligning and synchronization between physical (PHY) layers and a communications controller is provided. The IC includes a clock multiplier configured to multiply a frequency of the clock signal from a plurality of PHY layers to match a frequency of a clock signal of the controller, wherein the clock signal from the plurality of PHY layers is less than the frequency of the clock signal of the controller. IC support circuitry is configured to provide the multiplied clock signal to the controller. The IC includes a first clock divider configured to divide the frequency of the multiplied clock signal and to output the divided clock signal to the controller. The IC includes a phase alignment circuit configured to align phases of one or more data signals based on a phase of the clock signal and a phase of the multiplied clock signal.

Abstract: A method and apparatus for synchronizing a time stamp counter (TSC) associated with a processor core in a computer system includes initializing the TSC associated with the processor core by synchronizing the TSC associated with the processor core with at least one other TSC in a hierarchy of TSCs. One or more processor cores are powered down. Upon powering up of the one or more processor cores, the TSC associated with the processor core is synchronized with the at least one other TSC in the hierarchy of TSCs.

Abstract: A four-phase (or multi-phase) generation circuit, related method of operation, and transceivers or other systems utilizing such a circuit, are disclosed herein. In one example embodiment, the circuit includes two input ports respectively configured to receive positive and negative differential input signals, and four output ports respectively configured to output first, second, third and fourth output signals, respectively, the second, third, and fourth output signals being respectively phase-shifted relative to the first output signal by or substantially by 90, 180, and 270 degrees. Also, the circuit includes four SR latches respectively including output terminals that are respectively coupled to the respective output ports. Further, the circuit includes two tunable delay circuits respectively coupled at least indirectly between the input ports and latches, and two comparison circuits configured to output respective feedback signals.

Abstract: A system (1000) is disclosed including a resource allocation optimization (RAO) platform (1002) for optimizing the allocation of resources in network (1004) for delivery of assets to user equipment devices (UEDs) (1012). The RAO platform (1002) determines probabilities that certain asset delivery opportunities (ADOs) will occur within a selected time window and uses these probabilities together with information concerning values of asset delivery to determine an optimal use of asset deliveries. In this regard, the RAO platform (1004) received historical data from repository (1014) that facilitates calculation of probabilities that ADOs will occur. Such information may be compiled based on asset delivery records for similar network environments in the recent past or over time.

Abstract: The disclosure provides a method for correcting a 1 pulse per second (1PPS) signal and a timing receiver. In the embodiments of the disclosure, the proposed method allows the timing receiver to provide a corrected 1PPS signal with better quality to back-end slave devices, thereby ensuring that the synchronization effect of the slave devices is not overly affected by jitter in a single 1PPS signal.

Abstract: The present invention discloses an identification number numbering method and a multipoint communication system. The identification number numbering method includes the following steps: sending an identification number packet to a multipoint communication bus by a master device; receiving the identification number packet via the multipoint communication bus, and temporarily storing an identification number according to the identification number packet by a first slave device; changing a voltage level of a master device control output pin of the master device; and when the first slave device determines that a voltage level of a first control input pin coupled to the master device control output pin is correspondingly changed, updating a first slave device identification number of the first slave device according to the identification number.

Abstract: An apparatus for shifting a digital signal having a first sample rate by a shift time to provide a shifted signal having a second sample rate is provided. The apparatus includes a sample rate converter configured to provide a value of an interpolated signal at a compensated sample time as a sample of the shifted signal, the interpolated signal being based on the digital signal. The sample rate converter is configured to modify a time interval between a sample time of the digital signal and the compensated sample time based on the shift time.

Abstract: A method for operating a visual display apparatus is specified. The apparatus comprises a first optoelectronic semiconductor component configured to emit electromagnetic radiation of a first wavelength and comprising a first intrinsic switch-on delay. The apparatus comprises a second optoelectronic semiconductor component configured to emit electromagnetic radiation of a second wavelength and comprising a second intrinsic switch-on delay. The second wavelength is different from the first wavelength. The first semiconductor component is operated with a first operating current according to a first actuation signal. The second semiconductor component is operated with a second operating current according to a second actuation signal.

Abstract: A method of operation in a memory controller is disclosed. The method includes receiving a strobe signal having a first phase relationship with respect to first data propagating on a first data line, and a second phase relationship with respect to second data propagating on a second data line. A first sample signal is generated based on the first phase relationship and a second sample signal is generated based on the second phase relationship. The first data signal is received using a first receiver clocked by the first sample signal. The second data signal is received using a second receiver clocked by the second sample signal.

Abstract: Embodiments of the disclosure provided herein generally include a system and a method of configuring and/or controlling the transfer of information between two or more electronic devices due to the interaction of an electronic device and a host identifier signal generating system. Embodiments of the disclosure may include a system and a method of distributing useful information received by or contained within a memory of the electronic device based on the receipt of a host identifier signal. The electronic device may then perform one or more desirable functions or processes based the portable electronic device's interaction with the host identifier signal generating system.

Abstract: Creation and use of a digital twin instance (DTI) for a physical instance of the part. The DTI may be created by a model inversion process such that model parameters are iterated until a convergence criterion related to a physical resonance inspection result and a digital resonance inspection result is satisfied. The DTI may then be used in relation to part evaluation including through simulated use of the part. The physical instance of the part may be evaluated by way of the DTI or the DTI may be used to generate maintenance schedules specific to the physical instance of the part.

Abstract: Techniques are provided herein for pre-emptively reinforcing one or more buses of a computing device against the effects of signal noise that could cause a reduction in signal integrity. The techniques generally include detecting an event (or “trigger”) that would tend to indicate that a reduction in signal integrity will occur, examining a reinforcement action policy and system status to determine what reinforcement action to take, and performing the reinforcement action.

Abstract: Instructions can be executed to determine a quantity of logical units that are part of a memory device. The instructions can be executed to operate the logical units with a programming time sufficient to provide a required throughput for storage of time based telemetric sensor data received from a host. The instructions can be executed to operate the logical units with a trim that correspond to the programming time.

Abstract: A processing system includes a digital processing unit programmable as a function of a firmware stored to a non-volatile memory and a resource connected to the digital processing unit via a communication system. The processing system also includes a time reference circuit including a first digital counter circuit to generate, in response to a clock signal, a system time signal including a plurality of bits indicative of a time tick-count, and a time base distribution circuit to generate a time base signal by selecting a subset of the bits of the system time signal, wherein the time base signal is provided to the resource. The resource detects a given event, stores the time base signal to a register in response to the event, and signals the event to the digital processing unit. The digital processing unit reads, via the communication system, the time base signal from the register.

Abstract: Methods, systems, apparatuses, and computer program products are provided for prefetching data. A workload analyzer may identify job characteristics for a plurality of previously executed jobs in a workload executing on a cluster of one or more compute resources. For each job, identified job characteristics may include identification of an input dataset and an input bandwidth characteristic for the input dataset. A future workload predictor may identify future jobs expected to execute on the cluster based at least on the identified job characteristics. A cache assignment determiner may determine a cache assignment that identifies a prefetch dataset for at least one of the future jobs. A network bandwidth allocator may determine a network bandwidth assignment for the prefetch dataset. A plan instructor may instruct a compute resource of the cluster to load data to a cache local to the cluster according to the cache assignment and the network bandwidth assignment.

Abstract: In one embodiment, the present disclosure includes multichip timing synchronization circuits and methods. In one embodiment, hardware counters in different systems are synchronized. Programs on the systems may include synchronization instructions. A second system executes synchronization instruction, and in response thereto, synchronizes a local software counter to a local hardware counter. The software counter on the second system may be delayed a fixed period of time corresponding to a program delay on the first system. The software counter on the second system may further be delayed by an offset to bring software counters on the two systems into sync.

Abstract: A low-power coherent receiver is enabled with enhanced performance for intra-datacenter reach optical interconnection applications using several techniques. The first is a coherent skew adjustment technique which enables lower-power baud-rate ADC sampling and baud-rate-spaced coherent equalization. The second is a real-valued or mixed-valued low-power coherent equalization technique, where a single-tap real-valued 4×4 MIMO equalizer plus four real-valued or two mixed-valued single-input single-out (SISO) equalizers are used for simultaneous polarization recovery, in-phase and quadrature (I/Q) phase error correction, and bandwidth equalization. The third is a power-efficient dual-DSP architecture to enhance coherent receiver performance, in which a complementary low-speed coherent DSP is introduced for optimal I/Q phase error correction and constellation decision parameters determination through more sophisticated algorithms that are too power hungry to be implemented in the primary high-speed DSP.

Abstract: In an aspect, a UE may perform clock synchronization in accordance with a first network timing reference, such as a unicast network timing reference (UNTR) or a broadcast networking timing reference (BNTR). The UE may detect event(s) associated with a connection to a BS, which may trigger a switch between the UNTR and the BNTR for clock synchronization. In a further aspect, a communications device (e.g., UE or BS) may determine to transition a UE between the BNTR and UNTR for clock synchronization, and may perform one or more actions to facilitate the network timing reference transition.

Abstract: The present invention provides a System and method for multi-tiered data synchronization. Data is synchronized between a master synchronization server, one or more proxy synchronization servers, and client devices. Client devices establish synchronization sessions with either a proxy synchronization server or a master synchronization server, depending on which server provides the “best” available connection to that client device. Each proxy synchronization server synchronizes data with client devices that have established a synchronization session with such proxy synchronization server. The master synchronization server synchronizes data with client devices that have established a synchronization session with the master synchronization server. Each proxy synchronization server synchronizes data with the master synchronization server. Metadata associated with synchronized files is synchronized throughout the system in real-time. Files may be synchronized in real-time or of a delayed time.

Abstract: A system is provided for synchronizing clocks. The system includes a plurality of devices in a network, each device having a local clock. The system is configured to synchronize the local clocks according to a primary spanning tree, where the primary spanning tree has a plurality of nodes connected through a plurality of primary links, each node of the plurality of nodes representing a respective device of the plurality of devices. The system is also configured to compute a backup spanning tree before a failure is detected in the primary spanning tree, wherein the backup spanning tree includes one or more backup links that are different from the primary links. As such, upon detection of a failure in the primary spanning tree, the system reconfigures the plurality of devices such that clock synchronization is performed according to the backup spanning tree.

Abstract: Provided are an electronic device and a method of controlling an external device by the electronic device. According to various embodiments of the present disclosure, a method of controlling an external device by an electronic device includes displaying, on a screen, a first user interface (UI) corresponding to first UI data received from an external server, transmitting, to the external device, second UI data corresponding to the first UI, receiving, from the external device, coordinates selected by a user using the external device, obtaining additional information related to the first UI when the coordinates correspond to a position of the first UI displayed on the screen, and transmitting, to the external device, the additional information and an execution command of an application using the additional information.

Abstract: A power module according to the first embodiment incorporates a power device, and drives the power device by using a control signal acquired from a microcomputer being a control circuit. The power module includes: a plurality of first terminals that receive input of the control signal from the microcomputer; a main circuit that drives the power device based on the control signal, and detects an abnormality of the power module; an error output circuit that outputs an error signal from a second terminal to the microcomputer when the abnormality is detected by the main circuit; and a switching circuit that causes the first terminal to operate as an output terminal for the microcomputer when the error signal is output. Information of the power device is output from the first terminal operating as the output terminal to the microcomputer.

Abstract: A method for adjusting the signal frequency includes: acquiring a first number of times of outputting a reference signal at an active level within a reference duration, wherein a correlation between a frequency of the reference signal and temperature is less than a reference correlation threshold, the reference duration is negatively correlated with a frequency of a clock signal, a correlation between a frequency of a clock signal and temperature is greater than the reference correlation threshold, and a drive signal for driving a display device to display an image is generated based on the clock signal; acquiring a target adjustment value based on the first number of times if the first number of times is different from a reference number of times; and controlling and adjusting the frequency of the output clock signal based on the target adjustment value.

Abstract: Disclosed herein is an apparatus that includes a first shift register circuit including a plurality of first latch circuits coupled in series, and a second shift register circuit including a plurality of second latch circuits coupled in series. The first and second shift register circuits are cyclically coupled. Each of the first latch circuits is configured to perform the latch operation in synchronization with a rise edge of a first clock signal. Each of the second latch circuits is configured to perform the latch operation in synchronization with a fall edge of a first clock signal when a first selection signal is in a first state. One or more first latch circuits and one or more second latch circuits are configured to be bypassed when a second selection signal indicates a predetermined value.

Abstract: A semiconductor device includes a memory device configured to have a first buffer and a second buffer, the first buffer storing a plurality of requests sent to a plurality of destinations, the second buffer storing identification information of the entry associated with a first destination of a first request written to first buffer; and an entry selector configured to identify the first destination from the plurality of destinations when the identification information of the entry is stored in the second buffer, and to read the first request from the plurality of requests stored in the first buffer by using the first destination.

Abstract: Automated correlation of process attribute value changes with events related to the changes. A managed historian utilizes a namespace property to correlate process tag values with corresponding events. The managed historian generates and provides to remote user devices a graphical user interface that includes a plot of data values of the process tag and a visual icon representing the event overlaid atop the plot of data values.

Abstract: A parameter synchronization method is implemented in a computing device. The parameter synchronization method includes importing a deep learning training task of a preset model into a server communicatively coupled to the computing device, recording a preset number of iterative processes during the deep learning training, dividing each iterative process into a number of phases according to time, determining whether a time ratio of an H2D phase, a D2H phase, and a CPU phase in each iterative process is greater than a preset value, and confirming the server to use a copy mode for performing parameter synchronization when the time ratio of the H2D, D2H, and CPU phases is determined to be greater than the preset value.