Abstract: Apparatuses and methods for transmitting a command mode (e.g., operation mode) associated with a command between devices are disclosed. One device may be configured as a master and one or more devices may be configured as slaves. The command mode may be transmitted by the master to the slaves by setting a resting state of a clock signal transmitted between the devices and transitioning a device enable signal to an active state. The slaves may detect the resting state of the clock at the time the enable signal is transitioned to the active state in order to determine the command mode of the command. The devices may then execute the command in the mode indicated by the transmitted command mode.

Abstract: A browser-based video editor is configured to allow a user to create a composition schema having multimedia layers, including video, audio, and graphic and text layers. The composition schema may be transmitted to a remote service that employs a rendering engine to play back the composition schema and align the clocks for each respective multimedia layer into a single video representation. A master clock object is employed to sync the clocks while also checking a series of properties with each multimedia layer to comport the multimedia layers with an interval-based master clock. The composition schema is recorded using FFmpeg (Fast Forward Moving Picture Experts Group) to create a video representation for user consumption, such as an MP4 (Motion Pictures Experts Group 4) formatted file.

Abstract: The disclosed embodiments relate to a memory system that generates a multiplied timing signal from a reference timing signal. During operation, the system receives a reference timing signal. Next, the system produces a multiplied timing signal from the reference timing signal by generating a burst comprising multiple timing events for each timing event in the reference timing signal, wherein consecutive timing events in each burst of timing events are separated by a bit time. Then, as the reference clock frequency changes, the interval between bursts of timing events changes while the bit time remains substantially constant.

Abstract: To precisely synchronize system clocks, medium clocks, or the like of apparatuses with each other. A wireless apparatus includes a main control unit and a wireless control unit. Information regarding a correspondence between a clock that manages a time of the main control unit and a clock that manages a time of the wireless control unit is wirelessly sent to another wireless apparatus by the wireless control unit. This information regarding the correspondence includes information regarding a difference between the two clocks, information regarding a granularity ratio of the two clocks, and the like. For example, the wireless control unit sends the information regarding the correspondence as a part of a frame for measuring the time of the wireless control unit with respect to the other wireless apparatus or a part of a frame for connecting to the other wireless apparatus.

Abstract: An electronic device that coordinates a playback operation is described. In particular, an interface circuit in the electronic device may calculate, based on differences between transmit times when packets were transmitted by a second electronic device and receive times of the packets, relative drift as a function of time between a clock in the interface circuit and a second clock in the second electronic device. Then, the interface circuit may adjust, based on the relative drift, a clock circuit that provides the clock to eliminate the relative drift, and may determine a remaining time offset between the clock and the second clock. Next, the interface circuit may modify a future time when the second electronic device is to perform the playback operation based on the remaining time offset to determine a corrected future time, and may transmit information to the second electronic device specifying the corrected future time.

Abstract: A method for providing, based on an emulation schedule, a reset message to multiple circuits is provided. The reset message associates a reset signal with a selected clock cycle for each circuit, in the emulation schedule. The method includes determining a mask for each of the circuits based on the emulation schedule, providing a clock signal to the circuits, the clock signal comprising the selected clock cycle for each circuit, and tuning the reset signal relative to the clock signal based on a center of the selected clock cycle for each circuit. The method also includes providing the reset signal to the circuits and asserting the reset signal in the circuits based on the mask. A system and a non-transitory, machine-readable medium storing instructions to perform the above method are also provided.

Abstract: An IC design method is provided that includes steps outlined below. A clock tree structure is retrieved from an IC design file. A branch level number of a branch that each of clock units in the clock tree structure locates is determined. A common branch level number of a common branch that closest to each two of the flip-flops is determined. A scan chain structure is retrieved from the IC design file. A wire distance and a clock skew of each two of the flip-flops are determined. A cost is calculated according to the common branch number, the wire distance and the clock skew. An initial point and a terminal point of the flip-flops in the scan chain structure are determined to further calculate a path having a minimum cost. The order of the scan chain structure of the IC design file is updated.

Abstract: A small form-factor pluggable (SFP) time signal adapter module includes a printed circuit board, a cable connector mounted to the printed circuit board, and a differential receiver coupled to the cable connector, one or more of the plurality of wire traces, and an SFP edge connector. The printed circuit board has a plurality of wire traces and a plurality of pads of the SFP edge connector is at least coupled to two of the plurality of wire traces. The cable connector is coupled to at least one or more of the plurality of wire traces. The cable connector coupes to a connector of a cable to receive a differential time reference signal. The differential receiver receives and differentiates the differential time input signal to generate a single ended time reference signal that is coupled to a pad of the SFP edge connector.

Abstract: A switching device includes two connection lands, a measurement device for measuring a first quantity of a current flowing between the two lands, a power supply system and a trigger module, the latter including a first driver module for detecting an electrical fault according to first values stored in a first memory and controlling a switching member; a communication module for receiving and storing second values in a second, non-volatile memory; and a second driver module for replacing the first values with the second values in the first memory. The first driver module compares a second quantity of the first supply current with a threshold and controls the supply of power to the second driver module if the second value is higher than or equal to the threshold.

Abstract: We disclose herein an electronic device comprising: a state machine for receiving an output signal from a sensor; a comparator operatively coupled with the state machine; and a first processor operatively coupled with the comparator. The state machine is configured to receive the output signal from the at least one sensor to obtain sensor measurement data and configured to pass the obtained sensor measurement data to the comparator. The comparator is configured to process the obtained sensor measurement data into first processed sensor data, and configured to compare the first processed sensor data with a first predetermined threshold limit. The comparator is configured to inform the first processor about the obtained sensor measurement data if the first processed sensor data exceed the first predetermined threshold limit.

Abstract: A data serialization circuit includes a clock data operation circuit configured to generate a plurality of delay clock signals and a plurality of synchronous data signals in response to a plurality of parallel data signals and a plurality of multi-phase clock signals and a multiplexer configured to output a serial data signal in response to the plurality of delay clock signals and the plurality of synchronous data signals. A first one of the plurality of delay clock signals substantially aligns with a first one of the plurality of synchronous data signals.

Abstract: A memory controller component of a memory system stores memory access requests within a transaction queue until serviced so that, over time, the transaction queue alternates between occupied and empty states. The memory controller transitions the memory system to a low power mode in response to detecting the transaction queue is has remained in the empty state for a predetermined time. In the transition to the low power mode, the memory controller disables oscillation of one or more timing signals required to time data signaling operations within synchronous communication circuits of one or more attached memory devices and also disables one or more power consuming circuits within the synchronous communication circuits of the one or more memory devices.

Abstract: A recycling kiosk for recycling and financial remuneration for submission of a mobile telephone is disclosed herein. The recycling kiosk includes an inspection area with a plurality of white walls in order to perform a visual analysis of the mobile telephone for determination of a value of the mobile telephone. The visual analysis inspects the LCD screen of the mobile phone to determine if the LCD screen is damaged. The recycling kiosk also includes a processor, a display and a user interface.

Abstract: A method for testing autonomous reconfiguration logic for an electromechanical actuator includes executing a plurality of test cases against a computer model configured and operable to implement autonomous reconfiguration logic for an electromechanical actuator including a plurality of electromechanical motors to generate a first set of test results. The method further includes executing the plurality of test cases against a programmable logic device configured and operable to implement the autonomous reconfiguration logic for the electromechanical actuator to generate a second set of test results and comparing the first set of test results to the second set of test results.

Abstract: Various implementations described herein refer to an integrated circuit having first clock circuitry that receives a first clock signal and provides sampled offset pulses associated with the first clock signal when enabled with enable signals. The integrated circuit may include second clock circuitry that receives a second clock signal and provides the enable signals to the first clock circuitry based on the second clock signal. The integrated circuit may include fault detector circuitry that receives the sampled offset pulses from the first clock circuitry, receives the enable signals from the second clock circuitry, and provides one or more error flags for detected faults of the first clock signal based on the sampled offset pulses from the first clock circuitry and based on the enable signals from the second clock circuitry.

Abstract: Apparatus comprises master counter circuitry to generate a master count signal in response to a clock signal; slave counter circuitry responsive to the clock signal to generate a respective slave count signal, the slave counter circuitry having associated fault detection circuitry; and a synchronisation connection providing signal communication between the master counter circuitry and the slave counter circuitry, the master counter circuitry being configured to provide via the synchronisation connection: initialisation data at an initialisation operation; and fault detection data at a fault detection operation; the initialisation data and subsequent fault detection data each representing respective indications of a state of the master count signal; the slave counter circuitry being configured, during an initialisation operation for that slave counter circuitry, to initialise a counting operation of that slave counter circuitry in response to the initialisation data provided by the master counter circuitry; an

Abstract: A signaling system is disclosed. The signaling system includes a first integrated circuit (IC) chip to receive a data signal and a strobe signal. The first IC includes circuitry to sample the data signal at times indicated by the strobe signal to generate phase error information and circuitry to output the phase error information from the first IC device. The system further includes a signaling link and a second IC chip coupled to the first IC chip via the signaling link to output the data signal and the strobe signal to the first IC chip. The second IC chip includes delay circuitry to generate the strobe signal by delaying an aperiodic timing signal for a first time interval and timing control circuitry to receive the phase error information from the first IC chip and adjust the first time interval in accordance with the phase error information.

Abstract: A memory device is provided. The memory device receives a main clock signal and provides an internal main clock signal; a data clock buffer to receive a data clock signal; and a latency control circuit configured to generate latency information based on the data clock signal and provide the latency information to a data circuit. The latency control circuit includes: a divider configured to generate divided-by-two clock signals based on the data clock signal; a divider configured to generate divided-by-four clock signals based on a first group of the divided-by-two clock signals; a first synchronization detector configured to output divided-by-two alignment signals indicating whether a second group of divided-by-two clock signals is synchronized with the data clock signal; and a latency selector configured to detect phases of the divided-by-four clock signals based on the divided-by-two alignment signals and adjust a latency of the main clock signal based on the phases.

Abstract: A memory system includes a logic circuit and a phase locked loop (PLL) circuit. The logic circuit determines a first frequency of a first clock using a first signal and generates a second signal for adjusting the first frequency of the first clock. The PLL circuit receives a second clock, and generates the first clock having the first frequency determined by the logic circuit, using the second clock and the second signal. When a second frequency of the second clock varies, the logic circuit determines the first frequency of the first clock such that the first frequency of the first clock generated by the PLL circuit is uniform, and operates based on the first clock having the first frequency adjusted by the second signal.

Abstract: An apparatus is provided which comprises: a power management circuitry; and a processing circuitry comprising a processing core, wherein the power management circuitry is to: compute first voltage and frequency parameters, and transmit the first voltage and frequency parameters to the processing circuitry for operation of the processing core, and wherein in response to a detection of a fault, the power management circuitry is to: access second voltage and frequency parameters from a memory, and transmit the accessed second voltage and frequency parameters to the processing circuitry for operation of the processing core.

Abstract: An integrated circuit for testing a circuit includes a controller configured to select a loopback path of the circuit. The circuit includes a data path and an inverter, and each is electrically coupled to the selected loopback path. The integrated circuit includes a counter electrically coupled to the selected loopback path. The circuit is configured to receive a first voltage signal that is either a substantially low logic level signal or a substantially high logic level signal. The circuit is configured to generate an oscillating signal from the first voltage signal, and the counter is configured to count oscillations of the oscillating signal.

Abstract: Systems, methods, and apparatus for internal on-chip clock calibration for devices coupled to a serial bus are described. A data line of the bus is monitored at a device in order to detect select command signals on the data line, where the select command signals have an accompanying clock signal, such as a burst clock, on a clock line of the serial bus sent concurrently with the command signal. The internal on-chip clock generator in the receiving device utilizes the clock signal occurring with the command signal for calibration, where the select signals are those signals sufficiently long enough for a receiving device to effectively utilize the concurrent clock signal for calibration purposes. In this manner, clock calibration for an internal clock is maintained accurately without the need for an extra clock calibration input.

Abstract: A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.

Abstract: Technologies for providing shared immutable code among untrusting domains are provided. The untrusting domains may be cryptographically separated within a cloud computing service or environment. The shared immutable code may be a shared virtual machine monitor (sVMM) that is setup by system software to indicate that the sVMM code pages need integrity alone and should be protected with an integrity key associated with individual domains. This indication may be stored in page tables and carried over the memory bus to a cryptographic engine. The cryptographic engine may use this indication to protect the integrity of data before storing the data to memory. In order to ensure cryptographic isolation, integrity values may be generated using a domain-specific key ensuring that an attempt to modify the code by one domain is detected by a different domain. Other embodiments are described herein and claimed.

Abstract: A method, apparatus, and system for multi-instance redo apply is provided for standby databases. A multi-instance primary database generates a plurality of redo records, which are received and applied by a physical standby running a multi-instance standby database. Each standby instance runs a set of processes that utilize non-blocking, single-task threads for high parallelism. At each standby instance for the multi-instance redo, the plurality of redo records are merged into a stream from one or more redo strands in logical time order, distributed to standby instances according to determined apply slave processes using an intelligent workload distribution function, remerged after receiving updates from remote instances, and applied in logical time order by the apply slave processes. Redo apply progress is tracked at each instance locally and also globally, allowing a consistent query logical time to be maintained and published to service database read query requests concurrently with the redo apply.

Abstract: A mobile industry processor interface MIPI clock frequency configuration method and apparatus are provided. When a radio frequency band used by a device on which an MIPI is located changes, an MIPI clock frequency is determined according to radio frequency band information, where the radio frequency band information includes the radio frequency band currently used by the device, and the determined MIPI clock frequency causes no interference to the radio frequency band currently used by the device; and an MIPI clock frequency of the device is configured as the determined MIPI clock frequency. According to the technical solutions in the present invention, when a radio frequency band of a device changes, an MIPI clock frequency causes no interference to communication of the device, thereby improving communication quality and stability of the device.

Abstract: A browser-based video editor is configured to allow a user to create a composition schema having multimedia layers, including video, audio, and graphic and text layers. The composition schema may be transmitted to a remote service that employs a rendering engine to play back the composition schema and align the clocks for each respective multimedia layer into a single video representation. A master clock object is employed to sync the clocks while also checking a series of properties with each multimedia layer to comport the multimedia layers with an interval-based master clock. The composition schema is recorded using FFmpeg (Fast Forward Moving Picture Experts Group) to create a video representation for user consumption, such as an MP4 (Motion Pictures Experts Group 4) formatted file.

Abstract: Techniques and mechanisms for determining a latency event to be represented in performance monitoring information. In an embodiment, circuit blocks of a pipeline experience respective latency events at variously times during tasks by the pipeline which service a workload. The circuit blocks send to an evaluation circuit of the pipeline respective event signals which each indicate whether a respective latency event has been detected. The event signals are communicated in parallel with at least a portion of the pipeline. In response to a trigger event in the pipeline, the evaluation circuit selects an event signal, based on relative priorities of the event signals, which provides a sample indicating a detected latency event. Based on the selected event signal, a representation of the indicated latency event in provided to latency event count or other value performance monitoring information. In another embodiment, different time delays are applied to various event signals.

Abstract: A GPGPU-compatible architecture combines a coarse-grain reconfigurable fabric (CGRF) with a dynamic dataflow execution model to accelerate execution throughput of massively thread-parallel code. The CGRF distributes computation across a fabric of functional units. The compute operations are statically mapped to functional units, and an interconnect is configured to transfer values between functional units.

Abstract: Clock-controlled circuitry organised into at least first and second clock domains, the first clock domain configured to operate based on a first clock signal and the second clock domain configured to operate based on a second clock signal, wherein: the first clock domain comprises a first signal generator operable to generate a first repetitive signal synchronised to the first clock signal; the second clock domain comprises a second signal generator operable to generate a second repetitive signal synchronised to the second clock signal; the first signal generator is operable, when operating in master mode, to output to the second signal generator a first synchronisation signal indicative of a phase of the first repetitive signal; and the second signal generator is operable, when operating in slave mode, to: set a timing of the second repetitive signal relative to the second clock signal based on the first synchronisation signal so that the second repetitive signal is set to have a phase relationship with the

Abstract: An event-driven simulation system is provided. The simulation system includes an accelerator that executes event-driven instructions based on a testbench of a design. The accelerator uses an event table to keep track of pending input events and to identify instructions that need to be executed. The instructions are group-sorted into groups of logically independent instructions, and the simulation accelerator determines which group of instructions to fetch and execute based on which groups of instructions have pending events. The event table has an instruction event table and a group event table. Each group has one respective corresponding bit in the group event table for indicating whether the group has at least one pending event in the current time step. Each instruction of each group has a corresponding bit in the instruction event table for indicating whether the instruction has at least one pending event in the current time step.

Abstract: An audio/video (A/V) hub that calculates an estimated location is described. In particular, the A/V hub may calculate an estimated location of a listener relative to electronic devices (such as electronic devices that include speakers) in an environment that includes the A/V hub and the electronic devices based on: communication with another electronic device; sound measurements in the environment; and/or time-of-flight measurements. Then, the A/V hub may transmit, to the electronic devices, one or more frames that include audio content and playback timing information, which may specify playback times when the electronic devices are to playback the audio content based on the estimated location. Moreover, the playback times of the electronic devices may have a temporal relationship so that the playback of the audio content by the electronic devices is coordinated.

Abstract: Aspects of the disclosed technology provide a method comprising executing different first and second instructions a first and second number of times, respectively, in repeated alternations. The method further comprises measuring spectra of signals emanating as a result of the processor executing the first and second instructions. The method also includes analyzing data indicative of the spectra of the signals to determine side-channel candidate side-band pairs that each have a lower and upper sideband at first and second frequencies, respectively, that are separated by approximately twice the respective alternation frequency. Finally, the method includes identifying a side-channel carrier frequency at a frequency approximately at a midpoint between a side-channel candidate side-band pair's first and second frequency.

Abstract: One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communications links in a memory system. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. In one embodiment, the Host only transmits data (and CRC) and does not transmit control signals, over its communications link with the data buffer circuits. In one aspect, the memory control circuit does not send the store data tag to the data buffer circuits. In one embodiment, the Host and the data buffer circuits each maintain a separate state machine-driven address pointer or local address sequencer, e.g., local store tag FIFO, which contains the same tags in the same sequence. A periodic system check and resynchronization method is also disclosed.

Abstract: A frequency divider circuit (200) includes a frequency sub-divider (201) to provide a frequency divided clock, a delay circuit (250) configured to delay the frequency divided clock by N+0.5 cycles of the input clock to generate a delayed clock, and an output circuit (202) configured to generate an output clock based on the frequency divided clock and the delayed clock, where the output clock has a frequency that is equal to 1/(N+0.5) times a frequency of the input clock, and N is an integer greater than one.

Abstract: Each processor core in a computing device supports various different frequency ranges, also referred to as p-states, and can operate to run threads at any one of those different frequency ranges. Threads in the computing device are assigned one of multiple importance levels. A processor core is configured to run at a particular frequency range or in accordance with a particular energy performance preference based on the importance level of the thread it is running. A utilization factor of a processor core can also be determined over some time duration, the utilization factor being based on the amount of time during the time duration that the processor core was running a thread(s), and also based on the importance levels of the thread(s) run during the time duration. The utilization factor can then be used to determine whether to park the processor core.

Abstract: A high frequency multichannel pulse width modulation (PWM) control apparatus includes a pre-scaler configured to divide a frequency of a main clock signal to generate a first clock signal, and a multichannel PWM generator including first to n-th PWM generators, the PWM generators comprising corresponding periods and duties, configured to generate, respectively, first to n-th PWM signals, through first and second N/2-bit counting for the main clock signal, using the first clock signal, wherein each of the first to n-th PWM generators performs the first N/2-bit counting on the main clock signal based on the first clock signal, a corresponding coarse duty value, and a corresponding coarse period value to generate a fine clock signal, and performs the second N/2-bit counting on the fine clock signal based on a corresponding fine duty value and a corresponding fine period value to generate a corresponding PWM signal.

Abstract: A timing method and a clock device are provided. The method includes: determining a timing point according to a timing duration of a clock device, where a clock period of the clock device is T, the timing duration is N times of a first time duration, and the first time duration is equal to Q2×T, where Q2=?Q1? or Q2=?Q1?, and Q1=C/T, N is a positive integer, Q1 is not an integer, and C is a constant (210); and performing one adjustment on timing time of the clock device each time P first time durations elapse, where an amount of time for each adjustment is one clock period T, P=1/|Q2?Q1| (220). Based on this method, accurate timing can still be effectively implemented when a ratio of a constant C (for example, 1.25 ms) to a clock period is not an integer.

Abstract: In one example in accordance with the present disclosure, a system for auto-negotiation over extended backplane includes an enclosure and a switch external to the enclosure. The enclosure has a NIC (network interface controller) for a server in the enclosure and a DEM (downlink extension module). The DEM has a single DEM PHY connected to the NIC via a backplane and also connected to the switch via an external connection. The DEM PHY facilitates auto-negotiation between the switch and the NIC.

Abstract: A control circuit includes a reset circuit and a determination circuit. The reset circuit is coupled to a digital frequency divider of a phase locked loop circuit and configured to perform a reset operation. The determination circuit is coupled to the reset circuit and configured to determine whether a first predetermined time interval has elapsed so as to control the reset circuit to stop performing the reset operation when the first predetermined time interval has elapsed.

Abstract: A method and system includes acquiring a seismic dataset while fluids are injected into the subsurface with seismic data recorded at multiple sensor locations. Seismic travel times are computed between sensors and subsurface locations using a velocity model. Travel times and travel time delays between pairs of sensors may be used as input to determine a similarity coefficient associated with subsurface positions. The similarity coefficients are determined using cross correlation, semblance calculations or eigenstructure decomposition. The coefficient values are related to the acoustic response at each subsurface position and may be summed together for each position for comparison with other subsurface positions to determine the position of a fluid front moving through the subsurface. The values may be displayed to illustrate the position of fluids in the subsurface and displayed to show the time variance of the fluid position.

Abstract: A payment terminal has a clock management unit for providing clock signals to components of the payment terminal. The payment terminal also has a wireless communication interface for communicating wireless signals. A processing unit of the payment terminal may monitor operation of a wireless communication interface of the payment terminal and, when the payment terminal is communicating wirelessly, modify an initial clock signal provided to one or more components of the payment terminal that emit RF noise to modify a frequency at which the RF noise occurs. When the payment terminal is no longer transmitting, the processing unit may provide the initial clock signal to the RF noise source.

Abstract: A memory device includes an internal clock generator, a deserializer, a data comparator, and a clock controller. The internal clock generator generates a plurality of internal clock signals, which have different phases from each other, by dividing a clock signal received from a host. The deserializer deserializes serial test data received from a host as pieces of internal data using the internal clock signals. The data comparator compares reference data with the internal data. The clock controller corrects a clock dividing start time point of the clock signal of the internal clock generator based on the result of the comparison of the reference data and the internal data.

Abstract: A disassemble monitoring device of an electronic device includes a detecting unit, a one time programmable register, a storage, and a processor. The detecting unit is configured to detect whether the electronic device has been disassembled, and upon detecting that the electronic device has been disassembled, generate a detection signal. The one time programmable register is electrically coupled to the detecting unit and is configured to change a storage value of the one time programmable register in response to the detection signal. The storage value can only be changed once. The processor retrieves the storage value from the one time programmable register in response to a user operation and determines whether the storage value has been changed. Upon determining that the storage value has been changed, the processor confirms a result of determination that the electronic device has been disassembled and outputs the result of determination.

Abstract: A signaling system is disclosed. The signaling system includes a first integrated circuit (IC) chip to receive a data signal and a strobe signal. The first IC includes circuitry to sample the data signal at times indicated by the strobe signal to generate phase error information and circuitry to output the phase error information from the first IC device. The system further includes a signaling link and a second IC chip coupled to the first IC chip via the signaling link to output the data signal and the strobe signal to the first IC chip. The second IC chip includes delay circuitry to generate the strobe signal by delaying an aperiodic timing signal for a first time interval and timing control circuitry to receive the phase error information from the first IC chip and adjust the first time interval in accordance with the phase error information.

Abstract: The present disclosure provides a gate driver on array (GOA) circuit, where the GOA circuit includes a GOA driving chip, a GOA driving signal line, an array substrate test chip, a test signal line, and a GOA protecting circuit. The GOA driving chip is used to generate a scan driving signal. The GOA driving signal line is used to transmit the scan driving signal to a corresponding scan line. The array substrate test chip is used to generate an array substrate test signal. The test signal line is used to transmit the array substrate test signal to the corresponding scan line. The GOA protecting circuit is arranged between the GOA driving signal line and the test signal line.

Abstract: Disclosed is a calibration unit for calibrating an oscillator of a device comprises a counting and comparing unit and a control circuit. The counting and comparing unit is configured to determine a number of periods of a clock signal lying between a starting instance and an ending instance. Therein, the clock signal is generated by the oscillator. The counting and comparing unit is further configured to determine a deviation of the number of periods from a reference number. The control circuit is configured to adjust the oscillator depending on the deviation.

Abstract: An integrated circuit includes a first multi-lane interface having a plurality of first lanes, a second multi-lane interface having a plurality of second lanes; a first layer of clock lane selection units arranged to select one or two of the first and second lanes and output signals on the one or two selected lanes; a second layer of clock lane selection units arranged to select the one or two selected lanes as one or two clock lane and output signals on the one or two selected clock lane; and a plurality of sampling units, each coupled to second layer of clock lane selection units, each arranged to sample one of the first and second lanes according to the signal on the selected clock lane.

Abstract: According to various embodiments, provided are an electronic device and a control method therefor, the electronic device comprising: a main body comprising at least one electronic component; a rotating body rotatably provided in a manner such that the rotating body encompasses at least a part of a region of the main body; a rotation detection means for detecting a rotation parameter of the rotating body; and at least one processor for performing a corresponding function of the electronic device on the basis of the detected rotation parameter.

Abstract: Provided is a technique that can generate a spread spectrum clock signal in all of an upper-spread mode, a down-spread mode, and a center-spread mode. A spread spectrum clock generator (2) spreads a spectrum of a signal with a predetermined carrier frequency to generate a spread spectrum clock signal under the control of a control unit (13). The control unit includes carrier frequency correction control means (13b). The carrier frequency correction control means shifts the predetermined carrier frequency to generate, from one spread mode, a spread spectrum clock signal of another pseudo spread mode.