Abstract: A system is disclosed that includes a memory, and a processor configured to perform operations stored in the memory. The processor performs the operations to analyze each of a first set of sequential elements of a plurality of sequential elements to determine an edge of a clock signal pattern of a clock associated with each of the first set of sequential elements causing an output change at corresponding one or more sequential elements of the first set of sequential elements. The processor further performs the operations to discard one or more cycles of the clock signal pattern of the clock from emulation that do not include the edge of the clock signal pattern that causes at least one sequential element of the first set of sequential elements to change the output and emulate remaining cycles of the clock signal pattern of the clock.

Abstract: A memory includes: an input circuit, configured to: receive an outside clock signal, and output a first test clock signal; a test path selection circuit, connected to the input circuit, and configured to output a second test clock signal according to a read clock command; and an output circuit, connected to the test path selection circuit, and configured to convert the second test clock signal into a third test clock signal and output the third test clock signal to outside of the memory. In the embodiments of the disclosure, a time delay of inputting a clock signal into each chip under test is quantified, to acquire an actual output delay of the chip, thereby improving the accuracy of parallel tests of a plurality of chips.

Abstract: A transmitter circuit includes a clock generator configured to generate a plurality of clock signals having different phases, and a plurality of selection circuits configured to receive a plurality of parallel data signals and output a serial data signal on an output node based on the plurality of clock signals and the received plurality of parallel data signals. Each of the plurality of selection circuits includes a data multiplexer configured to generate a plurality of data selection signals based on the received one of the plurality of parallel data signals and the plurality of clock signals; a control signal generator configured to generate first and second control signals based on the plurality of data selection signals; and an output driver connected to the output node, and configured to precharge the output node based on the first control signal or discharge the output node based on the second control signal.

Abstract: A semiconductor device includes clock adjustment circuits, provided to a plurality of functional circuits operating in synchronization with a clock signal respectively for adjusting a delay amount for each functional circuit, and a clock path selection circuit for controlling whether a clock is transmitted to the functional circuits through any one of a plurality of paths included in the clock adjustment circuits respectively. In the semiconductor device, the clock path selection circuit outputs a path instruction signal for instructing switching of a path for transmitting a clock signal in accordance with a change in an operation state of a plurality of functional circuits.

Abstract: A system includes a switching converter, an input voltage source coupled to an input of the switching converter, and a load coupled to an output of the switching converter. The system also includes a load sense circuit coupled to the load and configured to provide a load sense signal. The system also includes an oscillator coupled to the switching converter and configured to provide a spread spectrum modulated (SSM) clock signal to the switching converter, wherein a frequency of the SSM clock signal varies as a function of the load sense signal.

Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller and a media unit divided into a plurality of zones. Data associated with one or more first commands is written to a first portion of a first zone. Upon a predetermined amount of time passing, dummy data is written to a second portion of the first zone to fill the first zone to a zone capacity. Upon receiving one or more second commands to write data, a second zone is allocated and opened, and the data associated with the one or more second commands is written to a first portion of the second zone. The data associated with the one or more first commands is then optionally re-written to a second portion of the second zone to fill the second zone to a zone capacity, and the first zone is erased.

Abstract: There is provided mechanisms for initial access to a radio access network. The method is performed by a wireless device. The wireless device is configured for accessing the radio access network using at least a first cellular RAT and a second cellular RAT. The method comprises obtaining system information using a first carrier frequency and the first RAT. The system information comprises inter-frequency cell information of the second RAT. The method comprises synchronizing with the second RAT using a second carrier frequency based on the obtained system information in order to establish initial access to the radio access network. The second carrier frequency is higher than the first carrier frequency.

Abstract: Embodiments of the present invention relate to a method and a device for providing a clock signal to an application, comprising (a) determining a time difference between a clock device and the clock signal; if the time difference is above a predetermined threshold x, (b) calibrating a first time unit and, during calibrating the first time unit, (c) using a second time unit for providing the clock signal to the application.

Abstract: Apparatus (2) is described including one or more signal sources (6). The apparatus (2) also includes a measurement front end (7) having at least first (+Vin)) and second (?Vin) inputs. The apparatus (2) also includes a substantially planar connector (1) having a length (L) between first (1a) and second (1b) ends and supporting a number of conductors (3) spanning between the first (1a) and second (1b) ends. At each point between the first (1a) and second (1b) ends the conductors (3) are substantially equi-spaced from one another within the substantially planar connector (1). The conductors (3) include at least one signal conductor (8) connecting the signal sources (6) to the first input (+Vin). The conductors (3) also include at least two further conductors (10, 11) connecting to the one or more signal sources (6). One or both of the two further conductors (10, 11) also connect to the second input (?Vin).

Abstract: An example method includes receiving, by a mobile computing device, electrical power via a wireless charging link between the mobile computing device and a wireless charging device; and responsive to an activation state of a camera of the mobile computing device, selectively adjusting, by the mobile computing device, one or more parameters of the wireless charging link, wherein wireless charging via the wireless charging link with the adjusted one or more parameters generates less noise in images captured by the camera while the mobile computing device receives electrical power via the wireless charging link than wireless charging with unadjusted one or more parameters.

Abstract: An application level request associated with a portion of an application code requested to be executed with an adjusted hardware acceleration (wherein the portion of the application code is identified using a mechanism compatible with a plurality of different hardware processors) is received. It is determined whether to allow the adjusted hardware acceleration based at least in part on a configuration received via a network.

Abstract: Various embodiments are generally directed to techniques for memory access by a computer in a reduced power state, such as during video playback or connected standby. Some embodiments are particularly directed to disabling one or more memory channels during a reduced power state by mapping memory usages during the reduced power state to one of a plurality of memory channels. In one embodiment, for example, one or more low-power mode blocks in a set of functional blocks of a computer may be identified. In some such embodiments, the computer may include a processor, a memory, and first and second memory channels to communicatively couple the processor with the second memory. In many embodiments, usage of the one or more low-power mode blocks in the set of functional blocks may be mapped to a first address range associated with the first memory channel.

Abstract: An apparatus to facilitate source synchronous signaling is disclosed. The apparatus includes transfer protocol logic to provide for source synchronous transfer of data within an interconnect fabric, including one or more synchronizers having logic to a transmit data signal and a source clock (clk) signal during the transfer of data.

Abstract: A signal generator includes N stages of cascaded control signal generating circuits, and is configured to receive K clock signals whose valid pulse edges are different from each other by a set time, an n-th control signal generating circuit of the N stages of control signal generating circuit generates a strobe signal based on a k-th clock signal of the K clock signals and sequentially outputs at least two different clock signals of other K?1 clock signals based on the strobe signal. A valid pulse edge of the k-th clock signal is within a valid pulse duration of a strobe signal of an (n?1)-th stage control signal generating circuit.

Abstract: An image processing device includes: an image sensor; a data buffer; an imaging interface part configured to read image data from the image sensor, generate an imaging signal, and write the generated imaging signal to the data buffer; an imaging processor configured to read out the imaging signal written in the data buffer and perform image processing; a synchronization signal generator configured to generate a synchronization signal synchronized with the image sensor; and a clock frequency controller configured to control a clock frequency of a clock input to the imaging processor on the basis of the synchronization signal, wherein the clock frequency controller is configured to change the clock frequency after a start of a valid period of the synchronization signal.

Abstract: A display device comprises a display panel and a timing controller. The timing controller supplies gate timing signals to a gate driver as a sequence of clock pulses that sequentially select different ones of the display lines for receiving the data signals during the vertical active periods and for receiving a sensing signal during the vertical blanking intervals. The clock pulses have a first timing during the vertical active periods and the clock pulses have a second timing during the vertical blanking intervals in which the second timing is different than the first timing.

Abstract: A system may include an external apparatus and a semiconductor apparatus. The semiconductor apparatus may be configured to communicate with the external apparatus by receiving a frequency-varying first clock signal provided from the external apparatus.

Abstract: A method includes obtaining (i) an operating-temperature profile of a hardware processing sub-unit (HPSU) of a network element as a function of time, and (ii) a dependence of an Equivalent Reliability Time (ERT) of the HPSU on operating temperature. The operating-temperature profile is weighted using the dependence of the ERT on operating temperature, to estimate an effective ERT of the HPSU. An operating condition of the HPSU in the network element is modified, depending on the effective ERT.

Abstract: The embodiments described herein describe technologies of dynamic random access memory (DRAM) components for high-performance, high-capacity registered memory modules, such as registered dual in-line memory modules (RDIMMs). One DRAM component may include a set of memory cells and steering logic. The steering logic may include a first data interface and a second data interface. The first and second data interfaces are selectively coupled to a controller component in a first mode and the first data interface is selectively coupled to the controller component in a second mode and the second data interface is selectively coupled to a second DRAM component in the second mode.

Abstract: Memory devices, memory systems, and systems, include memory devices with a bonding pad region including two or more bonding pads for operably coupling to external signals and two or more command-and-address (CA) input signals. The memory device also includes a memory cell region for storing information in a plurality of memory cells. A centralized CA interface region including two or more CA input circuits operably coupled to the two or more CA input signals. The centralized CA interface region is positioned between the bonding pad region and the memory cell region in a layout arrangement with the two or more CA input circuits neighboring each other in a compact region such that clock routing to the two or more CA input circuits is substantially reduced.

Abstract: A clock generation circuit and a clock signal generation method are disclosed. In the method, a direct current bias circuit in a first clock source superimposes a first direct current voltage on a first clock signal output by a first oscillation circuit, to generate a second clock signal; and a logical operation is performed on the second clock signal and a third clock signal that is generated by a second clock source, to generate a fourth clock signal. The fourth clock signal is used as a signal output by a clock generation circuit. In the method, when the first oscillation circuit cannot normally work, the clock generation circuit can still output a correct clock signal. This avoids clock signal interruption when switching is performed from the first clock source to the second clock source.

Abstract: The vector data path is divided into smaller vector lanes. A register such as a memory mapped control register stores a vector lane number (VLX) indicating the number of vector lanes to be powered. A decoder converts this VLX into a vector lane control word, each bit controlling the ON of OFF state of the corresponding vector lane. This number of contiguous least significant vector lanes are powered. In the preferred embodiment the stored data VLX indicates that 2VLX contiguous least significant vector lanes are to be powered. Thus the number of vector lanes powered is limited to an integral power of 2. This manner of coding produces a very compact controlling bit field while obtaining substantially all the power saving advantage of individually controlling the power of all vector lanes.

Abstract: A method includes executing an initialization routine upon startup of a processor. The method includes executing a benchmark program during the initialization routine after the startup. The method further includes comparing an amount of time for execution of the benchmark program to a reference time to determine if the processor has slowed due to thermal degradation of heat removal components for the processor.

Abstract: A circuit includes a random oscillation number generator (RONG) configured to generate first and second pulse signals at first and second RONG outputs. A first counter is coupled to the first RONG output and generates a first count at a first counter output. A second counter is coupled to the second RONG output and generates a second count at a second counter output. A selection circuit is coupled to the first and second counter outputs and to the first and second RONG outputs. A first pulse shaper is connected between the first RONG output and the first counter, and a second pulse shaper is connected between the second RONG output and the second counter.

Abstract: A method of using a cryotherapeutic system in accordance with a particular embodiment includes advancing an elongate shaft of a catheter toward a treatment location within a body lumen of a human patient and directing a flow of refrigerant toward a cryotherapeutic element at a distal end portion of the shaft. The directed refrigerant is expanded to cause cooling within a balloon of the cryotherapeutic element. The pressure within the balloon is monitored and its rate of change calculated. The rate of change is then processed using different feedback loops during different monitoring windows of a treatment cycle. The individual feedback loops include an upper and a lower threshold and are configured to cause the flow of refrigerant to the cryotherapeutic element to stop if the rate of change falls outside a range between the upper and the lower threshold.

Abstract: An apparatus and method thermally manage a high performance computing system having a plurality of nodes with microprocessors. To that end, the apparatus and method monitor the temperature of at least one of a) the environment of the high performance computing system and b) at least a portion of the high performance computing system. In response, the apparatus and method control the processing speed of at least one of the microprocessors on at least one of the plurality of nodes as a function of at least one of the monitored temperatures.

Abstract: A method and an apparatus for clocking data processing modules, with different average clock frequencies and for transferring data between the modules are provided. The apparatus includes a device for providing a common clock signal to the modules. Clock pulses are deleted from the common clock signal to individual modules in dependence on the clocking frequency required by each module. The clock pulses are applied to the modules between which the data is to be transferred at times consistent with the data transfer.

Abstract: A method of clocking a plurality of programmable, sequential data processing units, by adjusting the clock frequency of at least one of the programmable, sequential data processing units, without affecting the clock frequency of at least one other of the programmable, sequential data processing units.

Abstract: In some aspects, a method for adjusting an operating frequency of a memory controller is provided, wherein a graphics processing unit (GPU) accesses a memory via the memory controller. The method includes monitoring activity of the GPU to determine an active time of the GPU, comparing the determined active time with an active threshold, and, if the determined active time is greater than the active threshold, increasing the operating frequency of the memory controller.

Abstract: Methods and systems for timing analysis and closure during logic synthesis of synchronous digital circuitry are provided, which may be used to prevent timing conflicts in logic designs that may have data transfers between regions with substantial clock skew. In programmable logic devices having hardened circuitry and programmable fabric, data transfers between memory elements in hardened circuitry and programmable fabric may be subject to substantial clock skews and unknown latencies. Embodiments may employ pre-calculated latencies that may be stored in a file and/or a database, and dynamically retrieved during timing synthesis to determine multicycle constraints to mitigate latencies. Embodiments may employ destination multicycle constraints, which use as reference the clock waveforms delayed due to latency.

Abstract: An apparatus, method and system is described herein for efficiently balancing performance and power between processing elements based on measured workloads. If a workload of a processing element indicates that it is a bottleneck, then its performance may be increased. However, if a platform or integrated circuit including the processing element is already operating at a power or thermal limit, the increase in performance is counterbalanced by a reduction or cap in another processing elements performance to maintain compliance with the power or thermal limit. As a result, bottlenecks are identified and alleviated by balancing power allocation, even when multiple processing elements are operating at a power or thermal limit.

Abstract: A clock diagnostic apparatus repeatedly acquires clock values at constant intervals by software. A clock diagnostic unit (103) selects, from among the clock values which are acquired by the software, two clock values having a gap between acquisition timings, the gap being a predetermined time period which is sufficiently large compared to jitter which occurs at a time of acquiring a clock value by the software. The clock diagnostic unit (103) calculates a difference between the two clock values selected.

Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.

Abstract: Systems, methods, and computer programs are disclosed for reducing dynamic random access memory (DRAM) power consumption within a selected voltage frequency/bin. One embodiment is a method comprising receiving a selected voltage/frequency bin for operating a memory bus electrically coupling a memory controller to a dynamic random access memory (DRAM). The method monitors a bandwidth of the memory bus while operating at the selected voltage/frequency bin. The method frequency switches a clock for the memory bus, based on the monitored bandwidth, between a plurality of predefined frequencies within the selected voltage/frequency bin to maintain a target bandwidth.

Abstract: Techniques for reducing power consumption of a storage controller are provided. An example method includes determining a back-end bandwidth of a storage system, wherein the back-end of the storage system includes a storage drive communicatively coupled to a storage controller. The method also includes determining a front-end bandwidth of the storage system, wherein the front-end of the storage system includes a front-end bus coupling the storage controller to a host. The method also includes computing a target back-end memory bandwidth based on the back-end bandwidth and computing a target front-end memory bandwidth based on the front-end bandwidth. The method also includes reducing power consumption of the storage controller by reducing a clock frequency of a memory device of the storage controller based on the greater of the target back-end memory bandwidth and the target front-end memory bandwidth.

Abstract: In a system for performing clock generation for each semiconductor device, synchronization between the semiconductor devices is achieved without causing a count value in a counter to be discontinuously changed.

Abstract: In one embodiment, a processor includes: at least one core to execute instructions; a power controller to control power consumption of the processor; and a storage to store a plurality of entries to associate a dynamic capacitance with a time duration for which a current spike is to be exposed to a power delivery component. Other embodiments are described and claimed.

Abstract: A power regulation system for a read channel of a data storage assembly includes a first voltage regulator for supplying power to the front-end decoder and a second voltage regulator for supplying power to the back-end codec. The second voltage regulator may conserve power reduce supply voltage to the back-end codec when the codec operates at a lower sampling frequency. The second voltage regulator may additionally increase supply voltage to the back-end codec in conjunction with an increase in sampling frequency. The system may additionally include a third voltage regulator for supplying a memory structure of the read channel with only the minimum required operating voltage to prevent leakage power.

Abstract: A transfer data generator creates transfer data that suppresses an increase in radiation noise generated when the transfer data is transferred to an ink head. The transfer data generator creates transfer data including transfer printing image data to be transferred to the ink head, and a transfer clock signal. The transfer data generator includes a clock signal creation processor that generates a pulse period of at least one pulse of a plurality of pulses of the reference clock signal different from each of pulse periods of the other pulses to generate the transfer clock signal from the reference clock signal, and a printing image data creation processor that adjusts the reference printing image data so as to correspond to the transfer clock signal to generate transfer printing image data.

Abstract: A system and method for controlling clock generation. A system includes a processor configured to execute instructions retrieved from memory, and a clock generation system coupled to the processor. The clock generation system is configured to generate a clock signal that the processor applies to execute the instructions. The clock generation system includes a plurality of configuration registers and selection circuitry. Each of the configuration registers includes fields that control a frequency of the clock signal. The selection circuitry selects which of the plurality of configuration registers determines the frequency at a given time.

Abstract: The present disclosure relates to a method for dynamically optimizing power consumption in a System-on-Chip (SoC). The method comprises receiving at least one interrupt signal from a peripheral controller. The method further comprises switching clock frequency of the peripheral controller to a lower clock frequency than a normal operating clock frequency upon receiving the at least one interrupt. The method further comprises providing the lower clock frequency than the normal operating clock frequency to the peripheral controller for dynamically optimizing the power consumption of the SoC.

Abstract: A method of error detection during a booting process of a computer system includes: for each of setting variables of a BIOS program, determining whether or not a respective one of stored values corresponding to the setting variable is in a respective one of value ranges corresponding to the setting variable according to a variable range comparison table; and when it is determined that for at least one of the setting variables, the stored value corresponding thereto is not in the respective one of the value ranges, updating, according to a variable definition file, the at least one of the setting variables using one of preset default values corresponding to the at least one of the setting variables.

Abstract: A subscription management service utilizes a timer service to maintain timers corresponding to subscription events. The subscription management service exposes an interface through which clients can define new subscriptions that are then created and managed by the subscription management service. The subscription management service can charge subscribers on an appropriate billing period, and cancel or automatically renew subscriptions at the end of a contract period. The subscription management service can also provide notifications to clients, to subscribers, and/or to other components. The subscription management service might also perform other types of actions with regard to the subscriptions on behalf of the clients. The timer service receives payloads from clients, such as the subscription management service, and provides the payloads back to the clients at a specified time. The timer service might also utilize a jitter threshold to compute the time at which payloads should be provided to clients.

Abstract: A system and method for thermal management of a memory device is described. In an embodiment, one or more thermal sensors sends a signal to a thermal control module indicating that a pre-determined temperature threshold for a memory device or devices has been reached. The thermal control module may then begin tracking memory thermals or initiate thermal management operations based on the signal and history of memory device temperatures over time.

Abstract: A memory circuit system and method are provided in the context of various embodiments. In one embodiment, an interface circuit remains in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for performing various functionality (e.g. power management, simulation/emulation, etc.).

Abstract: This invention relates to a clock circuit for providing an electronic device with a clock signal having an adjustable clock frequency. The clock circuit is adapted to receive information regarding a context level of the electronic device and to dynamically control the clock frequency of the clock signal according to the context level. The dynamical control of the clock circuit output frequency based on the context level enables automated power-to-performance control of the electronic device. The invention also relates to an electronic device comprising a context setting unit adapted to set a context level in which the electronic device is operated and a clock circuit. Furthermore, it relates to a method of providing an electronic device with a clock signal having an adjustable clock frequency, wherein a clock circuit receives information regarding a context level of the electronic device; and wherein the clock circuit dynamically controls the clock frequency of the clock signal according to the context level.

Abstract: A processing system with multiple processors is switchable between two modes of operation dynamically: symmetrical multi-processing (SMP) and asymmetrical multi-processing (ASMP). The system uses certain criteria to determine when to switch to improve the power consumption or performance. A controller enables control and fast-switching between the two modes. Upon receipt of a switching command to switch between SMP and ASMP, a series or sequence of actions are performed to control voltage supplies and CPU/memory clocks to the multiple processors and cache memory.

Abstract: A transmission apparatus includes: a plurality of first devices; and a second device configured to output a data signal shared by the plurality of first devices and respective first clock signals to each of the plurality of first devices, and to control the plurality of first devices individually based on the respective first clock signals.

Abstract: In at least some examples, a computing node includes a processor and a local memory coupled to the processor. The computing node also includes a reflective memory bridge coupled to the processor. The reflective memory bridge maps to an incoming region of the local memory assigned to at least one external computing node and maps to an outgoing region of the local memory assigned to at least one external computing node.

Abstract: An improved system and method for communicating Presence Information. According to various embodiments, the sequence of actions undertaken in established Presence procedures are changed, and enhancements are also provided for Watcher 5 information notifications. Upon the initiation of a Presence Service, the Presence Source starts publishing Presence Information about a Presentity using a soft-state approach. Instead of having publication occur first, the Presence Source makes a subscription for the Watcher information first or simply waits until the Presence Server contacts the Presence Source. As a result, publication occurs only when there is a demand therefor.