Abstract: A method and apparatus for providing an errands engine is described. The errands engine comprises an errand receiving logic to receive a set of tasks comprising an errand, a starting state identification logic to generate a characteristic function that describes a set of valid starting states, and a solution logic to generate a tour to complete the errand.

Abstract: An information recording method has blocking an information and adding an error correction code to the information so as to generate an ECC block, adding plural kinds of synchronizing signals SY differently arranged according to a type of an information recording medium D (FIG. 4) or plural kinds of synchronizing signals SY having a signal pattern according to the type of the information recording medium to the generated ECC block at an predetermined interval, and recording a recording signal based on the ECC block in the information recording medium, is provided. Even if the whole information of a ROM medium is illegally copied, since it is detected by the arrangement of the synchronizing signals in the reproduction that the medium is a rewritable medium, countermeasure such as abortion of the reproduction can be made.

Abstract: Various systems and methods for testing one or more servers using a distributed test system may involve a master agent synchronously transitioning multiple test agents through several state changes. In some embodiments, a method may involve configuring multiple test agents to execute a test by initiating a state change to a first state at each of the test agents. Each of the test agents is prepared to execute the test when in the first state. Each of the test agents simulates multiple clients of a server under test when executing the test. In response to each of the test agents confirming the state change to the first state, a state change to a second state may be initiated at each of the plurality of test agents. Each of the test agents executes the test when in the second state.

Abstract: Systems and methods for transient error recovery in pipelined reduced instruction set computer (RISC) processors prevent state changes based on the execution of an instruction until the execution of the instruction is validated. If a transient fault occurs causing an error to appear in an instruction execution, the instruction is retrieved using an instruction fetch address associated with that instruction and is stored in a pipeline history cache. The RISC processor pipeline is then restarted with that instruction. The validation of the execution of an instruction may take place in the execution stage, though processors with high clock frequencies may include a separate validate stage in the pipeline so that there is adequate time to validate the execution of the instruction without having to decrease the clock frequency.

Abstract: A memory device tester capable of testing for proper operation of reduced power states in memory devices. The memory device tester can include a processor or a state machine, each configured to send commands to the memory device, and to compare results. An example of a memory device that can be tested by the memory device tester is a Direct Rambus Dynamic Random Access Memory (DRDRAM). The described processing systems and other circuits can test a DRDRAM for proper operation in a standby (STBY) state. When the DRDRAM is in STBY, the column decoder is shut off to conserve power, and the DRDRAM should not respond to column packets on the column control bus. The method and apparatus provide for testing that the column decoder is shut off when in STBY with no banks active, which is the recommended usage pattern for the part.

Abstract: The present invention relates to a method and system for efficiently identifying errant processes in a computer system using an operating system (OS) error recovery method that identifies if the error caused by the errant process can be recovered and, if so, can recover from the error. The method and system of the present invention operates after standard Error Correcting Code (ECC) and parity check bit methods and systems are unsuccessful in recovering from the error In accordance with an embodiment of the present invention, the method and system includes detecting an error during instruction execution, storing a physical address of an errant process that caused the error, and storing an execution instruction pointer (IP) in an interruption instruction pointer (IIP).

Abstract: Systems and methods for network profiling that may be used by a provider of high bandwidth connections to facilitate connectivity and service order entry by customers are disclosed. Typically, the customer has a plurality of client. The network profiling method generally comprises specifying at least one network configuration profile, the specifying including selecting a preferred CPE, selecting a network mode, selecting a network feature, selecting at least one network feature parameter including a static parameter, and defining a value for the static network feature parameter, wherein the network configuration profile includes at least one dynamic network feature parameter, the dynamic parameter having an unspecified value in the network configuration profile.

Abstract: A network managing method which divides a network to be managed into a plurality of virtual closed area networks, and defines management information on the virtual closed area networks separately in a plurality of logical hierarchies. A virtual LAN/network space defines a connection state among closed area networks, a closed area space defines attribute information on nodes within a closed area network, and a virtual service defines logical arrangement information on nodes in the overall network. The management information is distributively stored in each node and utilized for MAC control. When the configuration of the network is changed due to movements of nodes, an administrator inputs the contents of the change from the manager of each layer, so that the manager communicates with a node containing corresponding management information to instruct the node to update management information.

Abstract: A warm start of a system is initiated with a warm start manager disabling incoming signals to the system and initiating at least a two-phase warm start procedure. In the first phase, being an intra-process phase, each process is checked for integrity of its own data structures. When data structures fail this check and cannot be recovered, a cold start is initiated. In the second phase, being an inter-process phase, entities that each process owns are checked to ensure that all other processes have a consistent image of the entities. Those entities that do not have a consistent image across the processes are removed. In an optional third phase of the warm start procedure, a determination is made as to which of the removed entities can be recreated immediately, and those entities are recreated.

Abstract: An invention is disclosed for recovering data in computer environment. Initially a record of historic states of a disk is created, wherein the disk includes various disk locations, such as a disk location X, a disk location Y, and a disk location Z. In response to a request to overwrite original data at the disk location X with new data, the new data is stored at the disk location Y. Then, an indication is established in the record of historic states that indicates the roles of disk location X and Y. These roles could establish the role of disk location X as including historic data, and the role of location Y as including new data for location X. In addition, the method includes intercepting a command to Ski release data at the disk location Z, and establishing an indication in the record of historic states indicating the disk location Z stores historic data.

Abstract: An electronic circuit package having a wiring substrate, at least two semiconductor chips and a bus line. All the semiconductor chips to be connected by means of the bus line are bare chip packaged on a wiring substrate, and the semiconductor chips and the wiring substrate are connected by wiring bonding between wire bonding pads formed on the semiconductor chips and the wiring substrate. The wiring substrate may be a multilayered substrate. Preferably, there is an insulating layer partially formed on the surface of the multilayer wiring substrate and a die bonding ground formed on the surface of the insulating layer, in order to use a portion of the multilayer wiring substrate under the die bonding ground as a wiring or a via hole region, and at least one of the semiconductor chips is formed on the die bonding ground.

Abstract: A computer system supports suspend operations to save power. The suspend operation maintains power to the system memory to enable a quick recovery from the suspend mode. To insure the accuracy of the data in system memory, a copy of the data is backed up to non-volatile memory, such as a hard disk drive, prior to entering the suspend mode. In addition, a signature value representing blocks or pages of memory also is saved with the data. When normal operation resumes, data in system memory is validated by calculating a new signature for each data block or page, and comparing it with the save signature values. If the signatures match, the data is assumed to be valid. If the values do not match, a restore operation proceeds to load the back up copy to that block of system memory. The algorithm may be run immediately upon resuming operation, or may run in the background when the CPU is idle.

Abstract: To provide a cache-tag control method capable of correcting an error and capable of keeping a high-speed operation of a system at the same time. A true-tag with a parity code attached and a shadow-tag having an inverted polarity of the true-tag are stored respectively in separate addresses within a cache tag-RAM. At the time of retrieving the tags, both the true-tag and the shadow-tag are checked respectively to see whether there is an error in each tag. When an error has been detected, a hit decision is made by using a tag in which there is no error. Further, data within the cache tag-RAM is updated by using the tag in which there is no error, thereby correcting the error.

Abstract: A new approach for asynchronous state-machine replication in a fault-tolerant system offers both integrity and high availability in the presence of Byzantine faults. The approach also improves the security of previous systems by recovering replicas proactively without necessarily identifying that they have failed or been attacked. This proactive recovery limits the time extent of a particular fault by regularly recovering replicas. In this way, the system works correctly even when all the replicas fail multiple times over the lifetime of the system, provided that less than ⅓ of the replicas are all faulty within a window of vulnerability.

Abstract: A network system includes a plurality of networks, a first internetwork apparatus having a plurality of first ports each connected to the plurality of networks, a second internetwork apparatus having a plurality of second ports each connected to the plurality of networks, and a data transmission path connected to the first and second internetwork apparatuses to transmit data mutually between the first and second internetwork apparatuses. In the normal state, each of the plurality of first ports is caused to be able to transmit and receive data to and from one of the plurality of networks and the plurality of second ports are caused not to be able to receive data from the plurality of networks and to be able to transmit data to the plurality of networks.

Abstract: A method and an apparatus checks the fine-grain correctness of a microcode machine central processor unit (CPU) behavioral model. Macroinstructions are decomposed into microinstructions and each microinstruction is executed sequentially. A sequence of microinstructions is determined by an emulated microinstruction sequencer, using dynamic execution information, including information from execution of prior microinstructions in the sequence of microinstructions. At the end of execution of each microinstruction, a reference state is compared to a corresponding state of the behavioral model, and any differences are noted. After execution of all microinstructions in the microinstruction sequence, a reference state is compared to a corresponding state of the behavioral model, and any differences are noted.

Abstract: A recovery logging method wherein when a node in a computer network becomes unavailable, file systems which require verification and are locked are logged in a recovery log and checking of other file systems continues. In this manner, the host node effectively utilizes time which would otherwise be spent waiting for a file system to become available. Upon completing available file system verifications, those file systems which were logged are checked for availability via background processing. When a logged file system becomes available, it is then verified. During the time spent waiting for a logged file system to become available, the affected node is available for other processing.

Abstract: A standalone virtual device driver that is not a mouse driver replacement or a mouse minidriver examines mouse data packets received from the mouse hardware for data packets that are obviously or likely to be faulty. When such a data packet is detected, the virtual device driver also removes the suspected faulty data by returning a null mouse packet to the mouse driver in its place. The virtual device driver may also initiate resynchronization procedures or reset the mouse hardware if necessary.

Abstract: A hard disk driver state detection method includes the step of connecting at least one hard disk to a respective SCA2 (single connector attach2) on a SCSI (small computer system interface) card, the step of connecting the SCSI card to a computer system detection main unit through a SCSI bus on the SCSI card, and the step of driving the computer system detection main unit to detect the at least one hard disk. In addition to the step of detecting the at least one hard disk, the detection method includes the step of reading signals from the at least one hard disk by using a 12C (inter-integrated circuit) circuit in the SCSI bus, the step of judging the state of the at least one hard disk subject to the nature of the signal received, and the step of turning on respective indicator lights on the SCSI card subject to the result of the judgement.

Abstract: In a pipelined computer architecture in which instructions may be removed from the instruction queue out of sequence, instruction queue status at a cycle K is determined by adding together the number of invalid instructions or free rows in the queue during cycle K−2, the number of instructions issued for cycle K−1 and the number of instructions speculatively issued in cycle K−1 that have produced a cache hit, and subtracting from the sum the number of instructions enqueued for cycle K−1. The result indicates the number of invalid instructions in the queue cycle K. The number of invalid entries instructions, the number of issued instructions, and the number of enqueued instructions are preferably represented as flat vectors, so that adding is performed by shifting in one direction, while subtracting is performed by shifting in the opposite direction.

Abstract: A device for ensuring specifically optimized error handling in complex systems, in particular in computer-supported medical diagnostic systems, characterized by a system-end storage and evaluation device (local error handler) having an error evaluation program which handles and stores local error messages and application programs according to specific rules, for automatically determining of when it is necessary to make contact with the server of a maintenance center, an update of the error software being carried out in the local error handler, when necessary, after a message has been checked.

Abstract: A system searches for, and verifies, according to certain criteria, a database of records, typically call records generated during the testing of a telecommunications network after software or hardware updates have been applied to the system. Multiple instances of collecting and decoding processes embodied in stored programs running in a computer system act upon blocks of incoming data records to store both a raw image of the received data and a pre-parsed version of the data suitable for database searching and retrieval. Three-step partitioned processing comprises a set of collector processes for collecting data records, a set of decoder processes for decoding and parsing such records, and a set of loader processes for loading records into a database. A client can request certain call records or request verification of certain records. A rules mechanism embodied in stored templates operates to tie client requests to asynchronously received data.

Abstract: An independent checkpointing method using a memory checkpoint on a distributed system that includes a message transmission routine, a message processing routine, and a periodical checkpoint routine. The message transmission routine adds a self checkpoint number to a message to be transmitted when a current process tries to send a message to another process. The message processing routine performs a memory checkpoint and processes a message in reference to a checkpoint number of a transmission process, a checkpoint number of the current process, a memory checkpoint flag, and a message transmission flag when a message is received from a process. The periodical checkpoint routine performs a checkpoint that records a necessary state information for recovery against faults periodically in reference to the memory checkpoint flag.

Abstract: The location of a bug resulting from processing a sequence of input files is determined by generating a potentially smaller sequence of the files which result in the bug. Such files can include data, instruction, or both. The smaller sequence can be determined by excluding portions from the sequence, and or returning portions to the sequence, and testing the sequence to determine if it results in the bug. In one embodiment of the present invention, excluded and returned portions become successively smaller by about a quotient of two. In another embodiment, individual files are excluded from a sequence of files, preferably in reverse order to their appearance in the sequence of files. The resulting sequence is tested to determine if it results in the bug. If not, the file can be returned to the sequence, and the bug location method continued with another file of the sequence.

Abstract: A memory device tester capable of testing for proper operation of reduced power states in memory devices. The memory device tester can include a processor or a state machine, each configured to send commands to the memory device, and to compare results. An example of a memory device that can be tested by the memory device tester is a Direct Rambus Dynamic Random Access Memory (DRDRAM). The described processing systems and other circuits can test a DRDRAM for proper operation in a standby (STBY) state. When the DRDRAM is in STBY, the column decoder is shut off to conserve power, and the DRDRAM should not respond to column packets on the column control bus. The DRDRAM Specification suggests that the DRDRAM be put in the STBY state with no banks active. The method and apparatus provide for testing that the column decoder is shut off when in STBY with no banks active, which is the recommended usage pattern for the part.

Abstract: A backup control system comprises a control package, a file package including a battery monitor and a flip-flop circuit, and a back board having a return wire which provides connection/disconnection of the monitor terminal of the monitor. The monitor checks a voltage of the monitor terminal at all times and outputs a reset signal to the flip-flop circuit when the voltage of the monitor terminal becomes lower than a reference voltage. The return wire connects the monitor terminal to the power line when the file package is connected to the connection board, and disconnects the monitor terminal from the power line when the file package is removed from the connection board. The flip-flop circuit stores one of a set state and a reset state, and changes in state from the set state to the reset state when the reset signal is received from the monitor.

Abstract: A computer system supports suspend operations to save power. The suspend operation maintains power to the system memory to enable a quick recovery from the suspend mode. To insure the accuracy of the data in system memory, a copy of the data is backed up to non-volatile memory, such as a hard disk drive, prior to entering the suspend mode. In addition, a signature value representing blocks or pages of memory also is saved with the data. When normal operation resumes, data in system memory is validated by calculating a new signature for each data block or page, and comparing it with the save signature values. If the signatures match, the data is assumed to be valid. If the values do not match, a restore operation proceeds to load the back up copy to that block of system memory. The algorithm may be run immediately upon resuming operation, or may run in the background when the CPU is idle.

Abstract: In a time-versioned storage mechanism, data is stored as a plurality of records, each including at least one attribute, a time span indicating the time span for which the attribute is valid, an insertion time indicating when the record was created, and a type field. The type field indicates whether the record is a concrete record, a delta record that possibly modifies the attribute value of a previous concrete or delta record, or an archive record replacing one or more records that have been archived. The data is accessed to find an attribute value from the point of view of a specified viewpoint time, by retrieving only records with insertion times not later than said viewpoint time, and constructing an attribute value from the retrieved records. The data is updated only by adding concrete records or delta records, without modifying attribute values in the concrete records or delta records.

Abstract: A data processor includes first and second devices that are coupled together via a signal path. The first device includes a first arithmetic unit. The first arithmetic unit performs an arithmetic operation on data to obtain a first result during an operation cycle, in which the first device transfers the data to the second device through the signal path. The first arithmetic unit outputs the first result onto the signal path during an idle cycle in which no data is transferred through the signal path. The second device includes second arithmetic unit and comparator. The second arithmetic unit performs the same type of arithmetic operation on the data, transferred through the signal path in the operation cycle, to obtain a second result. The comparator compares the first result, transferred through the signal path in the idle cycle, to the second result and outputs a comparison result.

Abstract: Disclosed is a device adapter for controlling devices in a network comprising computer processor nodes and one or more devices, the device adapter having means for determining whether or not a device state has changed after a failure. Responsive to a determination that the device state has not changed, the adapter communicates with other device adapters in the network to reestablish permissions before resubmitting I/O requests. Responsive to a determination that the device state has changed after a failure, the adapter reintegrates itself with the other device adapters in the network before reprocessing work as necessary.

Abstract: Systems and methods for transient error recovery in pipelined reduced instruction set computer (RISC) processors prevent state changes based on the execution of an instruction until the execution of the instruction is validated. If a transient fault occurs causing an error to appear in an instruction execution, the instruction is retrieved using an instruction fetch address associated with that instruction and is stored in a pipeline history cache. The RISC processor pipeline is then restarted with that instruction. The validation of the execution of an instruction may take place in the execution stage, though processors with high clock frequencies may include a separate validate stage in the pipeline so that there is adequate time to validate the execution of the instruction without having to decrease the clock frequency.

Abstract: Systems and methods for transient error recovery in pipelined reduced instruction set computer (RISC) processors prevent state changes based on the execution of an instruction until the execution of the instruction is validated. If a transient fault occurs causing an error to appear in an instruction execution, the instruction is retrieved using an instruction fetch address associated with that instruction and is stored in a pipeline history cache. The RISC processor pipeline is then restarted with that instruction. The validation of the execution of an instruction may take place in the execution stage, though processors with high clock frequencies may include a separate validate stage in the pipeline so that there is adequate time to validate the execution of the instruction without having to decrease the clock frequency.

Abstract: A method and apparatus for reverting a disk drive to an earlier point in time is disclosed. Changes made to the drive are saved in a circular history buffer which includes the old data, the time it was replaced by new data, and the original location of the data. The circular history buffer may also be implemented by saving new data elements into new locations and leaving the old data elements in their original locations. References to the new data elements are mapped to the new location. The disk drive is reverted to an earlier point in time by replacing the new data elements with the original data elements retrieved from the history buffer, or in the case of the other embodiment, reads to the disk are mapped to the old data elements stilled stored in their original locations. The method and apparatus may be implemented as part of an operating system, or as a separate program, or in the controller for the disk drive. The method and apparatus are applicable to other forms of data storage as well.

Abstract: A method and apparatus for reverting a disk drive to an earlier point in time is disclosed. Changes made to the drive are saved in a circular history buffer which includes the old data, the time it was replaced by new data, and the original location of the data. The circular history buffer may also be implemented by saving new data elements into new locations and leaving the old data elements in their original locations. References to the new data elements are mapped to the new location. The disk drive is reverted to an earlier point in time by replacing the new data elements with the original data elements retrieved from the history buffer, or in the case of the other embodiment, reads to the disk are mapped to the old data elements stilled stored in their original locations. The method and apparatus may be implemented as part of an operating system, or as a separate program, or in the controller for the disk drive. The method and apparatus are applicable to other forms of data storage as well.

Abstract: A method and implementing system are provided for handling detected faults in a processor to improve reliability of a computer system. An exemplary fault-tolerant on-line transactional (OLT) computer system is illustrated which includes first and second OLT processors connected to an I/O processor through a system bus. Transaction results are stored in local processor buffers and at predetermined batch intervals, the stored transactions are compared. The matched transaction results are flushed to data store while unmatched transactions are re-executed. If the same errors do not occur during a re-execution, the errors are determined to be transient and the transaction results are flushed to storage.

Abstract: A fault-tolerant transaction processing system and method stores records associated with operations of the system in order to permit recovery in the event of a need to roll back a transaction or to restart the system. At least some of the operational records are stored as a recovery log in low-speed non-volatile storage and at least some are stored as a recovery list in high speed volatile storage. Rollback of an individual transaction is effected by reference to the recovery list whereas restart of the system is effected by reference to the recovery log.

Abstract: A network system includes a plurality of networks, a first internetwork apparatus having a plurality of first ports each connected to the plurality of networks, a second internetwork apparatus having a plurality of second ports each connected to the plurality of networks, and a data transmission path connected to the first and second internetwork apparatuses to transmit data mutually between the first and second internetwork apparatuses. In the normal state, each of the plurality of first ports is caused to be able to transmit and receive data to and from one of the plurality of networks and the plurality of second ports are caused not to be able to receive data from the plurality of networks and to be able to transmit data to the plurality of networks.

Abstract: Logic circuitry (70, 80, 90) for performing fault detection in a microprocessor (5) is disclosed. The fault detection logic circuitry (70, 80, 90) may be implemented into a scheduler (50) in a floating-point unit (31). Mask register (M) bit positions (M.sub.0 through M.sub.7) store state information relative to registers (52) or other resources in the microprocessor (5) that is to be interrogated upon scheduling of an instruction. The instruction includes an encoded address communicated on register address lines (SA) that is received by the fault detection logic circuitry (70, 80, 90). Pass gates (72) are controlled by the encoded address on the register address lines (SA) to generate a fault indicator (FLT). Partitioning of the decoding of the encoded address may be utilized for optimization of the fault detection operation.

Abstract: A network managing method which divides a network to be managed into a plurality of virtual closed area networks, and defines management information on the virtual closed area networks separately in a plurality of logical hierarchies. A virtual LAN/network space defines a connection state among closed area networks, a closed area space defines attribute information on nodes within a closed area network, and a virtual service defines logical arrangement information on nodes in the overall network. The management information is distributively stored in each node and utilized for communication control and so on. When the configuration of the network is changed due to movements of nodes and so on, an administrator inputs the contents of update from the manager of each layer, so that the manager communicates with a node containing corresponding management information to instruct the node to update the management information.

Abstract: The start-up of a computer system takes place rapidly using a computer system having a recovery system which collects data for the recovery in parallel fashion in a common memory so that the data can be transferred to peripheral units of the computer system. The collection begins with collecting the data into a local memory of a processor and then transferring the data to the common memory before transferring the data to the peripheral units.

Abstract: A network system includes a plurality of networks, a first internetwork apparatus having a plurality of first ports each connected to the plurality of networks, a second internetwork apparatus having a plurality of second ports each connected to the plurality of networks, and a data transmission path connected to the first and second internetwork apparatuses to transmit data mutually between the first and second internetwork apparatuses. In the normal state, each of the plurality of first ports is caused to be able to transmit and receive data to and from one of the plurality of networks and the plurality of second ports are caused not to be able to receive data from the plurality of networks and to be able to transmit data to the plurality of networks.

Abstract: A method and apparatus for reverting a disk drive to an earlier point in time is disclosed. Changes made to the drive are saved in a circular history buffer which includes the old data, the time it was replaced by new data, and the original location of the data. The circular history buffer may also be implemented by saving new data elements into new locations and leaving the old data elements in their original locations. References to the new data elements are mapped to the new location. The disk drive is reverted to an earlier point in time by replacing the new data elements with the original data elements retrieved from the history buffer, or in the case of the other embodiment, reads to the disk are mapped to the old data elements stilled stored in their original locations. The method and apparatus may be implemented as part of an operating system, or as a separate program, or in the controller for the disk drive. The method and apparatus are applicable to other forms of data storage as well.

Abstract: A cache memory holds data of a disk unit on a track unit basis. Recording format information of the track in each disk unit is held in an LTD. For a write request from an upper apparatus, in case of a hit of the cache memory, a write cache control unit finishes a writing process on the cache memory and reports an end of process to the upper apparatus. In case of a mishit of the cache memory, a recording format is analyzed with reference to the LTD and a record position on the track to be developed in the cache memory is recognized, the writing process is finished on the cache memory and an end of process is reported to the upper apparatus.

Abstract: An information processing apparatus having a resume function which can maintain security even when a plurality of users use a common information processing apparatus. A work state at a power-off time is preserved together with a work state name including a user's ID in a different area in a plurality of preservation areas for the resume operation function on a main memory for each user. When a power source is turned on again, data in the preservation area corresponding to the user's ID is used to reproduce the work state of the user at the power-off time. A work state preservation file on a file server apparatus in a network has a resume function which does not need battery back-up. When this information processing apparatus is used, a work state at a power-off time can be independently preserved and reproduced for each of users, thereby realizing a resume function that is excellent in terms of security and utility.