Abstract: A parity generating circuit reverses generated parity data to detect a parity error of a CSE entry during a determination of completion to execute a command retry. A parity check circuit that detects a parity error requests for the execution of the command retry. When a command retry mechanism stops a program and interrupts a verification, the execution of the command retry is suppressed by assuming that no parity error is detected.

Abstract: An embodiment of a method of seeking consensus among computer processes begins with a first step of saving a new timestamp in a timestamp array for a particular process. The method continues with a second step of determining whether a most recent entry in a decision array includes a previously established consensus decision. In a third step, if the most recent entry does not include the previously established consensus decision, the method saves a proposed decision as a consensus decision. Otherwise, in a fourth step, the method saves the previously established consensus decision as the consensus decision. In a fifth step, if a most recent timestamp in the timestamp array continues to be the new timestamp, the method returns the consensus decision. Otherwise, in a sixth step, the method returns an abort indicator.

Abstract: Restoration of data is facilitated in the storage system by combining data snapshots made by the storage system itself with data recovered by application programs or operating system programs. This results in snapshots which can incorporate crash recovery features incorporated in application or operating system software in addition to the usual data image provided by the storage subsystem.

Abstract: A method of connecting a card to a terminal including the following steps: a) on receiving corresponding respective commands from the terminal, it modifies the contents of the card memory by provisionally recording in the card memory each of said interdependent items of information without losing prior values corresponding to said items; and then b) the modifications are finalized either by all of them being confirmed or by all of them being discarded.

Abstract: A method and apparatus for bidirectional provision of inline power over data telecommunications cabling permits power to be received at a local powered device (PD) from remote power sourcing equipment (PSE) via at least one conductor at a first time and power to be provided by the local device to the remote device or another device at a second different time.

Abstract: The storage control device and storage device error control method of the present invention prevent incorrect data from being read out to the host in advance, and thus improve the reliability. For example, the controller 5 that controls the disk array subsystem disperses and stores data on respective disks 1 through 3, calculates parity data, and stores this parity data on a disk 4. In cases where the updating of a certain block (D12) fails, so that data is not written into this block, this is an uncorrectable error. The data of this block (D12) is recovered on the basis of data and parity data stored on the other disks. The controller 5 also recovers data for another block (D13) following the block (D12) on the basis of other associated data and parity data. As a result, even if by some chance the block (D13) which has not suffered an uncorrectable error stores old data, the correct data can be recreated and provided to the host 7.

Abstract: A method for storing data includes writing the data to a temporary storage location and buffering a mirror request to copy the data from the temporary storage location to a mirror. Once all the data is present, the validity of the data is determined. If the data is valid, the mirror request is executed. Otherwise, the mirror request is deleted.

Abstract: The present invention controls storage apparatuses, and saves setting information of the storage apparatuses, transmits the saved setting information to the storage apparatuses, receives from the storage apparatuses results of processing for the setting information, retains the setting information for which the processing results are in error, and executes processing for the setting information with the error.

Abstract: A method and computer program product for error monitoring partitions in a computer system. Provided to each partition is a partition status indicator (PSI) denoting a RUNNING or FAIL status of the partition, and an error log area (ELA) for storing partition error entries. The ELA includes a partition identifier, an entry status indicator (ESI) indicating READ/UNREAD status for the error entry, and an error identifier. An error procedure performed for each first partition whose partition status indicator indicates the FAIL status includes: copying each error entry in the ELA of the first partition whose ESI indicates the UNREAD status into the ELA of a second (running) partition; setting the ESI to the READ status for each copied error entry in the ELA of the first partition; and having the ESI set to the UNREAD status for each copied error entry in the ELA of the second partition.

Abstract: A media drive having a front panel for displaying historical event information associated with the media drive is provided. The media drive includes a front panel portion having a plurality of indicia for displaying information in a binary format. In one example, the indicia include a plurality of light emitting diodes (or other light sources) for representing the binary data. The media drive further includes a drive controller having display logic for selectively addressing the plurality of indicia to display historical event information associated with the media drive. The historical event information may include historical events (e.g., types or categories of historical events) as well as detailed error codes associated with the historical events (e.g., more detailed information relating to the status or error of the particular historical event).

Abstract: Recording resource limitation resolution is described. In one implementation a time period is detected during which programs are designated to be recorded, and during which at least one of the designated programs cannot be recorded due to a recording resource limitation. All possible combinations to record the designated programs which will resolve the recording resource limitation can be determined using an iterative selection process. A recording conflict user interface is displayed, and any one of the possible combinations which will resolve the recording resource limitation can be selected via the recording conflict user interface. Other implementations are also described.

Abstract: A new method for the detection and correction of errors or faults induced in a computer or microprocessor caused by external sources of single event upsets (SEU). This method is named Time-Triple Modular Redundancy (TTMR) and is based upon the idea that very long instruction word (VLIW) style microprocessors provide externally controllable parallel computing elements which can be used to combine time redundant and spatially redundant fault error detection and correction techniques. This method is completed in a single microprocessor, which substitute for the traditional multi-processor redundancy techniques, such as Triple Modular Redundancy (TMR).

Abstract: Mechanisms for adaptively entering and exiting recovery mode. When a message is received from a particular message transaction, the appropriate processing instance is loaded from persistent memory to system memory. The processing instance then determines from its own state information whether or not it is in recovery mode. This indication of recovery or normal mode may be set by a system-wide recovery detection module. If the processing instance determines that it is in normal mode, then the processing instance executes code appropriate for normal operation without needing to execute any recovery code at all. If, on the other hand, the processing instance determines that it is in recovery mode, then it executes recovery code. Once the recovery code has completed successfully, the processing instance may then cause its own normal mode.

Abstract: Diagnostic information is produced from a computer memory operably connected to a DBMS. A command is received from a user wherein the command comprises an identifier of a resource associated with the DBMS. The identifier is utilized to determine one or more control blocks residing within the computer memory and wherein the one or more control blocks are related to the resource. The memory locations occupied by the one or more control blocks are determined and the contents of the memory locations are then copied to a target destination. In this manner, the target destination forms a logical dump containing the diagnostic information.

Abstract: A system consistency management module that performs consistency checking on behalf of an instance. The module identifies data fields of state information corresponding to the instance that are to be subject to consistency checking. The instance may identify this data fields to the system module. The system module may also identify an event that will prompt the consistency checking. When the event occurs, the system module performs the consistency checking on the identified fields. If the system module detects an inconsistency, it may set the state information to reflect that the instance is operating in recovery mode. If the instance itself was to perform the consistency checking, the instance may inform the system module that an inconsistency has been detected. The system module then sets the state information for the instance to reflect that the instance is operating in recovery mode.

Abstract: A data storage system has a first storage processor, a second storage processor, and a communications subsystem. The communications subsystem has (i) an interfacing portion interconnected between the first storage processor and the second storage processor, (ii) a clock circuit coupled to the interfacing portion, and (iii) a controller coupled to the interfacing portion and the clock circuit. The controller is configured to enable operation of the interfacing portion to provide communications between the first and second storage processors, sense a failure within the clock circuit, and reset the interfacing portion in response to the sensed failure to enable one of the first and second storage processors to continue operation. Such resetting of the interfacing portion prevents the remaining storage processor from locking up, thus freeing that storage processor so that it is capable of continuing to operate even after the failure.

Abstract: A maintenance system of a hydraulic excavator (11) is provided with a maintenance monitoring device (21), a maintenance management server (12) for managing trouble information and operating information for each working machine, a model information server (13), and a service personnel mobile terminal (14) connected to one another through the Internet (15). When trouble occurs in the hydraulic excavator, the maintenance system (21) transmits trouble information to the maintenance management server (12), and the maintenance management server (12) transmits information on occurrence of trouble to the mobile terminal (14) and displays it on a display unit. This system manages the maintenance manuals and other data for each model in a model information database separate from the maintenance database and correlates the two databases based on the model data.

Abstract: In a network routing system,a control blade provides for redundancy and failover of virtual routers (VRs) instantiated by objects running on processing engines of the several virtual routing engines (VREs). When the control blade detects a failure of one processing engines, it may identify the virtual private networks (VPNs) and/or VRs operating on the failed processing engine. The control blade identifies a set of command lines corresponding with the identified VPNs and VRs, and replays the set of command lines with an identity of a new processing engine to recreate the identified VPNs and VRs on the new processing engine.

Abstract: Methods and systems are provided by which a flexible, efficient and easy-to-use real-time enterprise management system is provided. The methods and systems provided can effectively monitor and manage the resources and events of each of a plurality of computers within a fluidly changing network environment (e.g. client/server and peer-to-peer networks). Also provided are methods and systems which allow an individual computer to determine whether or not its current performance characteristics vary from their acceptable parameters without having to contact any other computer. Finally provided are methods and systems by which computers can analyze and store data regarding their performance characteristics in real time.

Abstract: A non-hardened processor is made fault tolerant to SEUs and SEFIs. A processor is provided utilizing time redundancy to detect and respond to SEUs. Comparison circuitry is provided in a radiation hardened module to provide special redundancy with the need to run additional processors. Additionally, a hardened SEFI circuit is provided to periodically send a signal to the process which, in the case of a processor not in the SEFI state, initiates production by the processor of a “correct” response. If the correct response is not received within a particular time window, the SEFI circuit initiates progressively severe actions until a reset is achieved.

Abstract: A method and apparatus to recover a set of data from a full backup and an incremental or differential backup are described. This includes a source directory that was modified between the full backup and the incremental or differential backup. The full backup is restored, including the source directory, and a new directory is created to replace the restored directory when the incremental or differential backup is applied to the restored full backup. Content for an entry from the modified source directory in the incremental or differential backup is created in the new directory if the corresponding content is present in the incremental or differential backup. If the content for the entry is not present in the incremental or differential backup, then the entry in the new directory is linked to corresponding content in the restored directory from the full backup.

Abstract: A new method for the detection and correction of environmentally induced functional interrupts (or “hangs”) induced in computers or microprocessors caused by external sources of single event upsets (SEU) which propagate into the internal control functions, or circuits, of the microprocessor. This method is named Hardened Core (or H-Core) and is based upon the addition of an environmentally hardened circuit added into the computer system and connected to the microprocessor to provide monitoring and interrupt or reset to the microprocessor when a functional interrupt occurs. The Hardened Core method can be combined with another method for the detection and correction of single bit errors or faults induced in a computer or microprocessor caused by external sources SEUs.

Abstract: Mechanisms for adaptively entering and exiting recovery mode. When a message is received from a particular message transaction, the appropriate processing instance is loaded from persistent memory to system memory. The processing instance then determines from its own state information whether or not it is in recovery mode. This indication of recovery or normal mode may be set by a system-wide recovery detection module. If the processing instance determines that it is in normal mode, then the processing instance executes code appropriate for normal operation without needing to execute any recovery code at all. If, on the other hand, the processing instance determines that it is in recovery mode, then it executes recovery code. Once the recovery code has completed successfully, the processing instance may then cause its own normal mode.

Abstract: Systems and methods for asynchronous multi-channel data communications are provided. An embodiment of the invention includes a minimum of three channels for digital computation in Primary Flight Computers and four channels for digital/analog conversion in Actuation Control Electronics. Each channel (Primary Flight Computer or Actuation Control Electronics) contains two computation lanes with dissimilar processors and compilers. Hence with dual-dissimilar processors the computer architecture is fail-passive to generic errors. The two Actuation Control Electronics computation lanes select the digital control data of one of the two computation lanes of one of the three digital computation channels for conversion and transmission to associated actuators.

Abstract: Restoration of data is facilitated in the storage system by combining data snapshots made by the storage system itself with data recovered by application programs or operating system programs. This results in snapshots which can incorporate crash recovery features incorporated in application or operating system software in addition to the usual data image provided by the storage subsystem.

Abstract: A system and method for fault-tolerant synchronization of replica updates for fixed persistent consistency point image consumption. PCPIs are consumed at a fixed level and each coalesced PCPI presents a valid version of the source file system from some point in time. The qtrees concurrently move through a coalescing cycle wherein some qtrees are updated, some may update partially and some may not update at all. Partially updated qtrees are rolled-back to the previous state, after which all qtrees are transitioned to a stable state.

Abstract: A memory device tester capable of testing for proper operation of reduced power states in memory devices. The memory device tester can include a processor or a state machine, each configured to send commands to the memory device, and to compare results. An example of a memory device that can be tested by the memory device tester is a Direct Rambus Dynamic Random Access Memory (DRDRAM). The described processing systems and other circuits can test a DRDRAM for proper operation in a standby (STBY) state. When the DRDRAM is in STBY, the column decoder is shut off to conserve power, and the DRDRAM should not respond to column packets on the column control bus. The method and apparatus provide for testing that the column decoder is shut off when in STBY with no banks active, which is the recommended usage pattern for the part.

Abstract: A data processor formed on a single integrated circuit and capable of connection to an external memory, the data processor including: a central processing unit; a local memory including a debug memory area; a plurality of interrupt inputs; an interrupt handler coupled to the interrupt inputs for interrupting the central processing unit in response to interrupt signals received on the interrupt inputs, and being arranged to periodically store in the debug memory area of the local memory data indicative of the status of the interrupt handler; the data processor being adapted to, after having been reset, perform a start-up routine including the step of outputting the contents of the debug memory area to the external memory.

Abstract: The present invention relates generally to database and file system management and, more particularly, to automatic database and file system maintenance and repair to ensure data reliability. Various aspects of the present invention relate to responding and correcting data corruptions at a data page level for all data page types, as well as to recovery (including rebuild or restore operations) for various scenarios including, without limitation, index page corruptions (clustered and non-clustered), data page corruptions, and page corruptions in the log file.

Abstract: Disclosed is a technique for processing interruption of an operation that transfers data between a source and a target. An indication that a reverse restore operation has been interrupted is received. It is determined whether designation of at least one of an original source and an original target has been reversed. The settings of one or more relation indicators are also determined. Processing to be performed is identified based on the determinations of whether designations have been reversed and based on the settings of the one or more relation indicators.

Abstract: Writing in each sector of a series of sectors of a recording medium in which data is to be written caused by a single data write request location information which is information indicating a location of the sector in the series of sectors and common information which varies every time data writing to the series of sectors occurs and is information set relating to the series of sectors.

Abstract: A method, system and computer program product for implementing a fault tolerant sleep mode of operation. The system state information may be stored in a volatile memory and in a non-volatile storage unit prior to entering the sleep mode of operation. If a memory corruption event, e.g., power outage, brownout, power surge, occurs during the sleep mode of operation, then, upon receiving an invocation to resume to a normal mode of operation, the system state information stored in the non-volatile storage unit may be reloaded into the volatile memory. By reloading the system state information stored in the non-volatile storage into the volatile memory, the computer system may resume to a normal mode of operation from a sleep mode of operation without any corruption or loss of data.

Abstract: In a network routing system, a control blade provides for redundancy and failover of virtual routers (VRs) instantiated by objects running on processing engines of the several virtual routing engines (VREs). When the control blade detects a failure of one processing engines, it may identify the virtual private networks (VPNs) and/or VRs operating on the failed processing engine. The control blade identifies a set of command lines corresponding with the identified VPNs and VRs, and replays the set of command lines with an identity of a new processing engine to recreate the identified VPNs and VRs on the new processing engine.

Abstract: In a data center, when a server is disconnected from the Internet because of illegal manipulation of a file, valid files (not manipulated) are copied to a standby server and the processing is resumed after a short period of disconnection. According to the invention, a control program P10 performs manipulation checks for all files listed in a manipulation checklist. If any of them is manipulated, it issues a request to disconnect from the external network and a request to assign a standby server to a control program P20 of a management server. Upon receipt of a disconnection completion signal and the address of a standby server b0, the control program P10 copies valid files (not manipulated) to the standby server b0, and for invalid files, requests the copies of their backup files. After finishing copying, the management server connects the standby server b0 to the external network to resume processing.

Abstract: The invention presents a programmable communication system for generating data for at least one processing unit at a fixed symbol frequency, which lies within a range of frequencies, on the basis of input samples received at an input frequency higher than the symbol frequency. To achieve this, communication time slots are reserved periodically as a function of the maximum envisaged symbol frequency, and the device is designed for using only a fraction of these slots reserved as a function of the fixed symbol frequency for transmitting the generated data. The invention is applicable to broadband digital communications, digital television, channel decoding, demodulation and other similar technology areas.

Abstract: A method for auditing and reconciliation of a network with a network model that includes identifying an audit state for each network resource included in the network model, storing the audit state for each resource, coupling the stored audit state information with information regarding the resource, reporting a calculated value reflecting the aggregate audit states of the resources, monitoring the calculated value, and triggering a reconciliation process when the calculated value drops below a defined threshold. The calculated value can be a best-case aggregate accuracy percentage, worst-case aggregate accuracy percentage, or presumed average aggregate accuracy percentage. The audit state can be stored as an additional field in the primary data store for the network model or in a separate data store that is associated with the primary data store. The audit state can be unconfirmed, confirmed, or suspect. The audit state is used to trigger and/or measure audit and reconciliation processes.

Abstract: A command transmission/reception section (4R), a power-control determination section (8) and a power control section (9) are provided in a controlled device (3) which is connected to a network (1) and which performs power control in response to a command transmitted from a control device (2). Upon receipt of a power control command from the control device (2), the power-control determination section (8) determines as to power-on/power-off in units of a block, and performs power control on the basis of a result of the determination. Consequently, unnecessary power-on in, for example, video reservation can be prevented.

Abstract: A microprocessor based system automatically detects the occurrence of certain conditions in the microprocessor. The conditions may include a determination of data corruption in the microprocessor. If a determination is made that data is corrupted, the microprocessor may be reloaded from a non-volatile memory. During a reload, a microcontroller controls the microprocessor. The non-volatile memory may be a flash memory or non-volatile random access memory.

Abstract: The present invention relates to systems and methods to port controller state and context via non-volatile portable memory to controllers employing an open operating system. The present invention provides for saving a controller's state and context, for example after the controller has been suitably configured. The saved image can then be employed for subsequent controller startups to resume a particular state and context, utilized during maintenance to return a controller to a previously saved state and context, and employed to efficiently configure similar controllers via porting and/or loading the saved image to the similar controllers, which mitigates manual controller configuration. The present invention can be employed in connection with various industrial controller designs, memory configurations, and data transfer techniques. In addition, the present invention provides for serial and/or concurrent state and context transfers between controllers and memory devices.

Abstract: Setting a plurality of table entries in a storage device includes subdividing the table entries into a N tasks, placing each of the N tasks in a memory location disposed within the storage device and accessible by a plurality of internal devices, the plurality of the internal devices accessing the memory location to retrieve at least one of the N tasks, and each of the plurality of the internal devices setting table entries corresponding to at least one of the N tasks retrieved from the memory location. Setting table entries may also include setting logical device table entries to indicate corresponding tracks contain invalid data in connection with operation of remote data transfer between multiple storage devices.

Abstract: A vehicle electronic controller for checking a control microcomputer with a common monitoring IC, which is used in different vehicles. The vehicle electronic controller includes a control microcomputer, which calculates control data to control an actuator installed in a vehicle in accordance with a driving condition of the vehicle, and a monitoring IC, which is connected to the control microcomputer and checks whether or not the control data is normal based on a determination value. The control microcomputer provides the determination value to the monitoring IC. The monitoring IC includes a memory device, which stores the determination value in a rewritable manner. The monitoring IC receives the determination value and stores the determination value in the memory device.

Abstract: A reconfigurable logic signal processor system (RLSP) (100) and method of error checking same in accordance with certain embodiments of the present invention loads configuration data capable of processing an air interface or portion thereof in a wireless system from a configuration storage memory (112) into reconfigurable resources (104), reads back the configuration data from the reconfigurable resources (104), reads expected results from the configuration storage memory (112), and executes a verification algorithm on the configuration data read back from the reconfigurable resources (104). A portion of the reconfigurable resources (104) of the RLSP system (100) may be utilized to implement the error checking upon itself. If an error is found in the configuration data, steps can be taken to activate another base configuration data to implement a functional base air interface in a wireless communication system and request downloading (if available) from the network of the erroneous configuration data.

Abstract: A TCP Offload Engine (TOE) device includes a state machine that performs TCP/IP protocol processing operations in parallel. In a first aspect, the state machine includes a first memory, a second memory, and combinatorial logic. The first memory stores and simultaneously outputs multiple TCP state variables. The second memory stores and simultaneously outputs multiple header values. In contrast to a sequential processor technique, the combinatorial logic generates a flush detect signal from the TCP state variables and header values without performing sequential processor instructions or sequential memory accesses. In a second aspect, a TOE includes a state machine that performs an update of multiple TCP state variables in a TCB buffer all simultaneously, thereby avoiding multiple sequential writes to the TCB buffer memory. In a third aspect, a TOE involves a state machine that sets up a DMA move in a single state machine clock cycle.

Abstract: Processor implementation-specific instructions save a processor state in a system memory and attempt to correct the error. Control is then transferred to processor-independent instructions. Control is returned to the processor implementation-specific instructions which then return to an interrupted context of the processor by restoring the processor state.

Abstract: Setting a plurality of table entries in a storage device includes subdividing the table entries into a N tasks, placing each of the N tasks in a memory location disposed within the storage device and accessible by a plurality of internal devices, the plurality of the internal devices accessing the memory location to retrieve at least one of the N tasks, and each of the plurality of the internal devices setting table entries corresponding to at least one of the N tasks retrieved from the memory location. Setting table entries may also include setting logical device table entries to indicate corresponding tracks contain invalid data in connection with operation of remote data transfer between multiple storage devices.

Abstract: A data processing system participating in two-phase transaction processing operations which, when a system failure occurs while one or more transactions are in process, can successfully rebuild “in-doubt” states even when another system failure occurs during an attempt to effect the rebuild. The system includes a file management system having exclusive access to reserved locations in the memory for reading and writing meta-data therein and physical file access logic selectively coupling the memory and the database access application, the physical file access logic incorporating file protections which are controlled by the file management system; such that, in the event of a failure, the local state of the transaction can be faithfully rebuilt after restart by accessing the meta-data.

Abstract: The present invention provides a system and method for analyzing hardware alarms in a telecommunications digital cross-connect system. The present invention also relates to a system and method for automating the process of analyzing hardware failures that cause path and parity alarms in a telecommunications digital cross-connect system used in a long distance network.

Abstract: In an image forming apparatus for forming an image in accordance with control codes stored in a plurality of memory media, when the control codes stored in the plurality of memory media to control the image forming apparatus is rewritten, rewrite execution codes adapted to execute rewrite of the control codes are transferred to predetermined one of the plurality of memory media from an external apparatus, and rewrite of the control codes is performed in accordance with the transferred rewrite execution codes.

Abstract: A method and system for updating status information in a persistent storage. The method comprises the steps of defining a table in persistent storage (NVS) for holding information about changes to the status information; and when that status information is changed, making an entry in the table to record the changed information. A task is initialized to update the information on the disk drive. This updating is done by (i) checking the table to determine if any changes have been recorded in the persistent storage, and (ii) if any changes have been recorded in the persistent storage, then copying the status information from the persistent storage to the disk drive.

Abstract: A method and apparatus for providing an errands engine is described. The errands engine comprises an errand receiving logic to receive a set of tasks comprising an errand, a starting state identification logic to generate a characteristic function that describes a set of valid starting states, and a solution logic to generate a tour to complete the errand.