Abstract: Method, systems and apparatuses may provide for technology that identifies first data and second data to be stored in a data storage. Each of the first data and the second data are in a first data format. Some technology may also interleave the first data with the second data. The interleaved first and second data are in a second data format. The second data format is different from the first data format.

Abstract: High-throughput software-defined convolutional interleavers and de-interleavers are provided herein. In some examples, a method for generating convolutionally interleaved samples on a general purpose processor with cache is provided. Memory is represented as a three dimensional array, indexed by block number, row, and column. Input samples may be written to the cache according to an indexing scheme. Output samples may be generated every MN samples by reading out the samples from the cache in a transposed and vectorized order.

Abstract: A coded bit transmission method and apparatus, to improve spectrum resource utilization and a data rate of a Wi-Fi system, where the method includes: A sender performing channel coding on information bits according to a used MCS, to generate coded bits; and the sender distributing the coded bits to a plurality of channel sets or a plurality of resource units according to a distribution rule. The MCS is an MCS used for each of the plurality of channel sets, or an MCS used for each of the plurality of resource units.

Abstract: Numerous embodiments are disclosed of improved architectures for storing and retrieving system data in a non-volatile memory system. Using these embodiments, system data is much less likely to become corrupted due to charge loss, charge redistribution, disturb effects, and other phenomena that have caused corruption in prior art non-volatile memory systems.

Abstract: A storage device including a nonvolatile memory device, a dynamic random access memory (DRAM) device, and a storage controller, an operation method of the storage device including performing an access operation on the DRAM device, collecting accumulated error information about the DRAM device based on the access operation, detecting a fail row of the DRAM device based on the accumulated error information, and performing a runtime repair operation on the detected fail row.

Abstract: A data processing circuit includes a plurality of transformation blocks suitable for respectively transforming in parallel a plurality of input bit groups into a plurality of output bit groups, wherein each of the transformation blocks transforms a corresponding input bit group into a corresponding output bit group by using a random pattern.

Abstract: A bit interleaving method involves applying a bit permutation process to bits of a QC-LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the codeword after the permutation process into a plurality of constellation words each including M bits, the codeword being divided into F×N?/M folding sections (N? being a subset of N selected cyclic blocks and being a multiple of M/F), each of the constellation words being associated with one of the F×N?/M folding sections, and the bit permutation process being applied such that each of the constellation words includes F bits from each of M/F different cyclic blocks in a given folding section associated with a given constellation word.

Abstract: A method, apparatus and computer program product providing improved communication performance through network coding is presented. Coded packets are formed at a source node, the coded packets comprising a combination of original packets at the source node. The coded packets are transmitted to at least one destination node using an unreliable protocol. A reconstruction is formed based on received coded packets at the destination node, wherein when a number of received coded packets are equal to the number of transmitted coded packets the forming a reconstruction comprises forming a complete reconstruction and wherein when the number of received coded packets is less than the number of transmitted coded packets the reconstruction comprises forming a best attempt at reconstruction.

Abstract: An encryption device for generating an electronic signature for security includes a random number generation module configured to generate at least one random number, a random number adjusting module configured to generate a one-time random number satisfying a random number condition in an elliptic curve cryptography-based digital signature algorithm (ECDSA) by adjusting the at least one random number; and an electronic signature generation module configured to generate the electronic signature using the one-time random number based on the ECDSA.

Abstract: A method and an apparatus for controlling an interleaving depth are provided. The interleaving depth controlling method includes performing a modulo operation on an interleaving depth selected to be less than or equal to a maximum interleaving depth and a total number of codewords to obtain a number of remaining codewords; and comparing the total number of the codewords to the interleaving depth, when the number of the remaining codewords excludes “0”, to control the interleaving depth.

Abstract: Techniques for wireless communication are described. A method of wireless communication at a user equipment (UE) includes receiving a synchronization signal within a synchronization signal (SS) block; receiving at least a portion of a physical broadcast channel (PBCH) of the SS block, the PBCH comprising a self-decodable portion and an outside portion; and decoding the PBCH based at least in part on receiving the self-decodable portion of the PBCH. The synchronization signal has a first bandwidth. The self-decodable portion of the PBCH has a second bandwidth substantially within the first bandwidth. The outside portion having a bandwidth that is outside of the second bandwidth and within a PBCH bandwidth, the PBCH bandwidth being greater than the first bandwidth.

Abstract: Debugging a program in an apparatus using a lockstep method are more efficiently performed and a semiconductor apparatus includes a first processor core, a second processor core, a first debug circuit, a second debug circuit, and an error control circuit capable of outputting an error signal for stopping execution of a program by the first processor core and the second processor core. The second debug circuit performs setting regarding debugging different from that of the first processor core with respect to the second processor core. Even if a first processing result of the first processor core and a second processing result of the second processor core do not coincide with each other, the error control circuit invalidates the output of the error signal when the first processor core executes the program and the second processor core stops execution of the program based on the setting regarding debugging.

Abstract: A method and an apparatus for controlling an interleaving depth are provided. The interleaving depth controlling method includes performing a modulo operation on an interleaving depth selected to be less than or equal to a maximum interleaving depth and a total number of codewords to obtain a number of remaining codewords; and comparing the total number of the codewords to the interleaving depth, when the number of the remaining codewords excludes “0”, to control the interleaving depth.

Abstract: A bit interleaving method involves applying a bit permutation process to bits of a QC-LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the codeword after the permutation process into a plurality of constellation words each including M bits, the codeword being divided into F×N?/M folding sections (N? being a subset of N selected cyclic blocks and being a multiple of M/F), each of the constellation words being associated with one of the F×N?/M folding sections, and the bit permutation process being applied such that each of the constellation words includes F bits from each of M/F different cyclic blocks in a given folding section associated with a given constellation word.

Abstract: A current frame in a sequence and one or more previous frames in the sequence may be encoded and decoded with forward error correction (FEC). The current frame is encoded at a first bitrate to generate one or more encoded source frames and the one or more previous frames are encoded at an equal or lower second bitrate to generate one or more encoded FEC frames. The encoded source frame(s) and FEC frame(s) are packetized into one or more data packets, which are stored in a memory or transmitted over a data network. The encoded source frame information and previous frame information is unpackaged from the packets and the encoded source frames are decoded. If given source frame of the sequence is missing, one or more encoded FEC frames that correspond to the given source frame are identified from among the data packets and decoded and used to reconstruct the given frame.

Abstract: The disclosure generally relates to a method and apparatus for frequency interleaving. Specifically, an embodiment of the disclosure relates to a communication system having one or more antennas, a radio, a memory circuit, and a processor circuit. The antennas can be used to communicate signals or to comply with different transmission protocols. The radio can be configured to send and receive radio signals. The memory can communicate with the processor circuit and contain instructions for the processor circuit to write data carriers along a plurality of rows and columns of a 2-D store in bit-reversed order and read the columns of 2-D store.

Abstract: A method for data storage includes receiving a plurality of data items for storage in a memory, including at least first data items that are associated with a first data source and second data items that are associated with a second data source, such that the first and second data items are interleaved with one another over time. The first data items are de-interleaved from the second data items, by identifying a respective data source with which each received data item is associated. The de-interleaved first data items and the de-interleaved second data items are stored in the memory.

Abstract: An interleaving method and apparatus for adaptively determining an interleaving depth of each of one or more interleaving blocks based on a maximum interleaving depth and a number of codewords of a packet, and interleaving the interleaving blocks based on the interleaving depth. The adaptively determining the interleaving depth includes: calculating a number of remaining codewords by performing a modulo operation on a basic interleaving depth and the number of the codewords; and determining the interleaving depth by adjusting the basic interleaving depth based on the number of the remaining codewords.

Abstract: A schedulable memory scrubbing circuit and/or a known-state memory test circuit (collectively, background memory test apparatus (“BGMTA”)) are located on-chip with an integrated computing system. The BGMTA operates in parallel with a system CPU but shares a system bus with the CPU. The BGMTA sequentially reads one word at a time from a block of memory to be tested during system bus idle cycles. The schedulable memory scrubbing circuit embodiment tests on-chip parity/ECC memory arrays using memory controller-implemented parity or ECC error detection to trigger error handling interrupts. The known-state memory test circuit embodiment performs CRC calculations on known-state memory arrays as each data word is read sequentially. A final resulting CRC calculation value is compared to a known CRC value for the block, sometimes referred to as a “golden CRC.” If the two CRC values differ, a CRC error interrupt is triggered for servicing by the CPU.

Abstract: A method and an apparatus for controlling an interleaving depth are provided. The interleaving depth controlling method includes performing a modulo operation on an interleaving depth selected to be less than or equal to a maximum interleaving depth and a total number of codewords to obtain a number of remaining codewords; and comparing the total number of the codewords to the interleaving depth, when the number of the remaining codewords excludes “0”, to control the interleaving depth.

Abstract: A method of block deinterleaving data received at a digital radio broadcast receiver is described. The method includes providing a block of memory having a n×k addresses, wherein the block comprises a single table, receiving a digital radio broadcast signal at the receiver, and demodulating the digital radio broadcast signal into a plurality of interleaved data units. For at least one series of n×k data units a pointer step size is determined, and for each data unit in the series, an address in the block is calculated based on the pointer step size, and an output data unit is read from the block at the address, such that said output data units represent block deinterleaved data units. An input data unit from the plurality of interleaved data units is then written to the block at the address. Associated systems and computer readable storage media are presented.

Abstract: Proposed is a bit-interleaver for an optical line terminal of an optical access network. The bit-interleaver contains a memory reader, that provides data streams at bit level to a space-time switch. The space-time switch reads within one input cycle up to N bit sets from the data streams. The switch switches within one writing cycle up to N bits onto up to its output ports, which provide respective output vectors. A number of N OR-function elements determine within the writing cycle respective single output bits. A number of N memory elements write within the one writing cycle a respective one of the output bits into a respective one of their bit sub-elements. A control unit that controls the reading of the data streams and also the switching of the bits by the switch. The control unit controls a choice of the writing addresses.

Abstract: A processor module includes at least one storage device, at least one central processing unit (CPU) that uses a preset interface, and a module controller to relay a connection between a common interface bus formed on the based board and an interface used by the CPU.

Abstract: A system and method for efficient data eye training reduces the time and resources spent calibrating one or more memory devices. A temporal calibration mechanism reduces the time and resources for calibration by reducing the number tests needed to sufficiently determine the boundaries of the data eye of the memory device. For one or more values of the voltage reference, the temporal calibration mechanism performs a minimal number of tests to find the edges of the data eye for the hold and setup times.

Abstract: A method and terminal are described for allocating resources for transmitting a signal in a multiple-input multiple-output (MIMO) wireless communication system. An uplink signal is transmitted using L layers at a terminal in a multiple-input multiple-output (MIMO) wireless communication system. Modulation symbols are generated by modulating output bit sequences of an interleaver matrix by a unit of log2 Q bits, where Q is a modulation order. Each of the output bit sequences has a size of L·log2 Q bits. The modulation symbols are mapped to the L layers and transmitted by using the L layers. The output bit sequences are generated by reading out entries of the interleaver matrix, column by column.

Abstract: The present invention relates to a wireless communication system. More specifically, the present invention relates to a method for transmitting control information through a PUCCH in a wireless communication system and an apparatus thereof, comprising the steps of: spreading modulation symbol sets to first slot, by using a first code; spreading modulation symbol sets to second slot, by using a second code, wherein the length of the second code is varied according to the number of SC-FDMA symbols for PUCCH transmission.

Abstract: A shiftable memory is employed in a system and a method to shift a contiguous subset of stored data within the shiftable memory. The shiftable memory includes a memory having built-in shifting capability to shift a contiguous subset of data stored by the memory from a first location to a second location within the memory. The contiguous subset has a size that is smaller than a total size of the memory. The system further includes a processor to provide an address and the length of the contiguous subset. The method includes selecting the contiguous subset of data and shifting the selected contiguous subset.

Abstract: One feature is a method of reading data from a plurality of pattern registers, generating a first output at a mapping register from the read data, generating a second output, different from the first output, at the mapping register from the read data, and generating a multi-level signal using the first and second outputs. In one embodiment, generating the first output is done by adding a first plurality of bits to a second plurality of bits, and generating the second output is done by adding the first plurality of bits to an inverse of the second plurality of bits.

Abstract: A state machine engine having a program buffer. The program buffer is configured to receive configuration data via a bus interface for configuring a state machine lattice. The state machine engine also includes a repair map buffer configured to provide repair map data to an external device via the bus interface. The state machine lattice includes multiple programmable elements. Each programmable element includes multiple memory cells configured to analyze data and to output a result of the analysis.

Abstract: A decoding method, a memory storage device and a memory controlling circuit unit are provided. The method includes: reading memory cells according to a first reading voltage to obtain first verifying bits; executing a decoding procedure including a probability decoding algorithm according to the first verifying bits to obtain first decoded bits, and determining whether a decoding is successful by using the decoded bits; if the decoding is failed, reading the memory cells according to a second reading voltage to obtain second verifying bits, and executing the decoding procedure according to the second verifying bits to obtain second decoded bits. The second reading voltage is different from the first reading voltage, and the number of the second reading voltage is equal to the number of the first reading voltage. Accordingly, the ability for correcting errors is improved.

Abstract: An exemplary method for reading data stored in a flash memory. The method comprises: controlling the flash memory to perform a first read operation upon the memory cell with a first threshold voltage to obtain a first binary digit for representing a bit of the N bits data; performing an error correction hard decode according to the first binary digit; controlling the flash memory to perform a second read operation upon the memory cell with a second threshold voltage to obtain a second binary digit for representing the bit of the N bits data, if the error correction hard decode indicates an uncorrectable result; and performing an error correction soft decode according to the first binary digit and the second binary digit.

Abstract: An apparatus and method for controlling a low-voltage memory in a mobile communication system are provided. The apparatus includes a memory for storing data including at least one error caused by a low-voltage, and an error correction unit for identifying whether the at least one error exists in the memory according to a first bit set in a local buffer of an error correction code storage, for comparing location information on the error data read from the memory and location information on error data of at least one protection set in the local buffer of the error correction code storage when it is determined that the at least one error exists in the memory, for generating an error correction code as a result of the comparison, and for correcting the error data of the memory according to the error correction code.

Abstract: A MIMO transmitter including an interleaving system for parsing encoded bits to a plurality of spatial streams and a plurality of interleavers to interleave bits for spatial streams such that at least a first spatial stream uses a first stream interleaver that interleaves with a pattern distinct from a second stream interleaver interleaving for a second spatial stream.

Abstract: A system and method for modulation diversity uses interleaving. Code bits are placed into groups and are then shuffled within each group.

Abstract: An electronic circuit includes a microcontroller processor (410), a peripheral (420) coupled with the processor, an endian circuit (470) coupled with the processor and the peripheral to selectively provide different endianess modes of operation, and a detection circuit (140) to detect a failure to select a given endianess, whereby inadvertent switch of endianess due to faults is avoided. Other circuits, devices, systems, methods of operation and processes of manufacture are also disclosed.

Abstract: A method includes a DSN access token module retrieving one or more sets of at least a threshold number of dispersed storage (DS) error coding function slices from the DSN memory via the computing device. The method continues with the computing device and/or the DSN access token module decoding the one or more sets of the at least a threshold number of DS error coding function slices using a default DS error coding function to recapture a DS error coding function. The method continues with the computing device and/or the DSN access token module generating a plurality of sets of data access requests in accordance with the DS error coding function. The method continues with the computing device sending the plurality of sets of data access requests to the DSN memory.

Abstract: A circuit having a first circuit and a memory is disclosed. The first circuit may be configured to (i) receive a control signal that identifies a current one of a plurality of wireless communication standards and a code word size and (ii) generate a plurality of tables corresponding to both the current wireless communication standard and the code word size. Each of the tables generally has a plurality of indices. Up to two of the indices may be generated by the first circuit per clock cycle. Each of the tables generally comprises a permutation table of a turbo code interleaver. The memory may be configured to store the tables.

Abstract: The present invention is related to systems and methods for harmonizing testing and using a storage media. As an example, a data system is set forth that includes: a data decoder circuit, a data processing circuit, and a write circuit. The data decoder circuit is configured to decode a test data set to yield a result. The data processing circuit is configured to encode a user data set guided by the result to yield a codeword. The write circuit is configured to store an information set corresponding to the codeword to a storage medium.

Abstract: A data storage system configured to efficiently search and update system data is disclosed. In one embodiment, the data storage system can attempt to correct errors in retrieved data configured to index system data. Metadata stored along with user data in a memory location can be configured to indicate a logical address associated in a logical-to-physical location mapping with a physical address at which user data and metadata are stored. The data storage system can generate modified versions of logical address indicated by the metadata and determine whether such modified versions match the physical address in the logical-to-physical mapping. Modified versions of the logical address can be generated by flipping one or more bits in the logical address indicated by the metadata. Efficiency can be increased and improved performance can be attained.

Abstract: A method of generating media programming includes the steps of providing by an aggregator to a client a list of feeds; receiving by the aggregator from the client a selection of one of the feeds; receiving by a publisher from the aggregator the feed selection; and providing to the client media programming based on a publisher-initiated feed responsive to the feed selection and including media elements selected and concatenated with the feed responsive to the client information.

Abstract: A configurable Turbo-LDPC decoder having A set of P>1 Soft-Input-Soft-Output decoding units (DP0-DPP-1; DPi) for iteratively decoding both Turbo- and LDPC-encoded input data, each of the decoding units having first (I1i) and second (I2i) input ports and first (O1i) and second (O2i) output ports for intermediate data; First and second memories (M1, M2) for storing the intermediate data, each of the first and second memories comprising P independently readable and writable memory blocks having respective input and output ports; and A configurable switching network (SN) for connecting the first input and output ports of the decoding units to the output and input ports of the first memory, and the second input and output ports of the decoding units to the output and input ports of the second memory.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. Such data processing includes data shuffling.

Abstract: An encoding apparatus derives a bit order based on a puncturing table that specifies different puncturing patterns for different transmission rates. The encoding apparatus then generates an error correcting code from an input information bit string and rearranges the error correcting code in the derived bit order. The error correcting code is punctured by taking a number of consecutive bits from the rearranged error correcting code. The number of bits taken varies depending on the transmission rate. The punctured error correcting code is output to a decoding apparatus, which realigns the code bits according to the transmission rate and the puncturing table, then uses the realigned error correcting code to correct errors in erroneous data. Rearrangement of the error correcting code makes the puncturing process more efficient by avoiding the need to decide whether to take or discard each bit individually.

Abstract: The present disclosure relates to a method for interleaving a stream of input data blocks, the method comprising steps of: subdividing a block into sub-blocks of fixed size in number of data rows and data columns, the sub-blocks being distributed in the block in rows of sub-blocks and in columns of sub-blocks, transferring the data contained in the block into a first memory, while respecting the order of the data in the input stream, transferring the data contained in the block by row of sub-blocks, into a second memory in which the data of each sub-block is accessible from the address of the sub-block, transferring the data of each sub-block by column of sub-blocks, from the second memory into a third memory, by putting back the data of each sub-block in data rows and columns, and transferring the data by data column from the third memory into an output stream.

Abstract: Methods and systems for storing data in a memory system with different levels of redundancy are disclosed. Methods and systems consistent with the present invention provide allow a redundancy level to be associated with received data, wherein associating the redundancy level of the data includes determining a desired level of protection for that data and determining the redundancy level based on the desired level of protection. A zone within a memory system is located that has a redundancy level that matches the redundancy level of the data, and the data is stored in the located zone with the desired redundancy level.

Abstract: A memory controller and method for managing the issuance of read and write requests to a system memory is provided. The number of outstanding read requests and write requests issued to the system memory are separately monitored and further issuance of read and write requests to the system memory is separately controlled based on the number of outstanding read and write requests, respectively. For example, the issuance of read and write requests can be managed by halting and resuming the issuance of read and write requests to the system memory to maintain the number of outstanding read requests between first and second read thresholds and to maintain the number of outstanding write requests between first and second write thresholds, respectively.

Abstract: Detecting a fault in the operation of a computer having a processor and a memory is taught. Instrumentation code is placed within an application program during compilation, and runtime library routines are modified to support detection of invalid memory accesses. Memory space is divided into application, shadow and unmapped memories. When accessing application memory at an original address, an address in shadow memory is computed by shifting the address and adding an offset. If the value stored at the shadow address indicates that the original address is invalid (e.g., not allocated or already freed), then error reporting code is executed that indicates the type of error and the location and optionally halts the computer. Invalid memory references to heap, stack and global objects in application memory can be detected.

Abstract: A storage subsystem coupled to a host computer is described. The storage subsystem includes storage devices and first and second storage apparatuses that control data transfer between the host computer and the storage devices. The first storage apparatus includes a first controller coupled to the host computer via a first host communication control unit and to the storage devices via a first storage device communication control unit. The second storage apparatus includes a second controller coupled to the host computer via a second host communication control unit and to the storage devices via a second storage device communication control unit. At least one of the controllers monitors a status of the first host communication control unit and the storage device communication control units, and, if the status of the first storage device communication unit indicates failure, switch communication paths for transferring data from the host computer to the storage devices.

Abstract: A method begins by a computing device determining that dispersed storage network (DSN) memory is to be accessed regarding data. The method continues when the computing device is paired with a DSN access token module with the DSN access token module retrieving a plurality of sets of at least a threshold number of dispersed storage (DS) error coding function slices from the DSN memory via the computing device. The method continues with at least one of the computing device and the DSN access token module decoding the plurality of sets of the at least a threshold number of DS error coding function slices using a default DS error coding function to recapture a DS error coding function and executing, by one or more of the computing device and the DSN access token module, the DS error coding function to access the DSN memory regarding the data.

Abstract: A system and method for permuting known and unknown message bits before encoding to provide a beneficial rearrangement of bits. Such a method can improve distance properties in the resulting subcode. In various embodiments, the structure of a beneficial rearrangement is dependent on the parameters of how known and unknown bits are grouped and on the specific type of code being used. Given these two parameters, the message bits can be rearranged to more efficiently leverage any apriori knowledge.