Abstract: Systems and methods for providing contextual interaction with connected devices are described. A mobile device having a display that presents a user interface enabling access to functionalities provided by connected devices. The user interface may be updated as various contextually-related data is received. For example, data representing a current position of the mobile device, such as Bluetooth low energy beacon signals, WiFi signals, and the like, may be monitored. In response to determining that the current position is within a threshold proximity of a first location, the user interface may be updated to emphasize a first location interface corresponding to the first location over interfaces corresponding to other locations.

Abstract: Technologies are provided for runtime identification of bad memory cells. An uncorrectable error can be detected in data stored in a plurality of memory cells of a memory device. Patterned data can be written to the plurality of memory cells that stored the data in which the uncorrectable error was detected. The data stored in the plurality of memory cells can be read and compared to the patterned data. One or more of the memory cells can be identified as bad memory cells based on differences between the patterned data and the data read from the plurality of memory cells. In at least some embodiments, the one or more identified bad memory cells can be omitted from subsequent data storage operations. Additionally or alternatively, the one or more identified bad memory cells can be repaired, for example, by using a post-package repair operation.

Abstract: Computing resource coverage is disclosed. In an example, a computing resource (CR) pool includes a plurality of CR types hosted on a plurality of hosts, where the plurality of CR types are routinely updated. A test repository stores a plurality of test cases (TC). A processor is configured to execute a testing service to compile, from a plurality of test daemons, a CR manifest of the CR types included in the CR pool. A TC manifest is compiled, including CR types tested by the plurality of TCs. The CR types included in the CR manifest are compared with the CR types included in the TC manifest. A test coverage report of tested and untested CR types is generated. A TC is added to the test repository based on the test coverage report.

Abstract: The disclosure describes a novel method and apparatus for improving interposers to include embedded monitoring instruments for real time monitoring digital signals, analog signals, voltage signals and temperature sensors located in the interposer. An embedded monitor trigger unit controls the starting and stopping of the real time monitoring operations. The embedded monitoring instruments are accessible via an 1149.1 TAP interface on the interposer.

Abstract: A system, may include a processor configured to receive circuit design data, identify one or more critical paths of the circuit design data, and generate one or more synthetic tunable replica circuits (STRCs) that may mimic the one or more critical paths. The processor may then compile the circuit design data and the one or more STRCs into program data. The system may also include an integrated circuit including a control circuit that may receive the program data from the processor, program a plurality of programmable logic regions of the integrated circuit to implement the circuit design data and the one or more STRCs, and adjust one or more operating parameters of at least one of the plurality of programmable logic regions based on the one or more STRCs.

Abstract: A JTAG TAP apparatus coupled between a host and an interface circuit, which is coupled between a memory and the JTAG TAP apparatus, includes first pin, second pin, first data register, and second data register. The first data register stores data shifted in by the host via the first pin, the shifted in data is stored into a specific address of the memory via the interface circuit. The second data register stores read back data from the specific address of the memory via the interface circuit and outputs the read back data to the host via the second pin to make the host compare the shifted in data with the read back data to perform comparison test.

Abstract: A method of screening weak bits in a memory array. The method includes storing a first set of data in a first memory array of the memory array, performing a first baking process on at least the first memory array or applying a first magnetic field to at least the first memory array, tracking an address of at least a first memory cell of a first set of memory cells of the first memory array, if the first memory cell of the first set of memory cells stores altered data, and at least one of replacing the first memory cell of the first set of memory cells storing the altered data with a corresponding memory cell in a second memory array of the memory array, or discarding the first memory cell of the first set of memory cells storing the altered data.

Abstract: Methods and systems for a semiconductor package with high routing density routing patch are disclosed and may include a semiconductor die bonded to a substrate and a high routing density patch bonded to the substrate and to the semiconductor die, wherein the high routing density patch comprises a denser trace line density than the substrate. The high routing density patch can be a silicon-less-integrated module (SLIM) patch, comprising a BEOL portion, and can be TSV-less. Metal contacts may be formed on a second surface of the substrate. A second semiconductor die may be bonded to the substrate and to the high routing density patch. The high routing density patch may provide electrical interconnection between the semiconductor die. The substrate may be bonded to a silicon interposer. The high routing density patch may have a thickness of 10 microns or less. The substrate may have a thickness of 10 microns or less.

Abstract: An integrated circuit may include an embedded test processor that is capable of performing in-field testing and repair of hardware-related defects without having to remove the integrated circuit from the customer's board. The test processor can be used to drive and monitor test vectors to performing defect screening on input-output circuitry, logic circuitry including lookup table (LUT) circuits and digital signal processing (DSP) circuits, transceiver circuitry, and configuration random-access memory circuitry. The test processor can generate a failure mechanism report and selectively fix repairable defects via a hardware redundancy scheme. The failure mechanism report allows the customer to identify the root cause of failure in the overall system.

Abstract: The present application discloses a computing device that can provide a low-power, highly capable computing platform for computational imaging. The computing device can include one or more processing units, for example one or more vector processors and one or more hardware accelerators, an intelligent memory fabric, a peripheral device, and a power management module. The computing device can communicate with external devices, such as one or more image sensors, an accelerometer, a gyroscope, or any other suitable sensor devices.

Abstract: The invention introduces a non-transitory computer program product for activating a flash device when executed by a processing unit of the flash device to have program code to: determine whether the flash device is physically reset when the flash device enters a test mode perform an operation of a first phase for transmitting a very first message to a card-initialization host when the flash device is physically reset; and perform an operation of a second phase for searching a flash module for information referenced by In-System Programming (ISP) code, obtaining the ISP code from a designated address, and programming the ISP code into the flash module when the flash device is not physically reset.

Abstract: A method for execution by a managing unit of a dispersed storage network (DSN) includes facilitating capture of log information from a plurality of entities of the DSN for storage in a log vault of the DSN. An error condition with regards to at least one of the plurality of entities can be detected. Error correlation information that includes an identified at least one of the plurality of entities can be generated based on the error condition and the log information. A DSN configuration change can be facilitated based on the error correlation information.

Abstract: A semiconductor chip may comprise: a processor for processing data; a shield which includes a metal line and is arranged over an upper portion of the processor; a detection unit for comparing a reference signal with an output signal, which is outputted when the reference signal passes through the shield, so as to detect whether there has been a wiring change within the shield or not; and a controller for configuring the routing topology of the metal line to be in a first state, and changing the routing topology from the first state to a second state.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for three-dimensionally stacked neural network accelerators. In one aspect, a method includes obtaining data specifying that a tile from a plurality of tiles in a three-dimensionally stacked neural network accelerator is a faulty tile. The three-dimensionally stacked neural network accelerator includes a plurality of neural network dies, each neural network die including a respective plurality of tiles, each tile has input and output connections. The three-dimensionally stacked neural network accelerator is configured to process inputs by routing the input through each of the plurality of tiles according to a dataflow configuration and modifying the dataflow configuration to route an output of a tile before the faulty tile in the dataflow configuration to an input connection of a tile that is positioned above or below the faulty tile on a different neural network die than the faulty tile.

Abstract: A design assistance method executed by a design assistance device for a computer system including a CPU and an accelerator, the design assistance method includes: extracting, from an input program described in a high-level language, a process including a function and data including a variable, and analyzing a relationship between a process and data, the relationship including an amount of access from the process to the data, based on a number of times of execution of the function or a loop; evaluating, for the acquired process, a used amount of resource, a delay, and a communication band of the accelerator, based on a hardware specification; and generating, for the acquired process and data, candidates represented by a combination of allocations to the CPU and the accelerator, and acquiring and presenting, for each of the candidates, a used amount of resource, a communication band, and performance of the input program.

Abstract: Disclosed are techniques regarding aspects of implementing client configurable logic within a computer system. The computer system can be a cloud infrastructure. The techniques can include determining that the client configurable logic has performed an errant action.

Abstract: A method for programmable logic controller (PLC) program randomization, the method comprising an engineering system computer receiving source code corresponding to a PLC program and compiling the source code into a plurality of functionally equivalent intermediate representations of the PLC program. Program structure of the PLC program is randomized during compilation such that each intermediate representation is unique among the plurality of intermediate representations. The engineering system computer transmits the plurality of intermediate representations to one or more PLCs.

Abstract: A constraint solver utilizes a modified relaxation process to generate multiple different stimulus stream arrays that comply with multi-dimensional (e.g., 2D or 3D) constraints. First, an array is generated including rows and columns of randomly generated test vector values. During a first revision phase, the array is modified to comply with first-dimension constraints (e.g., selected test vector values are changed in non-compliant rows until every row complies with all row constraints). A second revision phase is then performed in multiple cycles, where each cycle includes identifying a current element having a greatest impact on non-compliance of the array on second-dimension (e.g., column and/or diagonal) constraints, and revising the current element's test vector value in a way that both minimizes the non-compliance, and also maintains compliance of the array with the first-dimension constraints.

Abstract: In some examples, a programmable device may load configuration data into a configuration storage to configure programmable logic of the programmable device. The programmable device may include a key generation logic that may read at least a portion of the configuration data from the configuration storage. The key generation logic may generate a cryptographic key based at least in part on the at least a portion of the configuration data read from the configuration storage.

Abstract: Systems and techniques for memory event mitigation in redundant software installations are presented. A system can initiate an event executed by a first software application and a second software application that corresponds to the first software application. First data associated with the first software application can be stored in a first data store and second data associated with the second software application can be stored in a second data store. The system can also compare a first check value for the first data associated with the event and a second check value for the second data associated with the event. Furthermore, the system can re-initiate the event executed by the first software application and the second software application in response to a determination that the first check value does not correspond to the second check value.

Abstract: A built-in self-test (BIST) parallel memory test architecture for an integrated circuit, such as a system-on-a-chip (SoC), is disclosed. A BIST controller generates a test data pattern for memories of a common memory type, with this test data pattern forwarded to the memories, with pipeline delay stages inserted in the data path according to the operational speed of the memory in its normal operation. The expected data response of these memories, when read, and corresponding to this test data pattern is delayed for a group of memories by a local delay response generator shared by those memories. For example, the memories in the group of memories may be physically near one another. The local delay response generator delays the expected data response by a delay corresponding to the memory latency of those memories in the group, before applying the expected data response to local comparators associated with the memories in the group.

Abstract: An integrated circuit device includes a first partition and a second partition. The integrated circuit device also includes a Joint Test Action Group (JTAG) system that controls at least a portion of the integrated circuit device via logic signals. The JTAG system includes a JTAG interface that receives logic signals and a first JTAG hub instantiated in the first partition communicatively coupled to the JTAG interface. The integrated circuit device further includes a second JTAG hub instantiated in the second partition communicatively coupled to the first JTAG hub via a bridge.

Abstract: The present invention provides a semiconductor device and a failure detection method capable of detecting an excessive variation among elements that constitute an analog circuit as a failure. According to an embodiment, a semiconductor device 1 includes: an AD converter 11; a digital assist circuit 12 that corrects an error of a digital signal Do corresponding to an analog signal Ain processed by the AD converter 11; and a failure detection circuit 13 that detects whether the AD converter 11 has a failure based on a correction amount by the digital assist circuit. The semiconductor device 1 is therefore able to detect the excessive variation among the elements that constitute the AD converter 11 as a failure.

Abstract: Embodiments include methods, computer systems and computer program products for generating functional test patterns for diagnostics, characterization and manufacture test.

Abstract: The embodiments described herein may improve utilization of an emulator system's resources, and may improve efficiency and effectiveness in bug-identification and/or target-debugging; the components described herein may improve utilization of the emulator's resources, reduce wait time to execute emulation routines, and may limit or eliminate the need to stop or kill emulations in process. The various embodiments described herein allow for dynamically associating domains and targets by dynamically allocating and assigning domains with particular target connections, which are pins and/or wires that connect target pods to the emulation system. An emulation system may comprise one or more target MUXs that are situated between the target connections and the domains, to allow the relationships between target pods and domains to be identified and switched dynamically.

Abstract: The system includes an integrated sequenced arrangement of parametric type instruments, automated guided prober test instruments, and a test instrument system using analog signature analysis for identifying faults in circuit card assemblies, under control of a software system with a mass interconnect system.

Abstract: An integrated circuit device includes a first partition and a second partition. The integrated circuit device also includes a Joint Test Action Group (JTAG) system that controls at least a portion of the integrated circuit device via multiple logic signals. The JTAG system includes a JTAG interface receives the multiple logic signals. The JTAG system also includes a JTAG hub instantiated in the first partition and being communicatively coupled to the JTAG interface. The JTAG system further includes JTAG-based logic instantiated in the second partition. The integrated circuit device further includes an interface instantiated in the first partition configured to communicatively couple the JTAG hub to the JTAG-based logic.

Abstract: A programming system for device control is disclosed. The system includes a development board scanning module, a web server, and a working host. An application programming interface packaging module in the working host is a key part to translate high-level programming language codes into low-level programming language codes. Thus, using high-level programming language or interface to implement equipment control or development work becomes feasible.

Abstract: Aspects include a system having logic built-in self-test (LBIST) circuitry for use in an integrated circuit with scan chains. The system includes a pattern generator configured for generating scan-in test values for said scan chains; a signature register configured for collecting scan-out responses from said scan chains after a clock sequence; an on-product control generator configured for controlling at least one test parameter; one or more microcode array or memory elements configured to receive inputs to initialize fields in the microcode array or memory elements; and a test controller. The test controller includes a reader component configured for reading test parameters from a field of the microcode array or the memory elements; and a programming component configured for configuring the on-product control generator and the pattern generator with a LBIST pattern according to the read test parameters.

Abstract: A video encoding/decoding system includes a video encoding device and a video decoding device. The video encoding device includes an encoding part for encoding a diagnostic image or normal image. The video decoding device includes a decoding part for decoding the image encoded by the encoding part, a check signal generation part for generating a check signal of the decoded image, a storage part for storing the expected value of the check signal of the diagnostic image or the check signal generated by the check signal generation part, and a comparison part for comparing the check signal stored in the storage part with the check signal generated by the check signal generation part, in order to detect failure in all the paths from the image input part of the video encoding device to the image output part of the video decoding device.

Abstract: The provided scalable, radiation tolerant, high-integrity, space-rated Graphical Processing Unit (GPU) supports open interfaces and provides sufficient graphics performance for known display formats as well as as-yet-undefined, futuristic, display formats that may be updated on-mission without needing, for example, a host space vehicle to return to earth or a lunar site. The provided GPU further provides flexibility and dynamic scalability.

Abstract: Systems and methods are provided for determining a clock time associated with an event at a higher precision than is attainable by a main clock signal. A system includes a plurality of processing modules distributed across an integrated circuit, a main clock signal being transmitted to ones of the plurality of processing modules at a main clock frequency. A plurality of sub-cycle frequency resolution modules are disposed in corresponding ones of the processing modules, the sub-cycle frequency modules generating sub-cycle phase indicators at a frequency that is greater than the main clock frequency, the sub-cycle frequency resolution modules being configured to receive the main clock signal and to determine a clock time of an event based on a combination of the main clock and the sub-cycle phase indicators.

Abstract: A method, computer program product, and system performing a method that includes a processor compiling a description including information to be utilized by programmable logic to recognize a code fingerprint in a program executing in the runtime environment. The method also includes the processor configuring the programmable logic, by loading the description into the programmable logic at a predefined time and obtaining, during runtime of the program, an alert that the programmable logic recognized the code fingerprint in the program.

Abstract: Embodiments include methods, computer systems and computer program products for generating functional test patterns for diagnostics, characterization and manufacture test.

Abstract: Exemplary embodiments provide for a method, a system, and a computer readable medium for providing automation and control of equipment and facility resources via a mobile device of a user. Location information of a user in or near a facility is detected using a position sensor. The location information is communicated wirelessly from a mobile device of the user to a server. One or more actions are determined as being available to the user based on the location information and user role, where the actions are representative of the actions available in an ICS application. Instructions are communicated to cause the mobile device to display the determined actions in a user interface, enabling the user to receive messages and interact with equipment or facility resources located in proximity of the user by interacting with the one or more actions displayed in the user interface.

Abstract: One feature pertains to generating a unique identifier for an electronic device by combining static random access memory (SRAM) PUFs and circuit delay based PUFs (e.g., ring oscillator (RO) PUFs, arbiter PUFs, etc.). The circuit delay based PUFs may be used to conceal either a challenge to, and/or response from, the SRAM PUFs, thereby inhibiting an attacker from being able to clone a memory device's response.

Abstract: An integrated circuit chip with a built-in self-test (BIST) circuit having a BIST engine, which is electrically connected to multiple memories, which tests those multiple memories in parallel, and which incorporates an address generator. Prior to testing, the address generator generates a pair of tables. The tables include a first table, which indicates the highest decode numbers per specific bank numbers in all of the multiple memories, and a second table, which indicates the highest bank numbers per specific decode numbers in all of the multiple memories. During testing, the address generator sequentially and dynamically generates the specific test addresses to be swept and does so such that all of the specific test addresses are within a composite address space that is defined by one of the tables and by the highest maximum word line number in any of the memories. Also disclosed is an associated BIST method.

Abstract: A system for concurrent target diagnostics is disclosed. The system comprises dedicated FPGA for generating test data to test target connections between an emulator and a target system. In this way, domains of the emulator may continue to emulate at least a portion of a hardware design during the testing of the target connections. Further, a multiplexer operable to select target connections for testing eliminates errors resulting from manual swapping of target connections during the testing process. The system further comprises multiple paths to a target pod. The paths enable monitoring and reporting on the status of target connections between an emulator and a target system.

Abstract: A method for simulating a circuit includes running a first prototype of the circuit a predetermined number of cycles behind a second prototype of the circuit, and running a hardware emulator of the circuit in accordance with an input trace received by the first prototype and the second prototype.

Abstract: Determining a circuit design-specific, failures in time rate for single event upsets for an integrated circuit (IC) includes determining, using a processor, a number of critical interconnect multiplexer bits for a circuit design for a target IC and determining a number of critical look-up table bits for the circuit design. Using the processor, a device vulnerability factor is estimated for the circuit design for the target IC using the number of critical interconnect multiplexer bits and the number of critical look-up table bits. The estimated device vulnerability factor can be stored, e.g., for subsequent comparison with other circuit designs.

Abstract: A method in a memory device that operates in a testing mode, includes receiving a vector to be written to the memory device. The vector is written to the memory device only if the vector belongs to a predefined set of test vectors. If the vector does not belong to the set of test vectors, the vector is converted to one of the test vectors, and the converted vector is written to the memory device.

Abstract: A method of determining a fingerprint identification of a cryptographic implementation in a cryptographic system, including: receiving, by the cryptographic system, an input message that is a fingerprint identification message; performing, by the cryptographic system, a keyed cryptographic operation mapping the fingerprint identification message into an output message that includes a fingerprint identification; and outputting the output message.

Abstract: One or more specialized field programmable modules (e.g. CPLD and FPGA blocks) and their programming interface are embedded into a processing system (e.g. a CPU, GPU, APU and/or chipset). The field programmable modules are in-system programmable, in contrast to the application specific integrated circuit (ASIC) modules that perform the core functions of the processing system. The programmable flexibility of the field programmable modules can have various benefits during different stages of the integrated circuit life cycle for the processing system, such as reconfigurable interface bridging and two-way I/O expansion.

Abstract: Clock distribution schemes in emulation systems are typically complex and use significant resources. The present disclosure is generally directed to clock distribution to emulation chips using a serial interconnect mesh. A clock distribution tree is overlayed on the emulation chips allocated to a user's circuit design, the tree branching from a root emulation chip using selected serial interconnections and covering each allocated emulation chip. The emulation chips can recover a clock from received serial signals. The delay associated with each interconnection is determined and used by configuration software when creating the distribution tree. To start emulation stepping synchronously, each emulation chip is configured to know its delay from the root emulation chip. A message is sent from the root emulation chip to each branch emulation chip triggering a timer to countdown a time until emulation is to begin, allowing the emulation chips to start stepping in lockstep.

Abstract: A battery management and protection system includes a string of battery management and protection integrated circuit devices that may be connected to one another in a daisy chain configuration. Some of the devices can be electrically connected to one or more battery cells. Each device includes an inter-device communication interface comprising a daisy chain line driver. The system includes a controller external to the string of devices and a bi-directional connection lines connecting each device in the string to an upstream and/or downstream device in the string. The system can allow the external controller to access any single one of the devices in the daisy chain, any subset of the devices in the daisy chain, or all the devices in the daisy chain using a single command that is transmitted from one device to the next over a bi-directional connection line.

Abstract: In an example, a method of implementing a circuit design for a programmable integrated circuit (IC) begins by identifying combinatorial logic functions of the circuit design. The method maps, according to a first constraint, a first threshold percentage of the combinatorial logic functions onto a first type of lookup tables (LUTs) of the programmable IC in favor of second type of LUTs of the programmable IC, the second type of LUTs being more susceptible to single event upsets than the first type of LUTs. The method generates a first physical implementation of the circuit design for the programmable IC based on the mapping.

Abstract: A method for testing a set of circuitry in an integrated circuit (IC) is described. The IC includes multiple configurable circuits for configurably performing multiple operations. The method configures the IC to operate in a user mode with a set of test paths that satisfies a set of evaluation criteria. Each test path includes a controllable storage element for controllably storing a signal that the storage element receives. The method operates the IC in user mode. The method reads the values stored in the storage elements to determine whether the set of circuitry is operating within specified performance limits.

Abstract: A computation unit locates data of a first component in a first circuit, as well as data of a second component in the second circuit. The computation unit then obtains data of a first portion of the first circuit by tracing wiring lines from component to component in the first circuit, with the first component as the start point. Similarly the computation unit obtains data of a second portion of the second circuit by tracing wiring lines from component to component in the second circuit, with the second component as the start point. The computation unit outputs data indicating differences between the first portion and second portion, based on the obtained data of the first portion and the obtained data of the second portion.

Abstract: An integrated circuit (IC) structure can include a first die and a second die. The second die can include a first base unit and a second base unit. Each of the first base unit and the second base unit is self-contained and no signals pass between the first base unit and the second base unit within the second die. The IC structure can include an interposer. The interposer includes a first plurality of inter-die wires coupling the first die to the first base unit, a second plurality of inter-die wires coupling the first die to the second base unit, and a third plurality of inter-die wires coupling the first base unit to the second base unit.

Abstract: A device for performing timing analysis used in a programmable logic array system is provided. The device comprises first and second basic I/O terminals, a channel multiplexer, high-speed I/O terminals, a sampling module and a timing analysis module. The first basic I/O terminals receive under-test signals from an under-test unit. The channel multiplexer receives the under-test signals from the first basic I/O terminals to select at least a group of the under-test signals to be outputted to the second basic I/O terminals. The high-speed I/O terminals has a logic level analyzing speed higher than that of the first and second basic I/O terminals. The sampling module receives the group of under-test signals from the high-speed I/O terminals and samples the group of under-test signals to generate a sample result. The timing analysis module performs timing analysis and measurement according to the sample result.