Abstract: A configurable integrated circuit (IC) performs error detection and correction on configuration data. The IC includes a configuration memory for storing configuration data, an error detection circuitry for detecting an error and a circuit that outputs from the IC an uncorrectable error signal indicating the detection of an error. The configurable IC has a circuit inside of the IC that causes the IC to reset when the error circuitry detects an uncorrectable error. In another embodiment, the circuit that causes the IC to reset is located outside of the IC.

Abstract: A memory coupled to a programmable logic device (PLD) is configured through the PLD's JTAG port. A soft core loaded into the PLD connects to the JTAG port and memory. An external programming host device connects to the JTAG port, sends instructions and data to and receives data from the memory via the JTAG port and soft core. A synchronization JTAG instruction is loaded, and a Shift Data state of the JTAG port state machine is used. The programming host device and soft core are synchronized, and a memory chip select is asserted. A memory instruction, such as READ, WRITE or ERASE is loaded into the memory. An RTI state of the state machine is used to wait for instruction completion and the chip select is deasserted. Another instruction is processed starting with using the Shift Data state. Alternatively, a PLD Shift Data Register is used in conjunction with the soft core.

Abstract: According to some embodiments, characterization data can be loaded onto a programmable device. The characterization data can be configured to cause the programmable device to perform one or more functions if executed on the programmable device. It can then be determined whether or not loading the characterization data onto the programmable device caused the programmable device to be successfully programmed. An indication can be transmitted for receipt by an external device, the indication indicating whether or not the programmable device was successfully programmed.

Abstract: A circuit arrangement includes a programmable logic device. The programmable logic device includes configuration logic circuitry. The programmable logic device also includes configurable interconnects. The circuit arrangement further includes a storage device configured to provide data to the programmable logic device. The storage device communicates with the programmable logic device via a bi-directional interface.

Abstract: The present invention provides a programmable logic device including a main circuit unit capable of variably building desired user logic, based on configuration data inputted from a storage device, and a configuration data monitor unit for monitoring configuration data stored in the storage device.

Abstract: A system and method of providing error detection and correction capability in an IC using redundant logic cells and an embedded field programmable gate array (FPGA). The system and method provide error correction (EC) to enable a defective logic function implemented within an IC chip design to be replaced, wherein at least one embedded FPGA is provided in the IC chip to perform a logic function. If a defective logic function is identified in the IC design, the embedded FPGA is programmed to correctly perform the defective logic function. All inputs in an input cone of logic of the defective logic function are identified and are directed into the embedded FPGA, such that the embedded FPGA performs the logic function of the defective logic function.

Abstract: The methods and circuits of the present invention relate to testing integrated circuits. According to one aspect of the invention, a method of testing an integrated circuit is disclosed. The method comprises the steps of coupling test equipment to the integrated circuit; coupling a test equipment clock signal from the test equipment to the integrated circuit, wherein the test equipment clock signal has a first frequency; generating an internal burst clock signal within the integrated circuit based upon the test equipment clock signal, wherein the internal test clock signal has a burst frequency; and testing the integrated circuit using the internal burst clock signal. Other methods and circuits for testing programmable logic devices are also described.

Abstract: A device reduces false positive memory error detections by using a masking unit and sensitivity mask data to exclude unused portions of the memory from the error detection computations. A device includes an error detection unit to read data from the memory and verify data integrity. The sensitivity mask data indicates unused portions of the memory. Unused portions of the memory may correspond with configuration data for unused portions of a programmable device. Each bit of the sensitivity mask data may indicate the usage of one or more bits of the data from the memory. In response to the mask data, the masking unit sets data from the unused portions of the memory to values that do not change the result of the error detection computations. This prevents any errors in data from the unused portions of the memory from raising an error signal.

Abstract: Methods and structures utilizing multiple configuration bitstreams to program integrated circuits (ICs) such as programmable logic devices, thereby enabling the utilization of partially defective ICs. A user design is implemented two or more times, preferably utilizing different programmable resources as much as possible in each configuration bitstream. The resulting user configuration bitstreams are stored along with associated test bitstreams in a memory device, e.g., a programmable read-only memory (PROM). Under the control of a configuration control circuit or device, the test bitstreams are loaded into a partially defective IC and tested using an automated testing procedure. When a test bitstream is found that enables the associated user design to function correctly in the programmed IC, i.e.

Abstract: SEU mitigation, detection, and correction techniques are disclosed. Mitigation techniques include: triple redundancy of a logic path extended the length of the FPGA; triple logic module and feedback redundancy provides redundant voter circuits at redundant logic outputs and voter circuits in feedback loops; enhanced triple device redundancy using three FPGAs is introduced to provide nine instances of the user's logic; critical redundant outputs are wire-ANDed together; redundant dual port RAMs, with one port dedicated to refreshing data; and redundant clock delay locked loops (DLL) are monitored and reset if each DLL does not remain in phase with the majority of the DLLs. Detection techniques include: configuration memory readback wherein a checksum is verified; separate FPGAs perform readbacks of configuration memory of a neighbor FPGA; and an FPGA performs a self-readback of its configuration memory array.

Abstract: Integrated circuits such as programmable logic device integrated circuits have configuration random-access memory elements. The configuration random-access memory elements are tested to determine whether any of the elements have resistive bridging faults at their outputs. During testing, a pattern of test configuration data is loaded into the configuration random-access memory elements. The programmable logic device is placed in user mode to clear programmable logic registers on the device. The configuration random-access memory elements are sensitized to the presence of resistive bridging faults by performing read operations. After sensitizing the configuration random-access memory elements, a tester applies test vectors to the programmable logic of the programmable logic device. As the test vectors are applied, the tester observes whether the programmable logic of the device is performing properly or has been affected by the presence of a resistive bridging fault.

Abstract: A separate program power input is provided to a programmable logic array's memory to permit it to be programmed independently of printed circuit board power. Means are provided to isolate the program power input from the array's programmable logic circuit. Means are further provided to isolate the memory from the programmable logic circuit. The program power is not connected directly or indirectly to the programmable logic circuit thereby permitting the use of low-power devices to program the memory without connecting the printed circuit board to a power supply.

Abstract: Testing of routing resources in a path between network nodes is provided using simpler nodes to replace more complex IP modules which could be programmed into an FPGA after the routing resources are tested. Further, when it is impractical to generate a pattern from a source node S for testing a network path N to a load, subnetworks are created to perform testing. To provide the subnetworks, a source S? is first provided close to node S that generates signal patterns to route through a path N? to load L. When it is impractical to test a network path N from source to load L, a load L? is further provided close to load L that receives the signal patterns from a routing path N? provided from source S. The paths N? and N? overlap to cover all the routing resources of the path N.

Abstract: An adaptive test system includes one or more reconfigurable test boards, with each test board including at least one re-configurable test processor. The re-configurable test processors can transmit communicate with one another using an inter-processor communications controller associated with each re-configurable test processor. The communications include configuration information, control information, communication protocols, stimulus data, and responses. Configuration information and stimulus data can also be read from a memory. Configuration information is used to configure one or more re-configurable test processors. Once configured, the re-configurable test processor or processors process the data in order to generate one or more test signals. The one or more test signals are then used to test a DUT.

Abstract: An embodiment generally relates to a method of self-detecting an error in a field programmable gate array (FPGA). The method includes writing a signature value into a signature memory in the FPGA and determining a conclusion of a configuration refresh operation in the FPGA. The method also includes reading an outcome value from the signature memory.

Abstract: Techniques for organizing and displaying timing data derived from an EDA tool are provided that allows users to easily extract, analyze, and manipulate portions of the timing data relevant to particular user requirements. Relevant portions of signal waveforms are displayed on an interactive graphical user interface (GUI). Time points on the waveforms are marked with pointers so that users can easily visualize the relationships between different signals. A user can also extract relevant timing data from the EDA tool by manipulating the GUI. Manipulating and understanding circuit design requirements affects all of the design cycle and the quality of the final result from an EDA tool. A user can visualize all aspects of timing analysis on the GUI, such as clock skew, and the setup/hold relationship. A data entry approach is provided that can be used for natural and intuitive manipulation of various timing relationships.

Abstract: Error detection circuitry is provided on a programmable logic resource. Programmable logic resource configuration data is loaded into a cyclic redundancy check (CRC) module where a checksum calculation may be performed. In one embodiment, the checksum may be compared to an expected value, which is a precomputed checksum on data prior to being programmed into or while data is being programmed into a programmable logic resource. In another embodiment, the expected value may be included in the checksum calculation. An output indicating whether an error is detected may be generated depending on the relationship between the checksum and the expected value, or on the value of the checksum. This output may be sent to an output pin that is accessible by user logic.

Abstract: A circuit arrangement includes a programmable logic device. The programmable logic device includes configuration logic circuitry. The programmable logic device also includes configurable interconnects. The circuit arrangement further includes a storage device configured to provide data to the programmable logic device. The storage device communicates with the programmable logic device via a bi-directional interface.

Abstract: A method for generating automatic design characterization patterns for integrated circuits (IC) is provided. The method includes selecting a routing scheme from a file containing the device description of the routings of the IC. The routing scheme may be of a phase locked loop, clock tree, delay element, or input output block in one embodiment. Resource types for the routing scheme are identified and a path is defined, within constraints, between the resources. Once a path is defined, alternate paths are defined by retracing the path within constraints from an end of the path to the beginning of the path. An alternative path is then built and the alternative path shares a portion of the path previously defined. A computing system providing the functionality of the method is also provided.

Abstract: A diagnostic tool for simultaneously communicating with a plurality of motor vehicle control units and implements at least two different communication protocols within a single motor vehicle. The diagnostic tool includes a processor and a field programmable gate array. The processor simultaneously executes a plurality of diagnostic routines and thereby provides messages to at least two of the plurality of motor vehicle control units. The field programmable gate array provides a selectable multiple protocol interface to simultaneously accommodating the at least two different communication protocols. The field programmable gate array is coupled between the plurality of motor vehicle control units and the processor. The selectable multiple protocol interface simultaneously converts the messages from the processor into a format readable by the selected motor vehicle control units and simultaneously converting received control unit information into a format readable by the processor.

Abstract: A method and apparatus for a clock and data recovery circuit that includes a set of serializer/deserializer (SERDES) circuits that are adapted to sample progressively delayed versions of an input data stream. The sampling rate is slightly higher than the data rate of the input data stream, which produces duplicate bits in the detected data stream. Error and offset matrices are used to generate an index pointer into a detected data matrix to extract the correct data bits from the duplicate bits of the detected data matrix. Down-sampling of the corrected data is performed to populate a ring buffer. Data is then extracted from the ring buffer using a clock signal whose frequency is adapted from the sampling clock signal used by the SERDES to prevent underflow/overflow of the ring buffer.

Abstract: Reconfigurable circuits and systems having a recovery module coupled to the reconfigurable circuit and configured to access the configuration memory to retrieve configuration data stored in the configuration memory. The recovery module analyzes the retrieved configuration data to determine whether the configuration data has been corrupted and, if so, restores the configuration data to their uncorrupted state. Methods of operating such reconfigurable circuits and systems are also described.

Abstract: An Application Specific Distributed Test Engine (ASDTE) that provides an optimized set of test resources for a given application. The test engine resources, configuration, functionality, and even the number of test engines can be changed as different devices are tested, or as different test methodologies are used with the system. This can be done by including the test engine configuration as a part of the application files that are loaded during the system set-up. This approach differs from conventional testing systems which limit testing to a fixed, limited, or standard stimulus/response engine configuration intended to test a variety of devices.

Abstract: Method and apparatus for configuring a programmable logic device to perform testing on a signal channel is described. Configurable logic of the programmable logic device is configured for a test mode. Configurable interconnects are configured for communication from or to the configurable logic to or from transceivers coupled to the configurable input/output interconnect to communicate test signals.

Abstract: A reconfigurable device test scheme is provided for making a test of a reconfigurable device with configuration data which is loaded a smaller number of times. A reconfigurable device used herein holds a plurality of configuration data and is capable of instantaneously switching which configuration is implemented thereby. Specifically, one transfer configuration data and one or more test configuration data are previously loaded in a configuration memory of the reconfigurable device, and a test is made while sequentially switching the transfer configuration data and the test configuration data. In this way, the same configuration data need not be reloaded over and over, so that the test can be made with a smaller number of times of loading as compared with before.

Abstract: Circuit and method for testing digital logic circuit modules of an integrated circuit chip. The circuit includes a storage device, a first multiplexing module and a selection device. The storage device stores first, second, third and fourth N-bit groups of a test pattern separately according to a loading signal and an address selection signal. The first multiplexing module is coupled to the storage device and a first digital logic circuit module, for parallel transmitting the first, second, third and fourth N-bit groups which will be received and executed by the first digital logic circuit module to parallel generate first, second and third M-bit groups. The selection device is coupled to the first digital logic circuit module for sequentially selecting one of the first, second and third M-bit groups to output a first test result according to the address selection signal.

Abstract: Configuration memory cells in an integrated circuit (IC) may be corrupted by cosmic radiation and other sources, causing improper operation of the IC. Reliability of an IC is improved by refreshing subsets, such as frames, of the configuration data according to a schedule that has one subset being refreshed more frequently than another subset. For each subset of the configuration data, a respective indicator is determined that indicates whether a subset of configuration memory of the IC requires refreshing with the subset of configuration data. The indicator may be a probability that corruption of the subset of configuration memory results in improper operation. A schedule for refreshing the subsets of configuration memory is generated from the indicators. The subsets of configuration memory are refreshed according to the schedule, with one subset being refreshed more frequently than another subset.

Abstract: A programmable logic device includes, in accordance with one embodiment, a plurality of logic blocks; an interconnect structure adapted to route signals among the logic blocks; and a memory for storing data within the programmable logic device. A first set of the logic blocks are configured as logic analyzer trigger units adapted to each receive one or more input signals from within the programmable logic device and provide a corresponding trigger unit output signal. A portion of the memory stores a logic analyzer trigger expression, with the trigger unit output signals provided to the memory as address signals for the trigger expression.

Abstract: Methods of compensating for process variations and/or mask revisions in a programmable integrated circuit (IC). A non-volatile memory in the IC stores a value representing a process corner and/or mask revision for the IC. A configuration control circuit monitors a configuration bitstream provided to the programmable IC. When no code key is received, configuration data is applied to a first (e.g., digital) circuit. When a code key is identified, the code key is compared to the stored value. If there is a match, the subsequent configuration data is applied to a second (e.g., analog) circuit. If there is no match, the subsequent configuration data is ignored until an “unlock” command is detected in the bitstream. Thus, the configuration data for the digital circuit need be included only once in the bitstream, while the configuration data for the analog circuit is supplied once for each supported process corner or mask revision.

Abstract: A digital system and a method for operating the same. The digital system includes (a) a first and a second pins, (b) first and second logic domains, and (c) first and second test pulse generator circuits. The first test pulse generator circuit is electrically coupled to the first pin and the first logic domain. The second test pulse generator circuit is electrically coupled to the second pin and the second logic domain. When a first test signal and K (positive integer) common test enable signals being asserted, the first test pulse generator circuit generates two first test pulses resulting in the first logic domain being tested. When a second test signal and the K common test enable signals being asserted, the second test pulse generator circuit generates two second test pulses resulting in the second logic domain being tested. The first and second pins are connected to a tester.

Abstract: An integrated circuit (IC) performs error detection and correction on configuration data. The IC includes a configuration memory for storing configuration data and error correction data, and error correction circuitry for receiving the configuration data, correcting a particular error in the received configuration data when the particular error exists in the configuration data, and outputting the configuration data without the particular error. The IC further includes a configurable circuit (e.g., a configurable logic circuit or a configurable interconnect circuit) that receives the error-corrected configuration data from the error correction circuitry, and circuitry to write the corrected configuration data and error data back into the configuration memory.

Abstract: A test circuit in an integrated circuit and method of testing therewith are described. A test pattern generator provides a test pattern. A reference circuit includes a first sequential circuit coupled in series with a second sequential circuit. A circuit under test is coupled between a source sequential circuit and a destination sequential circuit to form a series. The source sequential circuit and the first sequential circuit are coupled to the test pattern generator to receive the test pattern. A comparison circuit is coupled to receive a first output from the destination sequential circuit and a second output from the second sequential circuit. The comparison circuit is configured to compare the first output with the second output to provide a signature output.

Abstract: A hardware and software co-test method for FPGA comprises the following steps of: setting up a HW/SW co-test system comprising a PC, a software part, HW/SW communication modules, a hardware accelerator for testing a DUT FPGA which is mapped with a configuration file of DUT; predefining a table of test vectors for FPGA by software part in PC; generating configuration files based on the tables of test vector for I/O module, CLB and routing matrix, and then sending the configuration file into DUT FPGA to configure the FPGA; testing DUT FPGA in terms of the tables of test vector for lo I/O module, CLB and routing matrix, and returning results to the software part; and comparing the test results with expected data in the software part, generating a test report, and during the above steps, the error cells in the FPGA are capable of being automatically positioned.

Abstract: Provided are systems for repairing an integrated circuit device. The systems include detection logic configured to locate a defective portion of an integrated circuit device, a supplemental integrated circuit component configured to functionally replace the defective portion, and logic configured to identify an interface location. Also provided are methods for repairing an integrated circuit device. The methods include the steps of: identifying a defective portion of an integrated circuit device; disconnecting existing circuit components; and incorporating a supplemental integrated circuit component with the integrated circuit device.

Abstract: Some embodiments provide a configurable integrated circuit (IC) that has several configurable circuits and several user design state (UDS) circuits. The UDS circuits store user-design state values. The configurable IC also includes a debug network communicatively coupled to the UDS circuits. The debug network is for retrieving the user-design state values of several UDS circuits at various stoppages of the operation of the IC without retrieving configuration data that is used to configure the configurable circuits of the IC. The retrieved user-design state values at each stoppage are used as the checkpointed state of the IC while debugging the IC. In some embodiments, the debug network allows the checkpointing of only certain portions of the configurable IC.

Abstract: A clock and data recovery circuit includes even and odd latches, a detection module, a clock recovery module, a compensating module, and a data recovery module. The even and odd latches are operably coupled to latch even and odd bits of a digital stream of data based on a recovered clock to produce even and odd latched bits. The detection module is operably coupled to produce a phase representative pulse stream based on the even and odd latched bits. The clock recovery module is operably coupled to produce the recovered clock based on the phase representative pulse stream. The compensating module is operably coupled to adjust biasing of the even and odd latches based on operating parameter changes of the clock and data recovery circuit. The data recovery module is operably coupled to produce recovered data from the even and odd latched bits based on the recovered clock.

Abstract: SEU mitigation, detection, and correction techniques are disclosed. Mitigation techniques include: triple redundancy of a logic path extended the length of the FPGA; triple logic module and feedback redundancy provides redundant voter circuits at redundant logic outputs and voter circuits in feedback loops; enhanced triple device redundancy using three FPGAs is introduced to provide nine instances of the user's logic; critical redundant outputs are wire-ANDed together; redundant dual port RAMs, with one port dedicated to refreshing data; and redundant clock delay locked loops (DLL) are monitored and reset if each DLL does not remain in phase with the majority of the DLLs. Detection techniques include: configuration memory readback wherein a checksum is verified; separate FPGAs perform readbacks of configuration memory of a neighbor FPGA; and an FPGA performs a self-readback of its configuration memory array.

Abstract: A programmable logic system includes a reconfigurable programmable logic device and configuration storage that stores at least two configurations. A default configuration loads first and then loads the desired user application configuration. If the user application configuration fails, the system saves data regarding the failure and then returns to the default configuration for recovery. The default configuration, after reading the failure data, causes an operator to be called to intervene, or loads a different (e.g., previous) configuration if one is available in configuration storage. The system is particularly useful where the user can update configurations remotely. In an alternative mode, the system stores only the user configuration (which is loaded first) and the default configuration. If a newly-loaded configuration fails, the default configuration is loaded and signals the operator or takes other action short of loading a different configuration.

Abstract: Methods and systems provide for early and simplified testing for defects in the interconnects of a programmable logic device (PLD) and in associated software tools. Data that describes the interconnects are read from a database for the PLD. For each interconnect, a respective test design is automatically generated with the test design replacing a portion of a coupling between an input pad and an output pad in an archetypal test design with a coupling that includes the interconnect. A respective configuration is automatically generated for the PLD from each test design. A respective operation of the PLD programmed with each configuration is simulated, and each operation of the PLD for is checked inconsistency with an expected result. In response to any inconsistency, an indication of the inconsistency is displayed to a user.

Abstract: An integrated circuit with a multiplexer system and a control circuit is described. The multiplexer system has an output terminal connected to an output pin of the integrated circuit and input terminals connected to internal nodes of the integrated circuit. In a normal mode the control circuit generates the control signals so that any one of the internal nodes is connected to the output pin so that the integrated circuit can function flexibly. In a test mode so that a different internal node is connected to the output pin in each cycle of a test clock signal.

Abstract: Built-in self-test (BIST) microcontroller integrated circuit adapted for logic verification. Microcontroller includes a plurality of hardware description language files representing a hierarchical description of the microcontroller, the plurality of hardware description language files including a library of circuit design elements, a plurality of library design circuit elements adapted to store a uniquely defined set of input and output signals to enable a logic BIST, and a plurality of latches adapted to store a plurality of values corresponding to a behavioral profile of a test clock.

Abstract: Method, apparatus, and computer readable medium for generating test vectors for an integrated circuit (IC) under test is described. In one example, a test function is specified using at least one elementary function that encapsulates program code associated with an architecture of the IC under test. An engine is configured with device description data for the IC under test. The engine is executed with the test function as parametric input to generate the test vectors. In one example, the IC under test comprises a programmable logic device (PLD) and the test vectors include configuration data for configuring a pattern in the PLD and at least one test vector for exercising the pattern. The test vectors may be applied directly to the device or through automatic test equipment (ATE). Alternatively, the test vectors may be applied to a IC design simulation of the device.

Abstract: Method and system for testing an integrated circuit and more particularly, for determining timing associated with an input or output of an embedded circuit, in an integrated circuit for testing are described. A bit is adjustably delayed with a first adjustable delay to provide a delayed bit. The delayed bit is provided to a bus, such as an input bus for example, of the embedded circuit as a second vector. A third vector is output from the embedded circuit responsive to the second vector. A fourth vector is obtained having second multiple bits. The fourth vector is compared with the third vector to determine a period of delay associated with at least approximately a maximum operating frequency of the embedded circuit.

Abstract: A method is used for configuring an electronic device to reduce a skew of a parameter. The method includes a step of incorporating a plurality of controllable built-in parameter variation adjusting circuits for effecting a small step-change in the parameter at different points of the electronic device for reducing said skew of the parameter. A specific example of the method is to incorporate one or a plurality of field programmable gate arrays for reducing the skew of time delays. Another method is using the capability of programmable data path and loading of FPGA to create programmable delay line and controllable delays.

Abstract: Memory circuitry is augmented with data validation circuitry that is closely coupled to the memory circuitry so that data read out of the memory for use in a validation operation does not have to pass through or to general-purpose routing or logic circuitry before it can be used by the data validation circuitry. The data validation circuitry compares the data read from the memory to other signals to determine whether or not there is a match. The data validation circuitry is preferably programmable to select which bits of a word read from the memory will actually be used in the data validation operation.

Abstract: A self test device includes an operational element determining unit that calculates, based on operation parameters for the time of operation of a board on which a reconfigurable device is mounted, operational elements used in the devices of the board for the operation, and non-operational elements; an element assignment determining unit that assigns a self-test target from among the non-operational elements; and a testing unit that makes a test signal transmit through a test path that passes through the test target.

Abstract: A method for debugging reconfigurable hardware is described. According to this method, all necessary debug information is written in each configuration cycle into a memory, which is then analyzed by the debugger.

Abstract: The present invention includes an apparatus and method to optimize a set of test designs to obtain complete coverage while reducing bit stream size for programmable fabric. Test designs are selected that do not result in lost coverage. The method selects a set of test designs, removes the set of test designs, and then determines if coverage is lost. If coverage is lost, the method creates a new set of test designs to test the lost coverage. If the new set of test designs is smaller than the removed set, the new set of test designs is added to the test design suite; otherwise the removed test designs are added back to the test design suite. The decision to add the new test designs or removed test designs is based on a number of criteria including evaluating the number of uniquely tested resources in each test design.

Abstract: Provision of configuration access to a programmable device such as a programmable logic device (PLD) via a boundary-scannable devices. In one embodiment a configuration controller is arranged to transfer configuration data that specify configuration access for the PLD. A scan controller is coupled to the configuration controller and arranged to generate boundary-scan signals responsive to configuration data from the configuration controller. At least one boundary-scannable device has a plurality of boundary-scan pins coupled to the scan controller, and a PLD is coupled to the boundary-scannable device.

Abstract: Integrated circuits such as programmable logic device integrated circuits are provided that have memory arrays. The memory arrays can be tested using configurable built in self test circuitry. The built in self test circuitry may have test control register circuitry and configurable state machine logic. The state machine logic may perform at-speed tests on a memory array and may provide test results to external equipment for analysis. A tester may be used to provide test control settings to the test control register circuitry. The test control settings may include march element settings for a march sequence. During testing, the configurable state machine logic may use the march element settings to generate march sequences. March sequences that have been generated in this way may be used in testing the memory array.