Substitution Of Previous Valid Data Patents (Class 714/747)
  • Patent number: 11893244
    Abstract: Recurrent Neural Networks (RNNs) wherein a non-volatile memory (NVM) array provides a memory bank for the RNN. The RNN may include a Neural Turning Machine (NTM) and the memory bank may be an NTM matrix stored in the NVM array. In some examples, a data storage device (DSD) that controls the NVM array includes both a data storage controller and a separate NTM controller. The separate NTM controller accesses the NTM matrix of the NVM array directly while bypassing flash translation layer (FTL) components of the data storage controller. Additionally, various majority wins error detection and correction procedures are described, as well as various disparity count-based procedures.
    Type: Grant
    Filed: October 12, 2021
    Date of Patent: February 6, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Daniel Joseph Linnen, Ariel Navon, Alexander Bazarsky, Ofir Pele
  • Patent number: 11770211
    Abstract: The technologies described herein are generally directed to changing error mitigation protocols used for a connection based on the quality of a network connection in a fifth generation (5G) network or other next generation networks. For example, a method described herein can include determining, by network equipment comprising a processor, that a quality of a connection between a user equipment and a network access point is below a connection quality threshold, with the connection employing a communications protocol using a first error mitigation process, and where the network access point enables respective access to services enabled via a communication network. The method can further include, based on the quality and the first error mitigation process, enabling, by the network equipment, a second error mitigation process of the communications protocol of the connection, the second error mitigation process being different than the first error mitigation process.
    Type: Grant
    Filed: September 14, 2021
    Date of Patent: September 26, 2023
    Assignees: AT&T INTELLECTUAL PROPERTY I, L.P., AT&T Technical Services Company, Inc.
    Inventors: Daniel Vivanco, David Ross Beppler, Slawomir Stawiarski
  • Patent number: 11579973
    Abstract: The present disclosure relates to methods and systems for implementing redundancy in memory controllers. The disclosed systems and methods utilize a row of memory blocks, such that each memory block in the row is associated with an independent media unit. Failures of the media units are not correlated, and therefore, a failure in one unit does not affect the data stored in the other units. Parity information associated with the data stored in the memory blocks is stored in a separate memory block. If the data in a single memory block has been corrupted, the data stored in the remaining memory blocks and the parity information is used to retrieve the corrupted data.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: February 14, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ashish Singhai, Ashwin Narasimha, Kenneth Alan Okin
  • Patent number: 11539571
    Abstract: IQ impairments compensation in sub-terahertz (sub-THz) communication is disclosed. According to some aspects, a user equipment (UE) determines an estimated in-phase (I) and quadrature phase (Q) impairment of the UE, the IQ impairment of the UE comprising a mismatch of phase and/or amplitude, between an I path and a Q path within an analog receiver circuitry of the UE, and reports the estimated IQ impairment of the UE to a base station (BS). The BS determines a pre-compensation to compensate for the estimated IQ impairment of the UE and uses the determined pre-compensation when transmitting to the UE.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: December 27, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: David Yunusov, Shay Landis, Idan Michael Horn
  • Patent number: 11438467
    Abstract: When a character required to be corrected is specified in a character string of a character recognition result, a plurality of candidate character strings are generated by using a substitution candidate for the specified character and not using a substitution candidate for a character other than the specified character, and one correct character string is finalized from the plurality of generated candidate character strings.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: September 6, 2022
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Shoji Tanaka
  • Patent number: 11146667
    Abstract: This disclosure describes techniques for a network interface controller (NIC) to communicate over a network according to a specified transmission communication protocol. The NIC receives, from a host processor, an indication of a data unit and an indication of a header template. The NIC generates, independent of the specified transmission communication protocol, metadata for transmitting a segment of the data unit over a network. The NIC generates, at last partly using the metadata, header fields that comply with the specified transmission communication protocol. The NIC processes the header template and the header fields to generate a packet header, and the NIC transmits, over the network, a packet including the packet header and the segment of the data unit.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: October 12, 2021
    Assignee: Cisco Technology, Inc.
    Inventors: Reese Faucette, David Walker
  • Patent number: 10938416
    Abstract: A memory device including a parity check circuit and a mask circuit may be provided. The parity check circuit may perform parity check on data sampled according to a data strobe signal, which does not include a post-amble. The mask circuit may generate a parity error signal based on results of the parity check, and output the parity error signal during a time period determined according to a burst length of the data.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: March 2, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hye-Seung Yu, Sukyong Kang, Wonjoo Yun, Hyunui Lee, Jae-Hun Jung
  • Patent number: 10803099
    Abstract: In embodiments of the disclosed technology, indexes, such as inverted indexes, are updated only as necessary to guarantee answer precision within predefined thresholds which are determined with little cost in comparison to the updates of the indexes themselves. With the present technology, a batch of daily updates can be processed in a matter of minutes, rather than a few hours for rebuilding an index, and a query may be answered with assurances that the results are accurate or within a threshold of accuracy.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: October 13, 2020
    Assignee: AT&T Intellectual Property I, L.P.
    Inventors: Marios Hadjieleftheriou, Nick Koudas, Divesh Srivastava
  • Patent number: 10593417
    Abstract: A memory system comprises a memory device including a plurality of memory blocks, the memory device being configured to perform a program operation and a program verify operation to program data to the memory blocks, and a controller configured to detect program error bit information as a result of the program verify operation, select a victim memory block among the memory blocks based on the detected program error bit information, and copy programmed data of the victim memory block.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: March 17, 2020
    Assignee: SK hynix Inc.
    Inventor: Jee-Yul Kim
  • Patent number: 10567123
    Abstract: A method for evaluating link or component quality using synthetic forward error correction (FEC) includes generating a bit sequence. The method further includes transmitting the bit sequence over a link or through a component under test without adding FEC to the bit sequence. The method further includes receiving a bit sequence transmitted over the link or through the component. The method further includes determining locations of bit errors in the received bit sequence. The method further includes determining locations of synthetic FEC codeword and symbol boundaries in the received bit sequence for the synthetic FEC algorithm against which link or component quality is being evaluated. The method further includes identifying symbol and codeword errors for the synthetic FEC algorithm based on the locations of bit errors in received bit sequence. The method further includes outputting an indication of link or component quality based on the symbol and codeword errors identified for the synthetic FEC algorithm.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: February 18, 2020
    Assignee: Keysight Technologies, Inc.
    Inventor: Gerald Raymond Pepper
  • Patent number: 10523004
    Abstract: An energy control system includes a facility model processor, a post VEE readings data stores, a VEE configuration engine, and a global model module. The facility model processor employs interval based energy consumption streams corresponding to a facility to develop and maintain weather-normalized baseline energy consumption data for the facility. The post VEE readings data stores tagged energy consumption data sets that are each associated with a corresponding one of said interval based energy consumption streams, each of said tagged energy consumption data sets comprising groups of contiguous interval values tagged as having been validated, wherein said groups correspond to correct data.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: December 31, 2019
    Assignee: ENEL X NORTH AMERICA, INC.
    Inventors: Elizabeth J. Main, Wendy Chen
  • Patent number: 10481206
    Abstract: A system that can include a computing device, upon implementing a host test program, can be configured to generate compiled host test instructions based on a non-host test program code that has been prepared in accordance with performance characteristics of a non-host automatic test equipment (ATE) and based on calibration data and/or offset data associated with a host ATE. The system can further include a hardware adapter that can be configured to generate non-host test signals based on host test signals generated by a host ATE and with substantially similar characteristics as test signals generated by the non-host ATE, wherein the host test signals are generated by the host ATE based on the compiled host test instructions.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: November 19, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ramana Tadepalli, Robert Gabriel Almendarez
  • Patent number: 10402250
    Abstract: A digital signage including a memory; a display; and a controller configured to display content on the display, capture a plurality of images of the displaced content, store the plurality of captured images in the memory, and display the stored images on the display in response to an error event signal.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: September 3, 2019
    Assignee: LG ELECTRONICS INC.
    Inventors: Seunghun Lee, Youngran Kim
  • Patent number: 10305543
    Abstract: The present invention relates to a device for transmission by power-line communication (1) between two items of equipment (10, 20) on board an aircraft (1), comprising a transmission cable (3) configured to simultaneously transmit a power supply current and a data signal. This cable (3) comprises two twisted pairs of conductors (34, 34a, 34b). The device comprises a data sender (100) comprising a COFDM coupler (44) configured to modulate a signal by carrier modulation according to a COFDM mode, and a data receiver (200) comprising a COFDM coupler (44) configured to demodulate a signal modulated by carrier modulation according to a COFDM mode. The data sender (100) is configured to send a test signal by carrier modulation according to a COFDM mode, while the data receiver (200) is configured to detect signals corresponding to the test signals sent, and to analyze the carriers of the detected signal in regard to the signal sent and deduce therefrom the state of the transmission cable (3).
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: May 28, 2019
    Assignee: SAFRAN ELECTRONICS & DEFENSE
    Inventor: Francois Guillot
  • Patent number: 10298012
    Abstract: An apparatus is provided for configuring validation, estimation, and editing (VEE) rules for performing VEE on a plurality of interval based energy consumption streams. The apparatus includes a network operations center, configured to receive the plurality of interval based energy consumption streams and is configured to perform VEE on the plurality of interval based energy consumption streams within a specified time period. The network operations center has a post VEE readings data stores and a rules processor. The post VEE readings data stores is configured to provide a plurality of tagged energy consumption data sets that are each associated with a corresponding one of the plurality of interval based energy consumption streams, each of the plurality of tagged energy consumption data sets including first groups of contiguous interval values tagged as having been validated and second groups of contiguous interval values tagged as having been edited.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: May 21, 2019
    Assignee: Enel X North America, Inc.
    Inventors: Elizabeth J. Main, Wendy Chen
  • Patent number: 10291022
    Abstract: An apparatus is provided for performing validation, estimation, and editing (VEE) on a plurality of interval based energy consumption streams. The apparatus has a network operations center, configured to receive the plurality of interval based energy consumption streams, and configured to perform VEE on the plurality of interval based energy consumption streams within a specified time period. The network operations center includes a VEE processor and a VEE configuration engine.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: May 14, 2019
    Assignee: Enel X North America, Inc.
    Inventors: Elizabeth J. Main, Wendy Chen
  • Patent number: 10262259
    Abstract: A method for selecting bit widths for a fixed point machine learning model includes evaluating a sensitivity of model accuracy to bit widths at each computational stage of the model. The method also includes selecting a bit width for parameters, and/or intermediate calculations in the computational stages of the mode. The bit width for the parameters and the bit width for the intermediate calculations may be different. The selected bit width may be determined based on the sensitivity evaluation.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: April 16, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Dexu Lin, Venkata Sreekanta Reddy Annapureddy, David Jonathan Julian, Casimir Matthew Wierzynski
  • Patent number: 10203714
    Abstract: A brown out prediction system is provided that performs validation, estimation, and editing (VEE) on a plurality of interval based energy consumption streams. The system includes a post VEE readings data stores, a rules processor, a peak prediction element, and a peak controller. The post VEE readings data stores is configured to provide a plurality of tagged energy consumption data sets. The rules processor is configured to read the post VEE readings data stores and is configured to create a plurality of anomalies having a plurality of differnt durations. The peak prediction element is coupled to the post VEE readings data stores and to weather stores, and is configured to receive post VEE readings. The peak controller is coupled to the peak prediction element, and is configured to receive the brown out time, and is configured to trigger exceptional measures to manage the cumulative energy consumption in order to preclude a brown out.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: February 12, 2019
    Assignee: Enel X North America, Inc.
    Inventors: Elizabeth J. Main, Wendy Chen
  • Patent number: 10191506
    Abstract: A demand response dispatch prediction system is provided that performs validation, estimation, and editing (VEE) on a plurality of interval based energy consumption streams. The system includes a post VEE readings data stores, a rules processor, and a dispatch prediction element. The post VEE readings data stores is configured to provide a plurality of tagged energy consumption data sets that are each associated with a corresponding one of the plurality of interval based energy consumption streams, each of the plurality of tagged energy consumption data sets comprising first groups of contiguous interval values tagged as having been validated and second groups of contiguous interval values tagged as having been edited.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: January 29, 2019
    Assignee: ENEL X NORTH AMERICA, INC.
    Inventors: Elizabeth J. Main, Wendy Chen
  • Patent number: 10170910
    Abstract: An energy baselining system is provided that performs validation, estimation, and editing (VEE). The system includes a facility model processor, a post VEE readings data stores, a VEE configuration engine, and a global model module. The facility model processor is configured to employ one or more interval based energy consumption streams corresponding to a facility to develop and maintain weather-normalized baseline energy consumption data for the facility, where the weather-normalized baseline energy consumption data is derived from training data for the facility. The post VEE readings data stores is configured to provide a plurality of tagged energy consumption data sets that are each associated with a corresponding one of the one or more interval based energy consumption streams, each of the plurality of tagged energy consumption data sets comprising first groups of contiguous interval values tagged as having been validated and second groups of contiguous interval values tagged as having been edited.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: January 1, 2019
    Assignee: Enel X North America, Inc.
    Inventors: Elizabeth J. Main, Wendy Chen
  • Patent number: 10120931
    Abstract: In embodiments of the disclosed technology, indexes, such as inverted indexes, are updated only as necessary to guarantee answer precision within predefined thresholds which are determined with little cost in comparison to the updates of the indexes themselves. With the present technology, a batch of daily updates can be processed in a matter of minutes, rather than a few hours for rebuilding an index, and a query may be answered with assurances that the results are accurate or within a threshold of accuracy.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: November 6, 2018
    Assignee: AT&T Intellectual Property I, L.P.
    Inventors: Marios Hadjieleftheriou, Nick Koudas, Divesh Srivastava
  • Patent number: 10096323
    Abstract: A frame error concealment method and apparatus and a decoding method and apparatus using the same. The frame error concealment method includes setting a concealment method to conceal an error based on one or more signal characteristics of an error frame having the error and concealing the error using the set concealment method.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: October 9, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ho-sang Sung, Kang-eun Lee, Jung-hoe Kim, Eun-mi Oh
  • Patent number: 9640244
    Abstract: A method and apparatus for pre-calibration of various system performance states is disclosed. In one embodiment, a method includes, for each of a number of different performance states (or operating points), performing initial calibrations of various parameters associated with transfers of data between a memory and a memory controller. After completing the initial calibrations, the calibrated values are stored. Thereafter, during normal operation and following a change to a new performance state, the values of the various parameters are set to the values to which they were calibrated during the initial calibration for that state.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: May 2, 2017
    Assignee: Apple Inc.
    Inventors: Robert E. Jeter, Rakesh L. Notani
  • Patent number: 9430376
    Abstract: Priority-based garbage collection utilizes attributes of data stored in the non-volatile memory array in order to improve efficiency of garbage collection and of the overall data storage system. A set of low priority data can be selectively evicted from a non-volatile memory array. This can, for example, reduce write amplification associated with garbage collection. Another set of low priority data can be regrouped or consolidated in a different region of the non-volatile memory array. In addition, flushing of data can be performed in order to enhance or optimize garbage collection. Performance and endurance can thereby be improved.
    Type: Grant
    Filed: December 26, 2012
    Date of Patent: August 30, 2016
    Assignee: Western Digital Technologies, Inc.
    Inventor: Robert L. Horn
  • Patent number: 9432151
    Abstract: An apparatus and a method for Automatic Repeat reQuest (ARQ) in a broadband wireless access system are provided. The method includes driving a timer which operates by a preset period to synchronize ARQ between the transmitter and a receiver; after transmitting data to the receiver without error, when a driving time of the timer expires, checking whether there is data to transmit to the receiver; when there is no data to transmit to the receiver, initializing the timer; and transmitting an ARQ reset message to the receiver. Hence, the air resource consumption and the power consumption in ARQ reset can be lowered by reducing unnecessary ARQ reset.
    Type: Grant
    Filed: November 7, 2008
    Date of Patent: August 30, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hye-Yeon Jeong, Sung-Wook Park, Jeong-Hoon Park
  • Patent number: 9264729
    Abstract: Video decoding device is disclosed. The video decoding device comprises a demultiplexer, a first decoder and a controller. The demultiplexer receives a Transport Stream to recover video Packetized Elementary Stream (PES) to determine a presentation time stamp (PTS) and a decoding time stamp (DTS) in a PES header of the PES. The first decoder retrieves a video frame from the video PES to determine temporal reference of the video frame. The controller receives the PTS, the DTS, and the temporal reference to determine whether there is a missing video frame.
    Type: Grant
    Filed: January 4, 2012
    Date of Patent: February 16, 2016
    Assignee: MEDIATEK INC.
    Inventors: Ying-Jui Chen, Chung-Bin Wu, Ya-Ting Chuang
  • Patent number: 9241281
    Abstract: A method includes identifying multiple statistics associated with each of multiple wireless connections. The multiple wireless connections form a single communication path between two wireless nodes in a wireless network. The method also includes identifying an overall quality associated with the communication path using the statistics. The method can also include assigning a quality value to each statistic for each wireless connection, where the overall quality is based on at least one of the quality values assigned to the statistics (such as a lowest of the quality values). The statistics could include a Received Signal Quality Indicator (RSQI), a Received Signal Strength Indication (RSSI), and a transmit success/fail ratio. The quality value assigned to each statistic could include a “good” quality, a “fair” quality, or a “poor” quality.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: January 19, 2016
    Assignee: Honeywell International Inc.
    Inventors: Christopher Pulini, Jeffrey B. Scott, Norman R. Swanson, Niral Sanghavi
  • Patent number: 9202041
    Abstract: This document discusses, among other things, an attack detection module configured to permanently shut down a slave device after a number of consecutive attacks.
    Type: Grant
    Filed: February 6, 2014
    Date of Patent: December 1, 2015
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Robert A. Card, Jefferson Hopkins, Christian Klein, Myron J. Miske, Michael Smith, John R. Turner, Jaeyoung Yoo
  • Patent number: 9165685
    Abstract: According to one embodiment, a semiconductor memory device includes semiconductor memory chips in which data requested to be written. The data has one or more pieces of first data in a predetermined unit. The device includes a write controller that writes the first data and redundancy information calculated by using a predetermined number of pieces of the first data and used for correcting an error in the predetermined number of pieces of the first data into different semiconductor memory chips; and a storage unit that stores identification information and region specifying information so as to be associated with each other. The identification information associates the first data and the redundancy information, and the region specifying information specifies a plurality of storage regions in the semiconductor memory chips to which the pieces of the first data and the redundancy information associated with each other are written.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: October 20, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigehiro Asano, Kenichiro Yoshii, Kazuhiro Fukutomi, Shinichi Kanno
  • Patent number: 9153237
    Abstract: Disclosed is an audio signal processing method comprising the steps of: receiving an audio signal containing current frame data; generating a first temporary output signal for the current frame when an error occurs in the current frame data, by carrying out frame error concealment with respect to the current frame data a random codebook; generating a parameter by carrying out one or more of short-term prediction, long-term prediction and a fixed codebook search based on the first temporary output signal; and memory updating the parameter for the next frame; wherein the parameter comprises one or more of pitch gain, pitch delay, fixed codebook gain and a fixed codebook.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: October 6, 2015
    Assignees: LG Electronics Inc., Industry-Academic Cooperation Foundation, Yonsei University
    Inventors: Hye Jeong Jeon, Dae Hwan Kim, Hong Goo Kang, Min Ki Lee, Byung Suk Lee, Gyu Hyeok Jeong
  • Patent number: 9136020
    Abstract: According to one embodiment, a semiconductor memory device includes semiconductor memory chips in which data requested to be written. The data has one or more pieces of first data in a predetermined unit. The device includes a write controller that writes the first data and redundancy information calculated by using a predetermined number of pieces of the first data and used for correcting an error in the predetermined number of pieces of the first data into different semiconductor memory chips; and a storage unit that stores identification information and region specifying information so as to be associated with each other. The identification information associates the first data and the redundancy information, and the region specifying information specifies a plurality of storage regions in the semiconductor memory chips to which the pieces of the first data and the redundancy information associated with each other are written.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: September 15, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigehiro Asano, Kenichiro Yoshii, Kazuhiro Fukutomi, Shinichi Kanno
  • Publication number: 20150143192
    Abstract: In a method of error recovery when downloading data files using an application server, the application server connects to at least one terminal device and several file servers. The application server receives a file downloading request from the terminal device, finds a first file server nearest to the terminal device, and downloads the required data file from the first file server to the terminal device. The application server searches a file configuration table to find a second file server which is away from the first file server when the data file has not been successfully downloaded from the first file server, downloads the required data file from the second file server to the terminal device, and synchronizes the data file of the second file server to recovery the data file of the first file server when the data file has been successfully downloaded from the second file server.
    Type: Application
    Filed: July 18, 2012
    Publication date: May 21, 2015
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Chung-I Lee, Hai-Hong Lin, De-Yi Xie, Hai-Yun Chen, An-Sheng Luo
  • Patent number: 9037934
    Abstract: A device for demultiplexing a packet-based transport stream of transport stream packets each provided with a systematic forward error detection code is described. The transport stream packets are each allocated to one of a plurality of data sinks, so that in a payload data section of the transport stream packets allocated to the same data sink a data stream of forward error protection code-protected data packets which are addressed to the respective data sink is embedded. The device determines, for a transport stream packet which is erroneous according to the systematic forward error detection code, a probability value for each of the plurality of data sinks which indicates how probable it is that the predetermined transport stream packet is allocated to the respective data sink, and allocates the predetermined transport stream packet to a selected one of the plurality of data sinks.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: May 19, 2015
    Assignee: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.
    Inventors: Andreas Mull, Christian Forster, Rainer Hildinger, Heinz Gerhaeuser
  • Patent number: 8909824
    Abstract: This invention relates to techniques for managing the transmission and reception of data fragments that contains one or more data blocks. One embodiment of the invention includes the following steps: processing the fragments sequentially, wherein each fragment has a processing index that corresponds to sequential processing of that fragment; processing each of the fragments until a termination upon meeting at least one pre-defined condition; assigning a timer to an un-terminated fragment having a lowest processing index; starting said timer having a timeout value; and running said timer until the processing of said un-terminated fragment is terminated.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: December 9, 2014
    Inventors: Yalun Li, William Li, Jr.
  • Patent number: 8873416
    Abstract: A method for estimating round-trip time (RTT) values for data packets travelling in a telecommunication network is disclosed. During a first time interval (206) which begins with the start of a data transmission, estimated RTT values (14) are generated by filtering a periodic sequence of RTT samples (12) with a self-initializing expanding memory polynomial (EMP) filter (16) and, after a first switch-over time at the end of the first time interval, the estimated RTT values are generated by filtering the RTT samples with a fading memory polynomial (FMP) filter (18). The first switch-over time is determined by comparing an FMP estimation error and an EMP estimation error, where the FMP estimation error is the difference between an output of the FMP filter and the RTT samples, and the EMP estimation error is the difference between an output of the EMP filter and the RTT samples, and triggering the first switch-over time when the FMP estimation error becomes equal to or less than the EMP estimation error.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: October 28, 2014
    Assignee: University of Cape Town
    Inventors: Guy-Alain Lusilao-Zodi, Norman Morrison
  • Patent number: 8868993
    Abstract: Systems and methods are provided for estimating missing samples in a signal. A plurality of samples in the signal is received, and a respective sample corresponds to a respective sample location in a plurality of sample locations. A subset of sample locations representing missing samples in the signal is identified, and a first and a second threshold are determined. Each threshold is an integer number of samples, and the second threshold is greater than the first threshold. A first set of consecutive sample locations from the identified subset of sample locations is formed, and the missing samples in the first set of consecutive sample locations are replaced based on a comparison between a number of locations in the first set of consecutive locations, the first threshold, and the second thresholds.
    Type: Grant
    Filed: April 13, 2012
    Date of Patent: October 21, 2014
    Assignee: Google Inc.
    Inventors: Kevin Yu, Xinyi Zhang
  • Patent number: 8843798
    Abstract: A frame error concealment method and apparatus and a decoding method and apparatus using the same. The frame error concealment method includes setting a concealment method to conceal an error based on one or more signal characteristics of an error frame having the error and concealing the error using the set concealment method.
    Type: Grant
    Filed: November 6, 2007
    Date of Patent: September 23, 2014
    Assignee: SAMSUNG Electronics Co., Ltd.
    Inventors: Ho-sang Sung, Kang-eun Lee, Jung-hoe Kim, Eun-mi Oh
  • Patent number: 8830914
    Abstract: An approach is provided for providing acknowledgement signaling. A transmission failure associated with data from a user equipment is determined. An allocation message is generated for signaling of the transmission failure to the user equipment. The allocation message provides allocation of resource for retransmission of the data.
    Type: Grant
    Filed: February 8, 2008
    Date of Patent: September 9, 2014
    Assignee: Nokia Corporation
    Inventors: Haiming Wang, Esa Malkamaki, Dajie Jiang
  • Patent number: 8826097
    Abstract: A data processing apparatus is provided which comprises a processor unit configured to perform data processing operations in response to a sequence of instructions and a storage unit configured to store data values for access by the processor unit when performing its data processing operations. Redundant error control data is stored in association with the data values, the redundant error control data enabling identification of an error in the data values. The data processing apparatus also comprises a data scrubbing unit configured to perform a data scrubbing process on at least a subset of the data values, the data scrubbing process comprising determining with reference to the redundant error control data if an error is present in that subset of data values and, where possible, correcting that error with reference to the redundant error control data.
    Type: Grant
    Filed: March 30, 2011
    Date of Patent: September 2, 2014
    Assignee: ARM Limited
    Inventors: Emre Özer, Sachin Satish Idgunji
  • Publication number: 20140245092
    Abstract: A method for content addressable memory (CAM) error recovery that includes detecting an error in an entry of a CAM, identifying an address of the entry in the CAM, copying data from the address in the backup random access memory (RAM) into the entry of the CAM to obtain a corrected CAM, clearing a results (first in first out) FIFO structure based on detecting the error, performing, using the corrected CAM, a match request stored in a replay FIFO structure to obtain a revised result, and storing the revised result in the results FIFO structure.
    Type: Application
    Filed: February 26, 2013
    Publication date: August 28, 2014
    Applicant: ORACLE INTERNATIONAL CORPORATION
    Inventors: Brian Edward Manula, Morten Schanke, Robert W. Wittosch
  • Publication number: 20140245093
    Abstract: A method for protecting a master boot record in a solid state drive, comprising the steps of (A) receiving a plurality of input/output requests from a host device, (B) determining whether one or more of the input/output requests is read/written to a first of a plurality of logical block addresses of the solid state drive and (C) writing an entry to a table for each of the input/output requests read/written to the first of the logical block addresses. The table (i) is separate from the first of the logical block addresses and (ii) is used to recover errors in the first of the logical block addresses.
    Type: Application
    Filed: March 11, 2013
    Publication date: August 28, 2014
    Applicant: LSI CORPORATION
    Inventors: Li Zhao Ma, Peng Xu, Ning Zhao, De Ling Li, Zhao Cui
  • Patent number: 8788900
    Abstract: According to one embodiment, a semiconductor memory device includes semiconductor memory chips in which data requested to be written. The data has one or more pieces of first data in a predetermined unit. The device includes a write controller that writes the first data and redundancy information calculated by using a predetermined number of pieces of the first data and used for correcting an error in the predetermined number of pieces of the first data into different semiconductor memory chips; and a storage unit that stores identification information and region specifying information so as to be associated with each other. The identification information associates the first data and the redundancy information, and the region specifying information specifies a plurality of storage regions in the semiconductor memory chips to which the pieces of the first data and the redundancy information associated with each other are written.
    Type: Grant
    Filed: April 23, 2013
    Date of Patent: July 22, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigehiro Asano, Kenichiro Yoshii, Kazuhiro Fukutomi, Shinichi Kanno
  • Patent number: 8782483
    Abstract: Embodiments related to retransmission in a communication system are described and depicted. In one embodiment, a retransmission entity repeats a transmission of a data transfer unit by the device after a predetermined number of other transmitted data transfer units has been transmitted. The retransmission entity may also determine whether a measure for a time period since the first transmission of the data transfer unit by the device has exceeded a predetermined threshold and to provide a final transmission of the data transfer unit based on the determining that the measure for the time period has exceeded the predetermined threshold.
    Type: Grant
    Filed: September 17, 2010
    Date of Patent: July 15, 2014
    Assignee: Lantiq Deutschland GmbH
    Inventors: Dietmar Schoppmeier, Gert Schedelbeck, Bernd Heise
  • Publication number: 20140164863
    Abstract: Examples are disclosed for generating or providing a moving read reference (MRR) table for recovering from a read error of one or more memory cells of a non-volatile memory included in a storage device. Priorities may be adaptively assigned to entries included in the MRR table and the entries may be ordered for use based on the assigned priorities. Other examples are described and claimed.
    Type: Application
    Filed: March 29, 2012
    Publication date: June 12, 2014
    Inventors: Lark-Hoon Leem, Kiran Pangal, Xin Guo
  • Patent number: 8750316
    Abstract: A communications system (100) includes a packet switching network (130) configured to transfer a stream of information packets from a source (110) to a destination (120). The communications system (100) also includes at least one loss concealment processor (140) configured to perform packet loss concealment on the stream of information packets as the stream passes through an intermediate point within the packet switching network (130).
    Type: Grant
    Filed: May 24, 2011
    Date of Patent: June 10, 2014
    Assignee: Verizon Laboratories Inc.
    Inventor: Adrian Evans Conway
  • Publication number: 20140143626
    Abstract: A device for demultiplexing a packet-based transport stream of transport stream packets each provided with a systematic forward error detection code, wherein the transport stream packets are each allocated to one of a plurality of data sinks, so that in a payload data section of the transport stream packets allocated to the same data sink a data stream of forward error protection code-protected data packets is embedded addressed to the respective data sink, the device being implemented to determine, for a predetermined transport stream packet which is erroneous according to the systematic forward error detection code, a probability value for each of the plurality of data sinks which indicates how probable it is that the predetermined transport stream packet is allocated to the respective data sink, and allocate the predetermined transport stream packet, on the basis of the probability values for the plurality of data sinks, to a selected one of the plurality of data sinks.
    Type: Application
    Filed: January 28, 2014
    Publication date: May 22, 2014
    Applicant: Fraunhofer-Gesellschaft zur Foerderung der Angewandten Forschung e.V.
    Inventors: Andreas MULL, Christian FORSTER, Rainer HILDINGER, Heinz GERHAEUSER
  • Publication number: 20140136915
    Abstract: A memory device includes but is not limited to a non-volatile memory array and control logic integrated with and distributed over the non-volatile memory array. The control logic can be operable to maintain a plurality of copies of data in the non-volatile memory array and detect errors by comparison of selected ones of the plurality of copies.
    Type: Application
    Filed: November 28, 2012
    Publication date: May 15, 2014
    Applicant: Elwha LLC, a limited liability corporation of the State of Delaware
    Inventor: Elwha LLC, a limited liability corporation of the State of Delaware
  • Patent number: 8719653
    Abstract: A frame error concealment method and apparatus and a decoding method and apparatus using the same. The frame error concealment method includes setting a concealment method to conceal an error based on one or more signal characteristics of an error frame having the error and concealing the error using the set concealment method.
    Type: Grant
    Filed: November 6, 2007
    Date of Patent: May 6, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho-sang Sung, Kang-eun Lee, Jung-hoe Kim, Eun-mi Oh
  • Patent number: 8718804
    Abstract: In an embodiment, a method of receiving a digital audio signal, using a processor, includes correcting the digital audio signal from lost data. Correcting includes copying frequency domain coefficients of the digital audio signal from a previous frame, adaptively adding random noise coefficients to the copied frequency domain coefficients, and scaling the random noise coefficients and the copied frequency domain coefficients to form recovered frequency domain coefficients. Scaling is controlled with a parameter representing a periodicity or harmonicity of the digital audio signal. A corrected audio signal is produced from the recovered frequency domain coefficients.
    Type: Grant
    Filed: May 4, 2010
    Date of Patent: May 6, 2014
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Yang Gao, Herve Taddei, Miao Lei
  • Patent number: 8677203
    Abstract: A method for data storage includes storing data in a memory that includes one or more memory units, each memory unit including memory blocks. The stored data is compacted by copying at least a portion of the data from a first memory block to a second memory block, and subsequently erasing the first memory block. Upon detecting a failure in the second memory block after copying the portion of the data and before erasure of the first memory block, the portion of the data is recovered by reading the portion from the first memory block.
    Type: Grant
    Filed: January 10, 2011
    Date of Patent: March 18, 2014
    Assignee: Apple Inc.
    Inventors: Ofir Shalvi, Naftali Sommer, Uri Perlmutter, Julian Vlaiko, Moshe Neerman