Abstract: One or more techniques provide majority detection in error recovery. Accordingly, a device retries reading an ECC codeword having one or more bits for a plurality of retries, and stores each retry. The device (“hard” majority detection) votes on a value of each bit of the codeword based on a majority of corresponding retry values in the plurality of corresponding retries. Also, the device (“soft” majority detection) may determine reliability information for a value of each bit of the codeword based on a reoccurrence ratio of corresponding retry values in the plurality of retries. The device may declare erasures based on the reliability information and a (dynamically adjusted) threshold of uncertainty, e.g., where an “uncertain” bit based on the threshold or any symbol with an “uncertain” bit is declared as an erasure.

Abstract: A method for near maximum-likelihood sequential decoding is provided. According to the method, paths unlikely to become the maximum-likely path are deleted during decoding through a level threshold to reduce decoding complexity. Besides, the method performs maximum-likelihood decoding through sequential decoding by adopting a metric, so that a received signal does not have to go through a hard decision procedure.

Abstract: A method of demapping in a receiver including deriving M intermediate soft bit values yj for the I and Q data of the input signal as a function of the spacing in the constellation; and limiting the range of the M values yj. A look-up table index is derived for each of the limited M values yj. A look-up table, having 2N+1 entries for supporting up to N soft bit outputs, is indexed using the derived indices; and K soft bits for each of the M values yj of the I and Q data are outputted.

Abstract: A method and apparatus for decoding received digital data representing video, audio, information or a combination thereof. After a forward error correction (FEC) frame sync lock is detected, a counter is incremented corresponding to the number of identical control words decoded from the received data. If the number of identical control words is above a threshold value, the control word is used to operate the decoder in a mode corresponding to the control word. Otherwise, the system repeats the operation of determining whether a FEC frame sync lock is detected.

Abstract: A data processing apparatus includes a non-volatile semiconductor memory configured to store a storage data and an additional data control circuit configured to generate an additional data and add the additional data to a main storage data, and the additional data is different between a first mode and a second mode. The additional data control circuit includes a first mode circuit configured to generate the additional data in the first mode; and a second mode circuit configured to generate the additional data in the second mode. The storage data contains a target data or an inversion data of the target data, as the main storage data and the additional data.

Abstract: A phase-change memory (PCM) includes a matrix of storage cells, including at least a first group with at least one cell. Each cell includes a phase change material having at least a first resistance value and a second resistance value, such that the first group can have an identical message encoded therein in at least a first way and a second way. The memory also includes a controller configured to encode the identical message in the at least first group the first or second way, based on which way causes the least amount of writing cost, given current levels of the group. Another embodiment of memory includes a matrix of storage cells, including at least a first group with at least one cell. Each of the storage cells has at least two levels, such that each of the storage cells can have an identical message encoded therein in at least a first way and a second way (the cells can be PCM or another technology).

Abstract: The invention relates to a decoding device particularly adapted to decode a digital input signal (E) in a transmission system using direct sequence spread spectrum, this digital input signal (E) being composed of symbols, each symbol representing a bit satisfying a Barker code, and comprising several symbol elements. This device comprises several finite response filters (FLT1 to FLT4) each of which receives the digital input signal (E), a clock circuit (CLK_GEN) outputting clock signals (CLK1 to CLK4) to the filters with a frequency equal to the frequency at which symbol elements are produced and uniformly distributed phase shifts, and an analysis circuit (ANL) designed to identify which of the filters is best tuned to the input signal (E) and to control the clock circuit to make it generated a clock signal (CLK5) optimised for decoding and an analysis circuit.

Abstract: Erasure detection and power control are performed for an intermittently active transport channel with unknown format. A receiver processes each received block and determines whether it passes or fails CRC. For each received block with CRC failure, the receiver performs erasure detection by computing a symbol error rate (SER) and energy of the received block, comparing the computed SER against an SER threshold, comparing the computed energy against an energy threshold, and declaring an erasure if the computed SER is less than the SER threshold and the computed energy exceeds the energy threshold. The SER and energy thresholds may be adjusted based on the average SER and the average energy for prior received blocks with CRC failures. For power control, an SIR target is increased by an UP step whenever an erased block is detected for the transport channel.

Abstract: A majority voter circuit is configured to generate a selecting signal based on first input data and inverted first input data. The first input data and the inverted first input data each include an odd-number of bits, and the odd-number of bits include bits of a first type and bits of a second type. The generated selecting signal is indicative of which of the first type and the second type of bits in the first input data are in the majority.

Abstract: A method of generating a code that minimizes error propagation by selecting integers m, n, mrl, and a range of fractions od, where m represents the number of bits in an unencoded sequence, where n represents the number of bits in an encoded sequence, where mrl represents the maximum run length of an encoded sequence, and where od represents a range of ones densities of an encoded sequence. Next, generating an encoding map M that maps each unencoded sequence to an n-bit encoded sequence that satisfies od and mrl. Next, generating a decoding map N that maps each n-bit sequence to an m-bit sequence. Next, determining an error-propagation score for M and N. Then, returning to the step of generating M if a user requires a lower error-propagation score.

Abstract: In one embodiment, a turbo equalizer has a channel detector that receives equalized samples and generates channel soft-output values. An LDPC decoder attempts to decode the channel soft-output values to recover an LDPC-encoded codeword. If the decoder converges on a trapping set, then an adjustment block selects one or more of the equalized samples based on one or more specified conditions and adjusts the selected equalized samples. Selection may be performed by identifying the locations of unsatisfied check nodes of the last local decoder iteration and selecting the equalized samples that correspond to bit nodes of the LDPC-encoded codeword that are connected to the unsatisfied check nodes. Adjustment of the equalized samples may be performed using any combination of scaling, offsetting, and saturation. Channel detection is then performed using the adjusted equalized samples to generate an updated set of channel soft-output values, which are subsequently decoded by the decoder.

Abstract: A system for enhancing the error correction capability of an error correction code (“ECC”) during error recovery operations accumulates, for respective bits, counts of the number of times the bits are detected as 1s in multiple re-reads of a data signal. The system then determines, based on the associated count, if a reconstructed bit should be considered a 1 or 0, or neither, that is, if the reconstructed bit should be considered erroneous, by comparing the count to a majority detection threshold and then to either an upper or a lower predetermined threshold that corresponds to the confidence with which the bit is reconstructed as a either a 1 or a 0. If the confidence is sufficiently low, that is, if the count falls below the upper threshold or above the lower threshold, the reconstructed bit is flagged as erroneous.

Abstract: A system and method for reducing power consumption in a Low Density Parity-Check Code (LDPC) decoder includes a sleep mode checking module and a gating circuit. The sleep mode checking module checks whether a check node is in sleep mode. The check node is considered to be in sleep mode when the absolute value of the message going to each of the one or more bit nodes corresponding to the check node is greater than a threshold value. The gating circuit turns OFF a Check Node and Bit Node Update Unit (CNBNU) associated with the check node when the check node is in the sleep mode. Turning OFF a CNBNU stops the exchange of messages between the check node and its corresponding one or more bit nodes.

Abstract: Briefly, a method, main processing unit and a computer system to report a failure in a bit of a memory line by updating first and second counters for a first time and a second time correction of bit failures in a line, respectively. The updating of first and second counters after a third time correction of bit failure in the line is disabled.

Abstract: A convolutional interleaving and de-interleaving circuit and the method thereof are provided. The convolutional interleaving and de-interleaving circuit includes an initial address generator, a first address generator, a second address generator, an address mixer, an adder, a controller and a memory. Wherein, the controller enables those address generators to provide or store corresponding channel addresses. Further, an adder is shared and memory addresses are appropriately arranged so as to reduce the requirement of registers. Accordingly, the required gate count and the chip layout area can be reduced.

Abstract: A bit failure detection circuit supports reliability testing of a memory device by accumulating a sum of data errors in data read from the memory device. The detection circuit compares a plurality of bytes of data read from the memory device against a plurality of bytes of reference data supplied during a test operation. The detection circuit also generates a flag upon detection that the sum of data errors exceeds a threshold number of acceptable data errors.

Abstract: Techniques for performing erasure detection and power control for a transmission without error detection coding are described. For erasure detection, a transmitter transmits codewords via a wireless channel. A receiver computes a metric for each received codeword, compares the computed metric against an erasure threshold, and declares the received codeword to be “erased” or “non-erased”. The receiver dynamically adjusts the transmit power based on whether the codewords met the erasure threshold or not.

Abstract: An error detection and correction apparatus includes three threshold logic units which make decisions based on current and previous bit values in a bit stream of block-coded data. One of the threshold logic units decodes the data stream based on an advancing time stream of data. Another threshold logic unit decodes the data stream based on a time-reversed stream of data, and the last threshold logic unit decodes the data stream based on a time-reversed input stream of data and a time-reversed set of decisions made by the first threshold logic unit. Each threshold logic unit generates decisions and a parity check of those decisions Error identification information is compared between the three streams of decisions and parity checks on those decisions, thereby producing error information, which is processed by a circuit which determines which is the most likely data transmitted.

Abstract: A receiving apparatus in a communication system in which when a systematically encoded signal cannot be decoded correctly on a receiving side, the signal is retransmitted from a transmitting side. The receiving apparatus combines stored data, which has been generated based upon data already received, and newly received data, decides a range of quantization levels of the combined data using an average level only of systematic bits of the stored data and newly received data, quantizes the combined data based upon the range of quantization levels and number of quantization bits, applies decoding processing to the quantized data, notifies the transmitting side of whether decoding could be performed correctly, and stores the combined data as the stored data when decoding cannot be performed correctly.

Abstract: A receiver comprises multiple receiving antennas configured to receive bitstreams transmitted from multiple transmission antennas; a bitstream candidate estimator configured to estimate a prescribed number of bitstream candidates among possible combinations of the received bitstreams and to calculate reliability information for each of the candidates; a bit-based estimator configured to produce a bit-based estimation result for each bit of the transmitted bitstreams based on the estimated candidates and the associated reliability information, the bit-based estimation result being adjusted by an adjusting criterion determined by the reliability information; and a decoder configured to decode the transmitted bitstreams based on the adjusted bit-based estimation result.

Abstract: A decoder device includes: a decoder that decodes data stored in a storage medium by performing error correction on the data, the error correction being capable of correcting code error and code erasure included in the data; a memory that stores a history of an address in the storage medium of a code included in the data, the code being detected to have the code error by the decoding unit; and a controller that controls the decoder to change a detail of the error correction based on the history stored in the memory.

Abstract: The information processing method of the present invention detects redundant circuits as described below by means of an information processor that is provided with: a storage unit for storing circuit operation information that uses hardware description language and a library for performing a logic synthesis of the circuit operation information and converting to a net list; and a display unit. The information processor hierarchically arranges statement by statement the circuit operation information that is stored in the storage unit, and then refers to the library, performs a logic synthesis of the circuit operation information that has been hierarchically arranged and converts to a net list. The information processor then detects redundant fault sites, which are sites that are logically redundant from the net list, and displays information showing the redundant circuits that contain the redundant fault sites on the display unit.

Abstract: A method of detecting two-dimensional codes using a plurality of light and dark data bits arranged two-dimensionally. The method includes detecting the code as a gray scale value image, splitting the detected gray scale value image into image areas corresponding to the individual data bits, determining a binarizing threshold representing a specific gray scale value for the image areas, carrying out a respective binarizing of the gray scale value of the individual image areas by means of a binarizing threshold to produce a bit sequence which represents the data bits and consists of the values 0 and 1, supplying the bit sequence to an error correction algorithm to recognize and/or correct bit errors within the bit sequence, identifying uncertain image areas whose gray scale values each lie close to the binarizing threshold, and taking the uncertain image areas into special account in the error correction.

Abstract: Properly detects an anomaly on the basis of directional data that are obtained in sequence from a monitored object.

Abstract: Disclosed is an apparatus and method for increasing the error correction capabilities of a receiver circuit that receives a data stream of encoded data symbols that are encoded with a linear block code. Analog and digital comparator circuits are used to detect laser clipping or analog to digital converter overloading. Corrupted symbols are detected by comparing in-phase and/or quadrature phase baseband signals with pre-determined threshold limits that indicate that the in-phase and quadrature phase signals have exceeded the normal signal trajectory of an unimpaired signal. Corrupted symbols may also be detected by determining that the laser has been clipped. Corrupted symbols are marked for erasure prior to decoding and error correction. Erasure of corrupted signals increases the error correction capabilities of the decoder circuit.

Abstract: A method and apparatus for selectively terminating turbo equalization is disclosed. At least two iterations of turbo equalization are performed. The number of errors corrected between the first iteration and the second iteration are calculated. In one embodiment, if the sign of corresponding bits in the data block is different between the two iterations, an error was corrected. If the number of errors corrected is greater than a stopping value, a subsequent iteration of turbo equalization is performed. If the number of errors corrected is less than or equal to the stopping value, then associated values for the data are output and the turbo equalization is terminated.

Abstract: Disclosed is a method and communication device for suppressing interference. The method comprises performing, with a turbo decoder (314), at least one turbo decoding attempt (1106) on a received signal (1104). The turbo decoding attempt generates at least one whole word code bit therefrom (1108). The whole word code bit (1108) corresponds to a group of bits comprising a transmitted symbol. The method determines if the whole word code bit (1108) has a confidence level exceeding a given threshold (1110). If the whole word code bit (1108) does have a confidence level exceeding the given threshold, the whole code word bit is selected for use in data symbol recovery (1114).

Abstract: The soft decision thresholds in a soft decision forward error correction (FEC) system may be adjusted based on mutual information of a detected signal. In one embodiment, a recursive algorithm may be used to optimize threshold values by maximizing the mutual information. In another embodiment, an adaptive scheme may be used to optimize threshold values based on a pre-knowledge of the noise in the channel. In a further embodiment, an adaptive scheme may be used to optimize threshold values by without pre-knowledge of the noise in the channel.

Abstract: In one aspect the invention is a method for decoding. The method includes receiving encoded data and decoding the encoded data using a noise-adaptive decoder. The data may include first-order Reed-Mueller (FORM) based codes. The data may be based on Complementary Code Keying. Using a noise-adaptive decoder may include determining values of a hard decision based on a first decoding process and discarding the values of the hard decision if a noise sensitivity parameter is above a threshold value. The method may further include using a second decoder process if the noise sensitivity parameter is above the threshold value.

Abstract: A threshold value is set in a decision circuit receiving a transmitted stream of binary symbols from a network link. The decision circuit uses the threshold value for detecting whether a 1 or a 0 is received to produce an output stream having a low bit error rate. Bit errors in the output stream of the detector are detected. The number of errors is counted when a transmitted 0 is detected as a 1 in the output stream. The number of errors is also counted when a transmitted 1 is detected as a 0 in the output stream. The counted numbers of errors are compared to each other. The threshold value is modified, if necessary, based on the result of the comparing, to e.g. make the probabilities of the two kinds of errors equal to each other. Extra predetermined bits can be inserted and used in determining bit errors.

Abstract: A method is described for FEC decoding a signal which has become affected by transmission errors, the original signal being transmitted together with parity data. The method comprises: receiving (5) the original signal (DATA) and parity data (ECC DATA) with errors; checking (6) for integrity thereof; and counting and locating the errors (7). The method is characterized by comprising: setting at leat one error threshold; comparing (11) the number of counted errors with the set threshold; and performing the correction (8) only in case the number of counted errors is lower than the threshold. Through the present invention, the problem of introduction of further errors during the decoding step is advantageously avoided.

Abstract: Based on an expected error rate for a wireless transmission, the length of the transmission may be limited so that the probability of an error in one or more particular data segments is no greater than a predetermined threshold value. The expected error rate and/or the threshold value may be periodically changed, based on various criteria.

Abstract: A technique of decoding a biphase signal comprises sampling the biphase signal to obtain phase sample values and sampling the biphase signal to obtain magnitude sample values. A first digital signal is derived from the phase sample values and associated bit combinations are formed from the first digital signal. A decision is made whether the bit combination is an erroneous bit combination, and a probability check is performed to obtain probability values that decide which parts of the erroneous bit combination are true and which are false. A corrected bit combination is generated from the obtained probability values, and a second digital signal is generated whose data states are formed from the valid bit combination and, in the presence of an erroneous bit combination, from the corrected bit combination.

Abstract: In one aspect this invention provides a method to operate a decoder, and a decoder that operates in accordance with the method. The method includes monitoring, during operation of the decoder on a signal received from a channel, the value of at least one extrinsic value; and based on the monitored at least one value, determining whether the signal comprises a valid code word or comprises only noise. In a preferred, but non-limiting embodiment, the decoder comprises one of a LogMap or a MaxLogMap turbo decoder, and the decoder forms a part of a baseband section of a wideband code division multiple access (WCDMA) user equipment. During the process of decoding rounds the absolute values of extrinsic values tend to increase, provided that the input signal contains a valid code word, as opposed to when the input signal contains only noise, and where determining accurately distinguishes a valid code word from noise, and may also obtain information that is indicative of the quality of the decoding process.

Abstract: Techniques are provided for performing early decoding of a message on a control channel in a wireless (e.g., GSM) communication system. In a GSM system, a message for a paging channel is transmitted in four bursts. For early decoding in GSM, a terminal initially receives the first two bursts for the message. The two bursts are processed and decoded to recover the message, which is then checked to determine whether it has been decoded correctly or in error. The decoding process can terminate and the terminal may go to sleep early if the recovered message is good. Otherwise, the third burst is received, and all three bursts are processed and decoded to recover the message. Again, the decoding process can terminate if the recovered message is good. Otherwise, the fourth burst is received, and all four bursts are processed and decoded to recover the message.

Abstract: In general, in one aspect, the disclosure describes an apparatus that includes a transmission module to split a data segment into a plurality of data stripes and transmit each data stripe over an associated data channel. The plurality of data channels are organized into at least one group and each group has an associated parity channel to transmit a parity stripe generated based on the data stripes within the group. The apparatus also includes a reception module to receive the plurality of data stripes and the at least one parity stripe. The apparatus further includes a controller to control the operation of the apparatus.

Abstract: A multicast service of a 3GPP Universal Mobile Telecommunications System (UMTS) is disclosed. By allowing an RNC to manage multicast group member information by multicast services on multicast areas, when a user terminal being currently provided with an MBMS service moves, the RNC sends information on the movement of the terminal to a core network. Since the RNC notifies the core network of the terminal's movement selectively on the basis of the multicast group member information by multicast services on the multicast area, the network resource can be effectively used, and especially, unnecessary transmission of terminal's movement information from the RNC to the multicast group managing entity of the core network can be prevented.

Abstract: A method decodes a received word for a binary linear block code based on a finite geometry. First, a parity check matrix representation of the code is defined. The received word is stored in a channel register. An active register represents a current state of the decoder. Each element in the active register can take three states, representing the two possible states of the corresponding bit in the word, and a third state representing uncertainty. Votes from parity checks to elements of the active register are determined from parity checks in the matrix, and the current state of the active register. A recommendation and strength of recommendation for each element in the active register is determined from the votes. The elements in the active register are then updated by comparing the recommendation and strength of recommendation with two thresholds, and the state of the corresponding bit in the received word. When termination conditions are satisfied, the decoder outputs the state of the active register.

Abstract: A technique of decoding erroneous biphase signals is disclosed comprising the following steps. First, phase and magnitude sample values (ps, bs) are formed, from which a first digital signal (d1) is derived. From this, associated bit combinations (St1, St2; Stp) are determined, and a decision is made as to whether the respective bit combination (St1, St2; Stp) is a valid combination (Sg1, Sg2; Sgp) or an erroneous one (Sf1, Sf2; Sfp). Probability values (Sw1, Sw2; Swp) are determined that decide which parts of the erroneous bit combination (Sf1, Sf2; Sfp) are probably true and/or which are probably false. Next, a corrected bit combination (Sk1, Sk2; Skp) is formed from the existing information. Finally, a second digital signal (d2) is generated as an output signal, whose data states are formed either from the valid bit combination (Sg1, Sg2; Sgp) or from the corrected bit combination (Sk1, Sk2; Skp).

Abstract: A method and an apparatus for reducing power consumption of a decoder in a communication system are disclosed. In a communication system communicating a packet, the packet can be arranged among slots of a communication channel so that each slot following the first slot contains redundant bits of the packet with respect to the first slot. A receiving station estimates quality metric of a received slot, determines a quality metric threshold, and delimits an interval in accordance with the modified quality metric threshold. If the estimated quality metric is outside of the interval, the segment is decoded.

Abstract: Method and apparatus for determining the stopping point of an iterative decoding process. In one embodiment the estimated values of an iteration of an iterative decoder are provided to a signature circuit. If the signature does not differ from the previous signature developed from a prior iteration, or the signature developed from an iteration prior to the previous iteration, the decoding stops. The variance may also be tested and compared to a threshold as a criteria to stop the iterative decoding.

Abstract: A switching circuit, for use in soft-decision Extended Hamming Code decoding, allows the detection of pairs of received bits having “low confidence” and whose position-ids SUM to the syndrome of the received code signal, when the occurrence of an even (and non-zero) number of errors is detected.

Abstract: The present invention provides a word voter for redundant systems with n modules wherein each of these n modules generates a word output. The word voter receives word outputs from each of the n modules. A voter decision is generated by the word voter utilizing a word basis of the word output of each of the n modules. The voter is based on a majority voting principle. The advantage of the present invention is that the word voter can be used to design redundant systems, such as, but not limited to, TMR systems, that are protected against common mode and multiple output failures. In addition, another advantage of the present invention is that is provides for a technique to efficiently design a TMR simplex system. The present invention provides a word voter for hardware systems.

Abstract: An encoder for encoding a data word with a plurality of bits, wherein the data word is transmittable in parallel on a data bus, wherein one bit line is provided for each bit and wherein each bit may have one of two logical states, including a means for examining the data word in order to determine whether a first number of bits of the data word with a first logical state deviates from a second number of bits of the data word with a second logical state by more than a predetermined threshold, a means for changing the state of a bit of the data word in order to create an encoded data word in case the predetermined threshold is exceeded by the data word, and a means for detecting auxiliary information referring to the changed bit.

Abstract: A system that adapts wireless link parameters for a wireless communication link. A measure is determined of errors occurring in communication over a wireless link. In a case that the measure of errors corresponds to more errors than a first predetermined threshold, communication changes from a first set of wireless link parameters to a second set of wireless link parameters. The second set of wireless link parameters corresponds to higher error tolerance than the first set of wireless link parameters. In a case that the measure of errors corresponds to fewer errors than a second predetermined threshold, communication changes from the first set of wireless link parameters to a third set of wireless link parameters. The third set of wireless link parameters corresponds to lower error tolerance than the first set of wireless link parameters. Preferably, the measure of errors is determined by monitoring a number of NACK messages and a number of ACK messages that occur.

Abstract: A method is described for FEC decoding a signal which has become affected by transmission errors, the original signal being transmitted together with parity data. The method comprises: receiving (5) the original signal (DATA) and parity data (ECC DATA) with errors; checking (6) for integrity thereof; and counting and locating the errors (7). The method is characterized by comprising: setting at leat one error threshold; comparing (11) the number of counted errors with the set threshold; and performing the correction (8) only in case the number of counted errors is lower than the threshold. Through the present invention, the problem of introduction of further errors during the decoding step is advantageously avoided.

Abstract: A method of, and apparatus for, slicing a modulated input signal is disclosed. The method comprises: generating at least one slice threshold level (20); comparing (3) the magnitude of the input signal (1) with the at least one threshold level to produce a corresponding sliced signal having a first magnitude if the input signal is greater than the threshold level and having a second magnitude if the input signal is less than the threshold level. The method further comprises detecting errors (5) in the sliced signal and producing a corresponding error signal; and setting the threshold level in response to the error signal.

Abstract: Method and apparatus for determining the stopping point of an iterative decoding process. In one embodiment the estimated values of an iteration of an iterative decoder are provided to a signature circuit. If the signature does not differ from the previous signature developed from a prior iteration, or the signature developed from an iteration prior to the previous iteration, the decoding stops. The variance may also be tested and compared to a threshold as a criteria to stop the iterative decoding.

Abstract: A circuit performs threshold normalization of accumulated transition probabilities for a given state of a state transition trellis in a maximum likelihood detector. Threshold normalization may be accomplished by comparison and setting of a single bit in stored transition probabilities. Threshold value comparison may be accomplished by comparing the bth bit of the stored transition probabilities if the threshold value is 2b. When all transition probabilities exceed the threshold value at a stage of the trellis, the transition probabilities are scaled, such as by subtracting the threshold value. Scaling may be implemented by setting the compared bth bits to zero before storage. In general, since accumulated transition probabilities are monotonically increasing for transition probabilities of paths through the trellis in both forward and reverse directions, the present invention may be employed for both threshold normalization of both the forward (&agr;) and reverse (&bgr;) transition probabilities.

Abstract: A system and method are provided for temporally analyzing serial input data. The method comprises: establishing three thresholds; distinguishing present (first) high probability one bit value estimates; distinguishing present high probability zero bit value estimates; and, using a temporal analysis of bit values to distinguish indefinite present bit value estimates. Using a temporal analysis of bit values includes: distinguishing a present bit estimate below first threshold and above the third threshold as a zero if both the past (second) and the future (third) bits are one values and otherwise as a one; and, distinguishing a present bit value estimate above the second threshold and below the third threshold as a one if both the past and future bits are a zero value and otherwise as a zero.