Threshold Decoding (e.g., Majority Logic) Patents (Class 714/760)
  • Publication number: 20030108114
    Abstract: A method for interleaving data in packet based communications includes interleaving elements of data in a source sequence to form an interleaved sequence and transmitting the interleaved sequence of the elements of the data. Adjacent elements of data in the interleaved sequence originally were separated by a first number of elements of data in the source sequence. Additionally, originally adjacent elements of data in the source sequence are separated by at least a second number of elements of data in the interleaved sequence.
    Type: Application
    Filed: December 10, 2001
    Publication date: June 12, 2003
    Applicant: University of Rochester
    Inventors: Mark F. Bocko, James Trek
  • Patent number: 6167552
    Abstract: An encoder and decoder for generating and decoding convolutional codes of improved orthogonality. In an exemplary embodiment the encoder includes a K-bit length shift register for receiving an input serial stream of information bits and providing for each input bit a K-bit parallel output to a self-doubly orthogonal code sequence generator. The encoded symbol stream is threshold decoded iteratively using the inversion of the convolutional self-doubly orthogonal parity code generators.
    Type: Grant
    Filed: October 2, 1997
    Date of Patent: December 26, 2000
    Assignee: Harris Corporation
    Inventors: Francois Gagnon, David Haccoun, Naim Batani, Christian Cardinal
  • Patent number: 6061820
    Abstract: A scheme for error control on AAL in ATM networks capable of realizing a reliable communication with a high throughput and a low latency. On AAL, the segmented data are sequentially written into each column of a matrix shaped data region in an interleaver, while variably setting a last column of the data region in the interleaver. Then, an error control code for the data up to the last column in each row of the data region in the interleaver is obtained and written into a corresponding location within a matrix shaped error control code region in the interleaver. The contents of each column of the data region and the error control code region in the interleaver are then read out, and a prescribed header/trailer is attached to a prescribed number of columns of the data and/or the error control codes read out from the interleaver to form a data unit.
    Type: Grant
    Filed: December 28, 1995
    Date of Patent: May 9, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kumiko Nakakita, Keiji Tsunoda
  • Patent number: 6044486
    Abstract: A method and device for error-correcting a plurality of bits transmitted over RF channels in a cellular communication system are provided. The present invention applies principles of majority voting to error-correct a plurality of bits in a message word simultaneously. Further, the present invention applies its error-correction capability to virtually any number of repeat transmissions over forward and reverse control/voice channels. Following synchronization of the transmit and receive stations, a message word having n-bits is transmitted repeatedly. The repeat bits are separated and analyzed whereafter the true logical state of the original n-bits is determined. The originally transmitted message word is then reconstructed based upon the determined true logical state of the n-bits.
    Type: Grant
    Filed: September 11, 1997
    Date of Patent: March 28, 2000
    Assignee: Uniden America Corporation
    Inventors: Mark Underseth, Nobusuke Matsuoka