Abstract: A signal detector/decoder is implemented in multiple stages. The beginning stage is configured to input channel data bits and to output hard data bits based on the channel bits and a maximum likelihood (ML) path. The next stage includes a postcoder coupled to receive channel domain information from the first stage and to convert the channel domain information to user domain information. The final stage includes a reliability unit coupled to receive the user domain information from the postcoder and to output user domain soft information for the hard data bits based on the ML path estimation and the user domain information.

Abstract: A digital communication receiver uses a maximum likelihood sequence estimation stage to recover symbols from digitized sample values of a received signal. A probability density function is calculated and used to improve a soft decision forward error correction calculation. The results of error decoding, which represent error corrected data bits, are further used to improve the probability density function calculation.

Abstract: A wireless communication apparatus in a hierarchically coded modulation system can use error control mechanisms generated during decoding of base layer information to predict a probability of successful demodulation of enhancement layer information. Performance in the demodulation of the base layer correlates to performance in the demodulation of the enhancement layer. The receiver can determine whether to attempt demodulation of temporally correlated enhancement layer data based in part on the predicted probability of success. If the receiver determines not to demodulate the enhancement layer, the receiver can power down the enhancement layer demodulator, or otherwise minimize the power expended in the enhancement layer demodulator.

Abstract: In a network for reliable transfer of packets from a transmitter to a receiver using an Internet Protocol (IP), a system for packet recovery comprising a detection block (detector) for packet loss detection and a probe device (probe) for Forward Error Correction (FEC) packets transmission, wherein the detector includes means for sending a missing packet report to the probe upon detecting a missing packet, wherein the probe includes means for storing received packets, sending FEC packets and adapting a size of the FEC packets to an error rate computed from the missing packet reports, wherein the size of FEC packets is made larger or smaller responsive to the error rate increasing or decreasing, respectively, and wherein the probe is located close to the transmitter for reliable packets reception and the detector is located close to the receiver for reliably detecting loss of packets in a receiver's surroundings.

Abstract: A method includes, in a memory controller that controls a memory, receiving from a host a read command that specifies data to be retrieved from the memory and further specifies a target error performance to be achieved in retrieving the data. A data retrieval configuration is selected in the memory controller depending on the target error performance specified in the read command. The data is retrieved from the memory using the selected data retrieval configuration, and the retrieved data is output to the host.

Abstract: Embodiments of the present invention provide multi-level signal memory with LDPC and interleaving. Thus, various embodiments of the present invention provide a memory apparatus that includes a memory block comprising a plurality of memory cells, each memory cell adapted to operate with multi-level signals. Such a memory apparatus also includes a low density parity check (LDPC) coder to LDPC code data values to be written into the memory cells and an interleaver adapted to apply bit interleaved code modulation (BICM) to the LDPC coded data values to generate BICM coded data values. Other embodiments may be described and claimed.

Abstract: Apparatus having corresponding methods and storage devices comprise: an iterative decoder configured to generate codewords based on input samples, wherein the iterative decoder is further configured to perform a number of decoding iterations for each codeword, wherein the number of decoding iterations is an integer greater than zero, and wherein the number of decoding iterations does not exceed a limit number; and a sensor configured to generate one or more measurements of a physical variable, wherein the limit number is set in accordance with the one or more measurements generated by the sensor.

Abstract: Disclosed herein is a nonvolatile memory including: a nonvolatile memory cell device including at least a nonvolatile memory cell array accessible in units of a word and further accessible at least with a fixed latency in a first access mode and with a variable latency in a second access mode; a first access path used in the first access mode; a second access path used in the second access mode; a first ECC processing part configured to be connected to the first access path and to perform error detection and correction using an ECC on the data output from the nonvolatile memory cell array in the first access mode; and a second ECC processing part configured to be connected to the second access path and to perform error detection and correction using the ECC on the data output from the nonvolatile memory cell array in the second access mode.

Abstract: A method may be performed at a data storage device that includes a memory and a controller. The method includes providing user data to a variable-bit error correction coding (ECC) encoder. The ECC encoder generates a first set of parity bits. A first number of parity bits in the first set of parity bits is determined based on stored counts of read errors. The method also includes storing the user data and the first set of parity bits to a memory of the data storage device.

Abstract: A method, computer readable medium, and system for implementing adaptive forward error correction in a network includes converting at a first computing device a number K of original data packets into a number N of error correction packets for forward error correction for a transmission to a second computing device. A subset number S1 of the number N of the error correction packets which is less than the number N of error correction packets is determined at the first computing device based on a loss rate for the transmission to the second computing device. The determined subset number S1 of the number N of the error correction packets is transmitted from the first computing device to the second computing device.

Abstract: According to one embodiment, a decoder includes a control unit and a decoding unit. The control unit determines a window size applied to a first target frame to be a first value and determines a window size applied to a second target frame different from the first target frame to be a second value different from the first value. The decoding unit carries out windowed decoding of a spatially coupled code on the first target frame with the window size set to the first value and carries out windowed decoding of a spatially coupled code on the second target frame with the window size set to the second value.

Abstract: In one embodiment, a circular pipeline processing system is provided. The system includes a plurality of processing stages configured to operate in a circular pipeline. Each processing stage is configured to output a fully processed data block in response to completing a final processing iteration, and otherwise, store a partially processed data block in a memory buffer of the processing stage. Each processing stage is configured to select between an unprocessed data block and a partially processed data block from the memory buffer of a preceding processing stage, based on one or more of availability of memory sufficient for storage of an unprocessed data block or availability of a partially processed data block. The processing stage is configured to process the selected data block.

Abstract: A semiconductor integrated circuit pertaining to the present invention comprises a plurality of storage elements for storing and holding an input signal, a majority circuit that outputs a result of a majority decision of outputs from the plurality of storage elements; an error detector circuit that detects a mismatch among the outputs of the plurality of storage elements and outputs error signals; and a monitor circuit that monitors the error signals from the error detector circuit, wherein the monitor circuit, based on the error signals, orders a refresh action that rewrites data for rectification to a storage element in which an output mismatch occurs out of the plurality of storage elements and, if rewrite and rectification by the refresh action are unsuccessful, sends a notification to an external unit or process.

Abstract: A data processing device including a controller configured to control the data processing device to execute steps of: receiving a data packet comprising a group identification information that identifies a restoration group, with which the data packet is associated, and redundant data for restoring a lost data packet, which is associated with the restoration group identified by the group identification information; determining whether a received amount of data packet associated with the restoration group identified by the group identification information is equal to or greater than a predetermined value; and restoring the lost data packet associated with the restoration group identified by the group identification information when the received amount of data packet associated with the restoration group identified by the group identification information is equal to or greater than the predetermined value.

Abstract: An exemplary communications receiver includes an error detector for determining whether a first and second received frame is corrupted, each frame comprising of a plurality of bits. The receiver includes a filter for determining whether the second received corrupted frame should be recovered. The receiver includes a frame generator for generating a recovered frame based on the plurality of bits of the first and second corrupted frame and frame information of the second corrupted frame, in response to the error detector determining that the first and second received frames are corrupted and the filter determining that the second received frame should be recovered.

Abstract: Provided are devices, systems and methods for rate matching and de-rate matching on digital signal processors. In one embodiment, a device for rate matching and de-rate matching, includes an interface for receiving a plurality of blocks of data and digital signal processor configured to pre-compute permutation parameters common to the plurality of blocks, wherein the plurality of blocks are subject to a set of given puncturing parameters and receive a set of pre-computed puncturing thresholds. For one or more blocks in the plurality of blocks, the DSP computes a block signature from the pre-computed puncturing thresholds; matches the block signature to one of a set of pre-computed zone signatures, derives a zone index corresponding to the one pre-computed zone signature, and applies pre-computed permutation and puncturing transformations corresponding to the zone index to the block.

Abstract: The present invention provides a low-complexity and multi-mode Low-density Parity-check (LDPC) codec, in which the decoding operations are divided into small tasks and a unified hardware is implemented so that the hardware resources can be reused in different modes. In addition, memory access is achieved via routing networks with fixed interconnections and memory address generators, the complexity of the hardware implementation is reduced accordingly. Further, the present invention provides an early termination function with which the iterative operations can be terminated early when a threshold is reached so that the power consumption can be thus reduced. The hardware resources for early termination shares a part of hardware resources with an encoder according to the present invention so that the complexity of the hardware implementation can also be reduced.

Abstract: A DRAM memory device includes several banks of memory cells each of which are divided into first and second sets of memory cells. The memory cells in the first set can be refreshed at a relatively slow rate to reduce the power consumed by the DRAM device. Error checking and correcting circuitry in the DRAM device corrects any data retention errors in the first set of memory cells caused by the relatively slow refresh rate. The memory cells in the second set are refreshed at a normal rate, which is fast enough that data retention errors do not occur. A mode register in the DRAM device may be programmed to select the size of the second set of memory cells.

Abstract: An iterative decoder dynamically controls the number of local iterations of error-correction decoding performed for each global iteration of channel detection. In so doing, the iterative decoder (i) limits the number of local iterations that are performed after error-correction decoding has likely encountered a trapping set and (ii) permits decoding to continue when error-correction decoding is on the path to converging on a valid codeword. To predict whether error-correction decoding is on the path to encountering a trapping set or converging on a valid codeword, a model is generated based on observed numbers of unsatisfied check nodes for a specified number of local iterations. For local iterations following the specified number of local iterations, the observed numbers of unsatisfied check nodes are then compared to the model to determine whether to continue or terminate local iterations of error-correction decoding.

Abstract: According to exemplary embodiments, a system, method, and computer program product are provided for BER-based wear leveling in a SSD. A block-level BER value for a block in the SSD is determined. An adjusted PE cycle count for the block is incremented or decremented based on the block-level BER value. Wear leveling is then performed in the SSD based on the adjusted PE cycle count.

Abstract: A method of setting a number of iteration counts of iterative decoding, and an apparatus and method of iterative decoding. The iterative decoder including a signal-to-noise ratio (SNR) estimation unit that estimates an SNR of a received signal, an iterative decoding count setting unit that sets a minimum number of iteration counts for the received signal based on the estimated SNR, and a decoding unit that iteratively decodes the received signal using tentative decoding and error check, and selectively performs the error check based on the minimum number of iteration counts.

Abstract: A method and apparatus are described including receiving channel condition feedback from a device over a wireless channel, determining response to the channel condition feedback if a forward error correction coding rate is sufficient for the device to recover lost data, adjusting the forward error correction coding rate responsive to the second determining act and generating forward error correction packets using the adjusted forward error correction coding rate from source data.

Abstract: One embodiment provides a method for time protocol latency correction based on forward error correction (FEC) status. The method includes determining, by a network node element, if a forward error correction (FEC) decoding mode is enabled or disabled for a packet received from a link partner in communication with the network node element. The method also includes determining, by the network node element, a first time correction factor if an FEC decoding mode is enabled, the first time correction factor includes a time delay associated with the enabled FEC decoding mode and the first time correction factor is applied to a time stamp associated with the packet. The method also includes determining, by the network node element, a second time correction factor if an FEC decoding mode is disabled, the second time correction factor is applied to the time stamp associated with the packet.

Abstract: The present inventions are related to systems and methods for irregular decoding of regular codes in an LDPC decoder, and in particular to allocating decoding resources based in part on data quality.

Abstract: An amount of time and an error rate function are received, where the error rate function defines a relationship between a number of iterations associated with iterative decoding and an error rate. A testing error rate is determined based at least in part on the amount of time. The number of iterations which corresponds to the testing error rate in the error rate function is selected to be a testing number of iterations; the testing error rate and the testing number of iterations are associated with testing storage media using iterative decoding.

Abstract: An adaptive controller for a configurable audio coding system comprising a fuzzy logic controller modified to use reinforcement learning to create an intelligent control system. With no knowledge of the external system into which it is placed the audio coding system, under the control of the adaptive controller, is capable of adapting its coding configuration to achieve user set performance goals.

Abstract: Subject matter disclosed herein relates to determining that a portion of a memory is at least partially non-functional, replacing the portion of at least partially non-functional memory; and adjusting an error detection and/or correction process responsive to determining that the portion of the memory is at least partially non-functional and/or replacing the portion of at least partially non-functional memory.

Abstract: Systems, methods and articles of manufacture for retransmission of data in streaming protocols are described herein. Embodiments enable efficient retransmission of dropped packet data in guaranteed delivery or request-response data transfer protocols such as TCP. In particular, embodiments provide efficient retransmission of dropped packet data based on the short and/or long term historical reliability of the underlying client connection. An embodiment includes maintaining, for one or more clients in a client-server architecture, data representing connection characteristics for one or more client-server connections. Based on collected short-term and long-term client connection characteristics, an efficient data packet retransmission scheme is determined to optimize use of the connection for retransmitting dropped packet data.

Abstract: Provided are systems and methods for rate matching and de-rate matching on digital signal processors. For example, there is a system for rate matching and de-rate matching, where the system includes a memory configured to contain a plurality of blocks of data, and a digital signal processor configured to pre-compute permutation parameters common to the plurality of blocks, wherein the plurality of blocks are subject to a set of given puncturing parameters. The digital signal processor is configured to process each block in the plurality of blocks by computing a block signature from pre-computed puncturing thresholds, matching the block signature to one of a set of pre-computed zone signatures, deriving a zone index corresponding to the one matched pre-computed zone signature, and applying pre-computed permutation and puncturing transformations corresponding to the zone index to the block.

Abstract: An apparatus for providing a data integrity field implementation in a data processing system includes a controller operative to interface between a host device and a destination device in the data processing system for transferring at least one data block therebetween. The data processing system further includes an error detection module associated with the controller. The error detection module is operative to determine a probability of an error occurrence based at least in part on a measured current error rate for the data processing system. The controller is operative to implement an error correction methodology which is selectively adaptable as a function of the probability of an error occurrence.

Abstract: A packet data transmitting method and mobile communication system using the same enables transmission of common ACK/NACK information from each sector of a base station to a user entity in softer handover. The method includes receiving via at least one of the plurality of sectors a data packet from the mobile terminal, the data packet being correspondingly received for each of the at least one of the plurality of sectors; combining the correspondingly received data packets, to obtain a signal having a highest signal-to-noise ratio; decoding the value obtained by the combining; determining a transmission status of the data packet according to the decoding; and transmitting to the mobile terminal a common ACK/NACK signal including one of a common ACK signal and a common NACK signal according to the determining, the common ACK/NACK signal being transmitted via each of the at least one sector.

Abstract: A controller of a storage control apparatus creates a fixed value, which is one or higher values conforming to a prescribed data pattern, with respect to first data, which is smaller than the size of a storage area of a storage device, creates a guarantee code related to a data area comprising the first data and the fixed value, and writes the data group comprising the data area and the guarantee code to the storage area. The controller reads a data group from the storage area, and determines whether or not more errors than the number of errors correctable by the guarantee code are included in this data group. In a case where the result of this determination is affirmative, the controller determines whether or not an error exists in the fixed value inside the data group.

Abstract: An adaptive controller for a configurable audio coding system including a fuzzy logic controller modified to use reinforcement learning to create an intelligent control system. With no knowledge of the external system into which it is placed the audio coding system, under the control of the adaptive controller, is capable of adapting its coding configuration to achieve user set performance goals.

Abstract: Adaptive error correction for non-volatile memories is disclosed that dynamically adjusts sense amplifier read detection windows. Memory control circuitry uses error correction code (ECC) routines to detect bit errors that are non-correctable using these ECC routines. The memory control circuitry then dynamically adjusts sense amplifier read detection windows to allow for correct data to be determined. Corrected data can then be output to external circuitry. The corrected data can also be stored for later access when subsequent read operations attempt to access address locations that previously suffered bit failures. The adaptive error correction can also be used with respect to memories that are not non-volatile memories.

Abstract: Detecting, avoiding and/or correcting problematic puncturing patterns in parity bit streams used when implementing punctured Turbo codes is achieved without having to avoid desirable code rates. This enables identification/avoidance of regions of relatively poor Turbo code performance. Forward error correction comprising Turbo coding and puncturing achieves a smooth functional relationship between any measure of performance and the effective coding rate resulting from combining the lower rate code generated by the Turbo encoder with puncturing of the parity bits. In one embodiment, methods to correct/avoid degradations due to Turbo coding are implemented by puncturing interactions when two or more stages of rate matching are employed.

Abstract: A system including an input configured to receive data and an encoder module configured to perform an encoding operation on the data using an error correcting code. The data comprises one or more bits inserted at predetermined locations in the data. A number of the one or more bits inserted in the data corresponds to a number of inner-code parity bits to be inserted at the predetermined locations subsequent to the encoding operation being performed on the data. The encoder module is configured to use, subsequent to the encoding operation being performed on the data, an inner code to generate the inner-code parity bits based on the data, and at the predetermined locations in the data, replace the one or more bits inserted in the data with the inner-code parity bits generated based on use of the inner code.

Abstract: An error correction data processing apparatus includes a noise predictive calibration circuit operable to calibrate a first set of filter coefficients based on a first data set and a second set of filter coefficients based on a second data set, and includes a first noise predictive detector operable to receive the first set of filter coefficients. The apparatus further includes a decoder operable to perform a first global iteration with the first noise predictive detector and determine a violation check count value, and a second noise predictive detector operable to receive the second set of filter coefficients if the violation check count value is less than a predetermined value or receive the first set of filter coefficients if the violation check count value is greater than the predetermined value.

Abstract: It is decided whether to adjust data associated with a decoder. In the event it is decided to adjust the data associated with the decoder, the data is adjusted to obtain adjusted data and decoding is performed on the adjusted data. In the event it is decided to not adjust the data associated with the decoder, decoding is performed on the data associated with the decoder.

Abstract: An automatic retransmission request control system in an OFDM-MIMO communication system includes a retransmission mode selection part which selects a retransmission mode from among (a) a mode in which to transmit the data, which are to be retransmitted, via the same antenna as in the previous transmission, while transmitting, at the same time, new data by use of an antenna via which no data retransmission is requested; (b) a mode in which to transmit the data, which are to be retransmitted, via an antenna via which no retransmission is requested, while transmitting new data via another antenna at the same time; (c) a mode in which to use STBC to retransmit the data via an antenna via which no retransmission is requested; and (d) a mode in which to use STBC to retransmit the data via all the available antennas.

Abstract: A transmitting circuit transmits data to which an error detection code is attached to a receiving circuit via a transmission path. When detecting the error of the data received via the transmission path, a receiving circuit transmits a retransmit request for the data in which the error is detected to the transmitting circuit. The receiving circuit enters a termination unit adjustment period using the error detection of the received data as a trigger and updates the resistance values of a receiving side termination unit installed at the termination of the transmission path to an appropriate value within the termination unit adjustment period.

Abstract: An apparatus generally having a plurality of first circuits and a second circuit is disclosed. The first circuits may be configured to (i) generate a plurality of intermediate bits by dividing a plurality data bits by a plurality of minimal polynomials of an encoding along a first path and (ii) generate a plurality of parity bits by multiplying the intermediate bits by the minimal polynomials along a second path. A number of the parity bits may be variable based on a configuration signal. The second circuit may be configured to (i) delay the data bits and (ii) generate a plurality of code bits by appending the parity bits to a last of the data bits.

Abstract: Systems and methods for error recovery are presented. Data is decoded with an iterative decoding scheme having a first set of parameters. In response to a determination that the iterative decoding scheme has failed, the data is re-read. While the data is being re-read, the iterative decoding scheme is reconfigured with a second set of parameters, and the data is decoded with the reconfigured iterative decoding scheme. In response to determination that the reconfigured iterative decoding scheme has failed, an error type associated with the data is determined. An error recovery scheme is selected from a plurality of error recovery schemes for the data based on the determined error type.

Abstract: Systems and methods are provided for selecting precisions during iterative decoding with a low-density parity check (LDPC) decoder in order to maximize LDPC code's performance in the error floor region. The selection of the precision of the messages may be done in such a way as to avoid catastrophic errors and to minimize the number of near-codeword errors during the decoding process. Another system and method to avoid catastrophic errors in the layered (serial) LDPC decoder is provided. Lastly, a system and method that select precisions and provide circuitry that optimizes the exchange of information between a soft-input, soft-output (SISO) channel detector and an error correction code (ECC) decoder for channels with memory is provided.

Abstract: A method for data storage includes storing data, which is encoded with an Error Correction Code (ECC), in a group of analog memory cells by writing respective first storage values to the memory cells in the group. After storing the data, respective second storage values are read from the memory cells in the group, and the read second storage values are processed so as to decode the ECC. Responsively to a failure in decoding the ECC, one or more of the second storage values that potentially caused the failure are identified as suspect storage values. Respective third storage values are re-read from a subset of the memory cells that includes the memory cells holding the suspect storage values. The ECC is re-decoded using the third storage values so as to reconstruct the stored data.

Abstract: A system for, and method of, assigning code blocks to constituent decoding units in a turbo decoding system having parallel decoding units. In one embodiment, the method includes: (1) representing the turbo decoding system as a resource diagram rectangle, (2) representing the code blocks as code block rectangles, (3) mapping the code block rectangles into the resource diagram rectangle and (4) assigning the code blocks to the constituent decoding units based on the mapping.

Abstract: A digital broadcasting system and method of processing data are disclosed. Herein, a method of processing data in a transmitting system includes creating a data group including a plurality of mobile service data packets, re-adjusting a relative position of at least one main service data packet of a main service data section, the main service data section including a plurality of main service data packets, and multiplexing the mobile service data of the data group and the main service data of the main service data section in burst units. Herein, a position of an audio data packet among the main service data packets of the main service data section may be re-adjusted. Also, a position of an audio data packet included in the main service data section may be re-adjusted based upon a multiplexing position of the main service data section.

Abstract: Joint encoding and decoding methods for improving the error rate performance are described. In one aspect, the systems and methods determine values and positions of L desired symbols. In encoding unit receives data symbols for encoding. The encoding unit calculates, responsive to receiving the data symbols, values and positions of H help symbols. The encoding unit inserts the help symbols into the data symbols at respective help symbols positions, thereby generating new data symbols. Encoding unit encodes the new data symbols to produce a codeword C? that contains the L desired symbols. The codeword C? is communicated to a decoder that is instructed to explore some or all L desired symbols in C?.

Abstract: A network communication device includes a host interface, which is coupled to communicate with a host processor, having a host memory, so as to receive a work request to execute a transaction in which a plurality of data blocks are to be transferred over a packet network. Processing circuitry is configured to process multiple data packets so as to execute the transaction, each data packet in the transaction containing a portion of the data blocks, and the multiple data packets including at least first and last packets, which respectively contain the first and last data blocks of the transaction. The processing circuitry is configured to compute a transaction signature over the data blocks while processing the data packets so that at least the first data block passes out of the network communication device through one of the interfaces before computation of the transaction signature is completed.

Abstract: Systems and methods for adaptively operating a storage device are provided. A level of integrity of storing data in the storage device is determined. A coding scheme is selected based on the determined level of integrity of the storage device. An operation is performed on the storage device using the selected coding scheme.

Abstract: Systems, methods, and apparatus are provided for improving the iterative decoding performance of a decoder, for example, as used in a wireless communications receiver or in a data retrieval unit. A decoding technique may receive and process a set of channel samples using an iterative decoder. If the iterative decoder output indicates a decoding failure, noise samples may be combined with the received channel samples to create biased channel samples. Noise samples may be generated using a pseudo-random noise generator and/or by using signals already present in the communications receiver or data retrieval unit. The biased channel samples may be provided to the iterative decoder and the iterative decoder may re-run using the biased channel samples.