Abstract: A method and system of receiving data with enhanced error correction is disclosed. One or more reliability bits associated with each received data bit are generated, for example, by a soft-decision slicer. Subsequently, one or more errors of the data bits may be corrected according to the associated reliability bit(s).

Abstract: Embodiments of the present invention provide a system that identifies an even delimiter in a forward error correction (FEC)-coded Ethernet frame. The system receives an FEC-coded Ethernet frame that includes the even delimiter, which is a predetermined sequence that separates a conventional Ethernet frame and FEC parity bits in the FEC-coded Ethernet frame. Next, the system scans a bit stream of the FEC-coded Ethernet frame. Then, the system determines a first Hamming distance between a first consecutive set of frame bits in the bit stream and the even delimiter. The system also determines a second Hamming distance between a second consecutive set of frame bits in the bit stream and the even delimiter. Both the first and second Hamming distances are shorter than a predefined value. The system subsequently selects one of the first and second sets of frame bits having the shorter Hamming distance as the even delimiter.

Abstract: Some embodiments of the present invention provide a system that can be reconfigured to provide error detection and correction after a failure of a memory component in a memory system. During operation, the system accesses a block of data from the memory system, wherein each block of data in the memory system includes an array of bits logically organized into R rows and C columns, including two checkbit columns containing checkbits, and C-2 data-bit columns containing data bits, wherein each column is stored in a different memory component, and wherein the checkbits are generated from the data bits to provide block-level detection and correction for a failed memory component. Next, upon examining the block of data, the system determines that a specific memory component in the memory system has failed.

Abstract: The invention relates to a method for secure data transmission in connections between two functional modules of an electronic unit. A first module of a message of k bits in a word code of n bits is injection coded with a constant Hamming weight of w. The word of code is transmitted to a second module. An error signal is generated when the Hamming weight of the word of code of n bits, received by the second module, is different from w. In the absence of error, the code word is decoded, where k, w and n are whole numbers. The invention further relates to a corresponding electronic circuit.

Abstract: The present invention provides a method for enhancing reliability of information transmission, comprising the steps of: (a) establishing a matrix based on the length of bits of valid information in frame time slots; and creating a new matrix by presetting Error Correction Coding (ECC) for rows and columns of said matrix; (b) adopting the 1st Interleaving method to re-allocate bits which have been processed twice by using said ECC in said new matrix, to both ends of said frame time slots; and (c) adopting the 2nd Interleaving method to re-allocate the remaining bits in said new matrix to the middle of said frame time slots. After processed like this, the anti-interfering ability of the bits at both ends of TDMA frame time slot can be significantly enhanced, and the bit-error rate is decreased most, and all redundancy bits of Hamming codes can be arrayed at both ends of TDMA frame time slot.

Abstract: A flash-memory system is organized into a plurality of blocks and a plurality of pages in each block, each page having 2N data locations and K spare locations. At least one page in the memory has 2M?1 user data sectors and each sector has 2N?M+L locations therein. Error-correction code (ECC) data related to the user data is calculated and stored in at least the 2M user data locations unused by the 2M?1 user data sectors. Because L is at least 1 but less than 2N?M (N>M), at least a portion of one user data sector is stored in the spare memory locations. Additional locations in each page are available to allow for the ECC data to have additional redundancy bits added per sector, thereby making the flash memory system more robust and reliable.

Abstract: Methods of data handling include receiving data having a previously-generated error correction code and generating one or more error correction codes for the data, with each error correction code corresponding to the data having one or more particular bits of the data in differing data states. Such methods further include comparing the generated one or more error correction codes to the previously-generated error correction code, and if a particular one of the generated one or more error correction codes matches the previously-generated error correction code, transmitting the data having its one or more particular bits in the data states corresponding to that particular one of the generated one or more error correction codes. Methods of data handling may further include prioritizing the error correction in response to at least locations of known bad or questionable bits of the data.

Abstract: Unrecoverable electronic correction code (ECC) errors in memory storage devices are usually preceded by recoverable ECC errors. A memory storage device controller is provided notice of the recoverable errors and associated information. The memory storage device controller can cause the data having the recoverable information to be rewritten on the memory storage device. Rewriting the data on the memory storage device (often in a different location) normally reduces the probability of encountering data with unrecoverable data errors.

Abstract: A method of channel coding a digital communication system and a device using the same is provided. The method includes quantizing analog data to digital data, the digital data corresponding to a predetermined number of digital codes; allocating channel codes to the digital codes, as a Hamming distance between a pair of channel codes corresponding to any pair of the digital codes is proportional to a difference between analog values of the pair of the digital codes; and channel coding the digital data by using the channel codes which are allocated to the digital codes to generate channel coded digital data. Accordingly, digital data, such as multimedia digital data without source coding and the like, of which information significance is different may be effectively transmitted and received.

Abstract: The invention relates to a method of probabilistic symmetric encryption of a plaintext message element with the aid of a secret key that can be represented in the form of a matrix. It comprises an operation of encrypting the plaintext message element, with the aid of the matrix parametrized by a random vector, so as to obtain an encrypted message element coupled to the random vector. Furthermore, there is envisaged a step of encoding the plaintext message element as a code word with the aid of an error correcting code having a given correction capacity and a step of adding a noise vector. The error correcting code and the noise vector are adapted so that the Hamming weight of the noise vector is less than or equal to the correction capacity of the correcting code.

Abstract: A method and apparatus providing improved set membership determination and group membership identification of candidate data elements using a single Bloom filter programmed to provide a plurality of non-zero f-bit binary vectors, where each of the f-bit binary vectors is associated with a respective group. The Bloom filter is programmed using one or more (but not all) of a plurality of hash filter sets.

Abstract: An improved mapping policy, signal mapper, transmitter, receiver, and communication system are introduced. The improved signal mapping policy alternates between standard and inverted bit mapping functions at selected phase states to reduce the error coefficient of MSK and other types of CPFSK signals. The proposed policy can more generally be applied to other types of signals with memory as well. Simulations show that the mapping policy can significantly improve performance particularly at lower to moderate SNR values.

Abstract: Control symbols taking the form {k1-k2-k2-k1} are inserted in a serial stream including m bit data words. k1 and k2 are each predefined m bit control words differing from the m bit data words. The Hamming distance between k1 and k2 is at least 2. Such control symbols may be robustly detected in the presence of a one bit error in the symbol, or a data word immediately preceding or following the symbol. The m bit words may be 8B/10B encoded data, or defined control words. The control symbols may be used for data delineation, stream synchronizaiton, transmitter/receiver synchronization or for other control signalling.

Abstract: Memory systems and devices are provided. One memory system includes a controller configured to be coupled to a plurality of computing devices, a plurality of Multi-Level Cell (MLC) devices coupled to the controller, and a Single-Level Cell (SLC) device coupled to the controller and the plurality of MLC devices. The MLC devices are configured to split the storage of data across the plurality of MLC devices and the SLC device is configured to function as a parity device for the data. A memory device includes a controller, a plurality of MLC FLASH devices, and a SLC FLASH device. The MLC FLASH devices are configured to split the storage of data across the plurality of MLC FLASH devices and the SLC FLASH device is configured to function as a parity device for the data. Also provided are computing devices including the above memory device.

Abstract: Some embodiments include apparatus and methods to prevent at least one of misidentifying and ignoring multiple-bit errors if the multiple-bit errors include a plurality of erroneous data bits that belong to only one specific group of a plurality of groups of data bits and if none of the other groups of the plurality of groups have errors.

Abstract: A method for reducing data loss includes a first computing step for computing an intermediate result for each redundancy information entity of a redundancy set by processing respectively associated data information entities of a given data set on at least two main diagonals of a parity check matrix representing an error correction coding scheme. The method further includes a second computing step for computing the information content of the respective redundancy information entity dependent on the respective intermediate result.

Abstract: Method and a receiver in a communication system for receiving a transport block. The transport block comprises code blocks, each of the code blocks includes an error detection code and an error correction code. Reliability metrics are determined using an input generated during processing of the code blocks after the transport block is received. Each of the reliability metrics corresponds to each of the code blocks. A code block reorderer reorders the code blocks in an order based on the reliability metrics and a selection criterion. A decoder decodes each of the code blocks using the error correction code in the order. A verifier verifies each of the decoded code blocks using the error detection code.

Abstract: Error tolerance is increased for a storage system having a plurality of arrays by making local redundancy in a selected array globally available throughout the storage system. To achieve the increased error tolerance, a donor array is selected from the plurality of arrays when the difference between a minimum distance of the donor array and a minimum distance of a recipient array is greater or equal to 2. A donor storage unit is selected in the donor array and recipient information is then rebuilt from the recipient array on the selected storage unit. The selected storage unit is indicated to the donor array as having been donated before the lost information is rebuilt on the selected storage unit. Preferably, the minimum Hamming distance of the recipient array is d?2 before the donor array is selected from the plurality of arrays.

Abstract: A method and apparatus for decoding data is provided herein to show how to turbo decode LDPC codes that contain a partial dual diagonal parity-check portion, and how to avoid memory access contentions in such a turbo decoder. During operation, a decoder will receive a signal vector corresponding to information bits and parity bits and separate the received signal vector into two groups, a first group comprising signals corresponding to the information bits and one or more parity bits, a second group comprising a remainder of the parity bits. The first group of received signals is passed to a first decoder and the second group of received signals is passed to a second decoder. The decoders are separated by an interleaver and a deinterleaver. Iterative decoding takes place by passing messages between the decoders, through the interleaver and the deinterleaver, and producing an estimate of the information bits from the output of the first decoder.

Abstract: Apparatus and methods for operating a flash device characterized by use of Lee distance based codes in a flash device so as to increase the number of errors that can be corrected for a given number of redundancy cells, compared with Hamming distance based codes.

Abstract: In a method of reading data from a non-volatile memory device, read data is generated based on a word line voltage. The read data includes data read from a plurality of sectors included in the non-volatile memory device. Bad sector data is transferred data based on read data and bad sector information. The bad sector data corresponds to data read from at least one bad sector included in the plurality of sectors. The bad sector information is updated by checking error bits of the bad sector data. The word line voltage is generated based on the updated bad sector information.

Abstract: A system and method for efficient uncorrectable error detection in flash memory is described. A microcontroller including a non-volatile flash memory utilizes an Error Correction Code (ECC) having a certain error detection and correction bit strength. The user data is first processed by a hash function and hash data is stored with the user data. Then, the user data and hash data are processed by the ECC system. In detection, the hash ensures that a relatively low bit-strength ECC system did not incorrectly manipulate the user data. Such a hash integrity check provides an efficient, robust detection of incorrectly corrected user data resulting from errors beyond the correction but strength of the ECC system utilized.

Abstract: A method of de-duplicating duplicate data in a data storage system that includes identifying a plurality of portions of data, comparing each portion of the data to identify duplicate data and identifying a link associated with each duplicate data, determining whether a Hamming link-separation-distance between the identified link and all other existing links is greater than twice the Hamming radius of an error correction code in the data storage system, and then replacing the duplicate data with the identified link.

Abstract: A memory device, such an MRAM device, includes self-healing reference bits (104) associated with a set of array bits (102). The memory performs an error detection step (e.g., using an error-correction coding (ECC) algorithm, to detect the presence of a set of errors within the data bits. One of the reference bits (104) is toggled to a different state if an error count is greater than a predetermined threshold. If the set of errors remains unchanged when subsequently read, the reference bit (104) is toggled back to its original state.

Abstract: A telecommunication system and related methods. Implementations may include implementations of a method of encoding data for transmission, including forming a frame by encoding a message block using a short-block low density parity check (LDPC) code and an encoder to form a short encoded block, modulating the short encoded block using a modulation format and a modulator to form a modulated short encoded block, including the modulated short encoded block in a data payload of the frame, and transmitting the frame into a telecommunication channel with a transmitter. The frame may be one of a plurality of frames and each modulated short encoded block in each of the plurality of frames may have a constant number of symbols. The frame may include a modulation/code pair (ModCod) including information relating to the modulation format and the short-block LDPC code used for encoding and modulation.

Abstract: The present invention relates to coding method and coding device that allow Rate-Compatible LDPC (low-density parity-check) codes to have favorable BER performance both with a low code rate and with a high code rate. In coding of LDPC codes that have plural code rates and whose all parity check matrices are composed of plural cyclic matrices, a coder 121 performs the coding in such a way that 1<w0 and w1<w0 are satisfied when the maximum column weight of the cyclic matrices in the check matrix of a certain code whose code rate is not the minimum value among the LDPC codes is defined as w0 and the maximum column weight of the cyclic matrices in the check matrix of a code having a code rate lower than that of the certain code is defined as w1.

Abstract: A first device receives first data that includes a plurality of input vectors, which includes a primary input vector and a set of secondary input vectors and detects uncorrectable errors in the first data based on a quality metric indication. Based on detecting the uncorrectable errors in the first data, the first device substitutes a predetermined codeword for the primary input vector encoded using a non-perfect code, and substitutes a predetermined input vector for the primary input vector. The first device modulates a set of encoded secondary input vectors using the predetermined input vector to generate a modulated set of encoded secondary input vectors and transmits as second data the predetermined codeword and the modulated set of encoded secondary input vectors to a target device, wherein the substituting step creates a first number of errors that is detected by the target device as uncorrectable errors in the transmitted second data.

Abstract: A method for field error checking begins by decoding a predetermined pattern of a field of a frame to produce a decoded pattern. The method continues by determining, for the decoded pattern, a path metric distance of a predetermined state of a plurality of states of the decoding. The method continues by comparing the path metric distance with an excepted path metric distance for the predetermined state. The method continues by indicating a field error when the path metric distance compares unfavorably with the excepted path metric distance.

Abstract: Systems, methods and computer program products for providing a nested two-bit symbol bus error correcting code. Methods include constructing a nested error correcting code (ECC) scheme. The method includes receiving a Hamming distance n code. A symbol correcting code H-matrix is created by iteratively adding rows of H-matrix bits on a symbol column basis such that the symbol correcting code H-matrix describes a symbol correcting code, and the Hamming distance n code is preserved as a subset of the symbol correcting code H-matrix.

Abstract: Systems, method, and computer program products for utilizing a spare lane for additional checkbits. Systems include computer, storage or communications systems with bitlanes for transferring error correcting code (ECC) words in packets over a bus in multiple cycles, a spare bitlane available to the bus, a spared mode and an initial mode. The spared mode is executed when the spare bitlane has been deployed as a replacement bitlane for carrying data for one of the other bitlanes. The initial mode is executed when the spare bitlane has not been deployed as a replacement bitlane. The initial mode includes utilizing the spare bitlane for carrying one or more additional ECC checkbits. The initial mode provides at least one of a more robust error detecting function for the bus than the spared mode and a more robust error correcting function for the bus than the spared mode.

Abstract: Bit errors in packets of data that are communicated in a network such as a wireless network can be corrected by processes that do not require any overhead in the data such as conventional error-detection codes or redundant information such as conventional error-correction codes. A validation-set process compares corrupted data against values in a set of known valid values and selects one of the known valid values to replace the corrupted data. A consistency-check process uses data correlation characteristics of two or more parameters to determine if values obtained from a packet are consistent with one another. If not, values are changed to make them consistent.

Abstract: A system (e.g., Fibre Channel Error Detecting Code (FC-EDC)) that maps the “standard” Hamming codes onto the bits of a 33-bit control block is provided. The system employs a “rotation” of the check positions in a two-dimensional parity-check matrix for the FC-EDC. The specification discloses a computer-implemented program to test further modifications and permutations of the “standard” distance-4 parity-check matrix to yield an FC-EDC with enhanced error-detecting properties, designed to detect the most likely errors in the known physical environment. By using a parity-check matrix with the “rotation” property, certain error-detecting properties of the parity-check matrix are ensured, and the computation time for searching for a matrix with enhanced error-detecting properties becomes much shorter.

Abstract: An apparatus and method for detecting and correcting errors in control characters of a multimedia interface. The apparatus comprises a hamming distance filter for detecting and correcting bits errors in a first subset of bits of an input control character including M bits; a glitch filter for detecting and correcting a second subset of bits being a complementary subset of bits of the control character; and an character alignment unit for detecting and correcting misalignment errors between the corrected first subset of bits and the corrected second subset of bits.

Abstract: A block code decoding method and device thereof are provided. The procedure of the bounded distance decoding is simplified and the number of correlation calculating is reduced via a set of pre-established XOR masks. The decoding method includes: picking up the source code part of the received message; executing a XOR calculating for the source code part with the XOR masks, and encoding the results thereof to produce a set of compared codes; executing a correlation calculating for the set of compared codes and the received message; and determining a compared code having the maximum correlation result as the decision.

Abstract: An automatic data recovery circuit includes a register, an error detection unit and a data recovery unit. The register stores a register data including an input data and a remainder data generated by a cyclic redundancy check calculation on the input data using a predefined generation polynomial. The error detection unit performs a modular calculation on the register data stored in the register using the predefined generation polynomial to generate an error detection signal indicating whether an error is detected in the register data stored in the register. The data recovery unit recovers the input data when an error is detected in the input data based on the error detection signal and a comparison data generated by comparing the input data stored in the register with a reference voltage using a capacitor.

Abstract: A method of generating a code that minimizes error propagation by selecting integers m, n, mrl, and a range of fractions od, where m represents the number of bits in an unencoded sequence, where n represents the number of bits in an encoded sequence, where mrl represents the maximum run length of an encoded sequence, and where od represents a range of ones densities of an encoded sequence. Next, generating an encoding map M that maps each unencoded sequence to an n-bit encoded sequence that satisfies od and mrl. Next, generating a decoding map N that maps each n-bit sequence to an m-bit sequence. Next, determining an error-propagation score for M and N. Then, returning to the step of generating M if a user requires a lower error-propagation score.

Abstract: A method of stabilizing an identification series of bits by iteratively reading the identification series and logical OR'ing the identification series with a mask string after each read of the identification series. This produces a mask string having a first value in all positions of the mask string where bits in the identification series have never changed value during all of the readings of the identification series, representing stable bits, and a second value in all positions of the mask string where bits in the identification series have changed value during at least one of the readings of the identification series, representing unstable bits. The number of the unstable bits in the mask string having the second value is counted, and a method failure code is selectively reported when the number of unstable bits exceeds a maximum allowable number of unstable bits. An identification string is produced from the stable bits, and an identification code is calculated from the identification string.

Abstract: A transmission apparatus includes: a CRC encoding processing unit configured to include a plurality of generating polynomials for an CRC encoding processing with each of a plurality of data of which the code lengths differ as a target, and employ the optimal generating polynomial out of the plurality of generating polynomials to perform the CRC encoding processing; and a transmission unit configured to transmit data obtained by the CRC encoding processing unit performing the CRC encoding processing.

Abstract: A memory device for an error-correcting block code is provided, whereby each code word of the block code can have data bits and parity bits. The device also includes a memory for storing the data bits and the parity bits of each code word, and includes an error detection circuit, which is formed to detect an error of the data bits in a code word by evaluating exactly one subset of the stored parity bits of the code word. The subset being smaller than the total number of parity bits of the code word.

Abstract: A system, method and computer program product is provided for mitigating the effects of burst noise on packets transmitted in a communications system. A transmitting device applies an outer code, which may include, for example, a block code, an exclusive OR (XOR) code, or a repetition code, to one or more packets prior to adaptation of the packets for transmission over the physical (PHY) layer of the communications system, wherein the PHY layer adaptation may include FEC encoding of individual packets. The outer coded packets are then separately transmitted over a channel of the communications system. A receiving device receives the outer coded packets, performs PHY level demodulation and optional FEC decoding of the packets, and then applies outer code decoding to the outer coded packets in order to restore packets that were erased during transmission due to burst noise or other impairments on the channel.

Abstract: According to an embodiment of the present invention provides the signal processing system. In the signal processing device that estimates information data from a reception signal by performing iterative processing between a demodulator that demodulates data of n(>m) bits obtained by modulating data of m bits into m bits and an ECC decoder and carrying out maximum a posteriori probability decoding, the device has a module that calculates an a posteriori value after demodulation by performing calculation of modulation data having a pattern estimated to have a high probability alone as modulation data to be decoded from all patterns of the modulation data to be decoded when effecting calculation of the a posteriori value after demodulation based on an a priori value fed back from the ECC decoder at the time of effecting modulation for a second or subsequent time.

Abstract: An apparatus and method for non-exclusive multiplexing of at least one active control channel comprising preparing the at least one active control channel for transmission in a next frame using a transmitter data processor; assessing channel robustness of the at least one active control channel based on a channel robustness threshold; and if the channel robustness threshold is not met, performing constellation control or power control on the at least one active control channel which is active prior to transmitting the at least one active control channel; or if the channel robustness threshold is met, transmitting the at least one active control channel using a transmitter.

Abstract: To derive a Hamming code to manage data errors a set of at least four parity bit positions is selected for parity bits which will protect a set of data bits (where each data bit has a data bit position in the data bit set). A syndrome is determined for each data bit position. This involves selecting a unique sub-set of at least three parity bit positions. The unique sub-set shares at least one parity bit position with at least one other unique sub-set of at least three parity bit positions. A parity bit value may then be calculated for each parity bit position based on the determined syndromes. The header of a packet may be provided with a word which defines the length of the packet and an error management code generated utilizing this word so that errors in the word may be detected and, possibly, corrected.

Abstract: An error correction apparatus, a method thereof, and a memory device including the apparatus are provided. The error correction apparatus may include: a determination unit configured to determine whether a number of errors in a read word being read and extracted from a multi-level cell (MLC) exists in an error correcting capability range; a read voltage control unit configured to either increase or decrease a read voltage applied to the MLC when the number of errors in the read word is outside the error correcting capability range; and a codeword determination unit configured to analyze a bit error based on the increase or decrease of the read voltage, and to select a codeword corresponding to the analyzed bit error based on a selected read error pattern. Through this, it may be possible to efficiently correct a read error that occurs when the data of the memory device is maintained for a long time.

Abstract: A system and method enable the fast decoding of a front end of data (e.g., a header) that is convolutionally encoded by treating the front end as a block code. The system and method receive the convolutionally encoded data; extract a finite sized block from the data; and decode the extracted block using a block error correction decoding method. A Viterbi decoder can then be used to decode the remainder of the encoded data based on the decoded block.

Abstract: A method of encoding multi-bit level data includes: determining a range of an error pattern generated according to a transmission symbol, encoding an M-bit level of a P-bit level corresponding to the transmission symbol based on the range of the error pattern, and excluding encoding of a P-M bit level of the P-bit level. The variable P is a natural number of a value at least two, and the variable M is a natural number less than P.

Abstract: The present disclosure is directed to a system and method of correcting video data errors. In a particular embodiment, the method includes receiving a stream of data packets at a re-generator of an Internet Protocol (IP) video transport stream. The stream of data packets includes a plurality of IP media packets and a plurality of forward error correction (FEC) packets. The method also includes determining an error profile of an error within the plurality of IP media packets. The method includes identifying one of the plurality of FEC packets, where the identified FEC packet is associated with an error correction code corresponding to the error profile. The method also includes selecting an inverse FEC function from a plurality of inverse FEC functions. The selected inverse FEC function corresponds to the identified FEC packet.

Abstract: Received communication signals may be decoded according to a combined, iterative inner code-outer code decoding technique. The inner code decoding is based on information produced by the outer code decoding.

Abstract: To derive a Hamming code to manage data errors a set of at least four parity bit positions is selected for parity bits which will protect a set of data bits (where each data bit has a data bit position in the data bit set). A syndrome is determined for each data bit position. This involves selecting a unique sub-set of at least three parity bit positions. The unique sub-set shares at least one parity bit position with at least one other unique sub-set of at least three parity bit positions. A parity bit value may then be calculated for each parity bit position based on the determined syndromes. The header of a packet may be provided with a word which defines the length of the packet and an error management code generated utilizing this word so that errors in the word may be detected and, possibly, corrected.

Abstract: A system and method for dynamical decoupling of a quantum system includes forming a graph including elements to account for decoupling sequence effects represented as nodes in the graph and soft pulses applied being represented as edges in the graph. Sequences which visit edges and nodes in the graph are provided. Binary strings corresponding to the nodes in a coordinate system are mapped using a fixed linear error correcting code. A decoupling method is provided based upon a matrix formed using the error correcting code to determine features of the soft pulses to decouple environmental effects from the quantum system.