Abstract: An error correcting device for correcting erroneous data included in data read out from a nonvolatile memory includes a determining unit that determines whether the data read out from the nonvolatile memory include an error beyond an error correcting capability of the error correcting device. When the determining unit has determined that an error beyond the error correcting capability exists, the error correcting device does not perform the correction of the error.

Abstract: Data move operations in a memory device are described that enable identification of data errors. Error detection circuitry in the memory device can be operated using parity data or ECC data stored in the memory. Results of the error detection can be accessed by a memory controller for data repair operations by the controller.

Abstract: The present application relates to a data bus system, its encoder/decoder and encoding/decoding method.

Abstract: Error tolerance is increased for a storage system having a plurality of arrays by making local redundancy in a selected array globally available throughout the storage system. To achieve the increased error tolerance, a donor array is selected from the plurality of arrays when the difference between a minimum distance of the donor array and a minimum distance of a recipient array is greater or equal to 2. A donor storage unit is selected in the donor array and recipient information is then rebuilt from the recipient array on the selected storage unit. The selected storage unit is indicated to the donor array as having been donated before the lost information is rebuilt on the selected storage unit. Preferably, the minimum Hamming distance of the recipient array is d?2 before the donor array is selected from the plurality of arrays.

Abstract: Systems and methods for error correction of data. In one embodiment of the invention, a plurality of error correction schemes are applied when encoding data and depending on the circumstances, one or more of those schemes is selected to decode the data. In one of these embodiments, the applied error correction schemes include the BCH algorithm and the Hamming algorithm.

Abstract: The present invention provides a semiconductor device which sufficiently ensures the security and prevents the decline of the yield even when the failure or the like causes a bit change in the data of the test mode control flag stored in the nonvolatile memory. The semiconductor device of the present invention includes: a nonvolatile memory which stores a test mode control code in a predetermined address; a generation unit which generates a fixed value indicating permission for or prohibition of a test mode; and a Hamming distance determination circuit which controls switching to the test mode depending on whether or not a Hamming distance between the control code and the fixed value is equal to or less than a predetermined number.

Abstract: This invention relates to a circuit technique for rapidly and efficiently correcting for read and write data errors in a digital semiconductor memory. More generally, this can also be in any type of digital memory or digital communication channel. As semiconductor memories get smaller and smaller, the memory cells are subject to higher rates of manufacturing defects and soft errors. Correction of manufacturing defects is achieved through extensive testing and use of redundant memory cells to replace defective memory cells. Soft errors are very difficult to detect and correct and only the simplest parity check codes have been implemented. The cost in terms of delay time and computational complexity are barriers to the implementation of ECC. This invention represents a device that introduces very little delay and requires minimal hardware complexity to implement.

Abstract: Semiconductor devices, a system including said semiconductor devices and methods thereof are provided. An example semiconductor device may receive data scheduled for transmission, scramble an order of bits within the received data, the scrambled order arranged in accordance with a given pseudo-random sequence. The received data may be balanced such that a difference between a first number of the bits within the received data equal to a first logic level and a second number of bits within the received data equal to a second logic level is below a threshold. The balanced and scrambled received data may then be transmitted. The example semiconductor device may perform the scrambling and balancing operations in any order. Likewise, on a receiving end, another semiconductor device may decode the original data by unscrambling and unbalancing the transmitted data. The unscrambling and unbalancing operations may be performed in an order based upon the order in which the transmitted data is scrambled and balanced.

Abstract: The error tolerance of an array of m storage units is increased by using a technique referred to as “dodging.” A plurality of k stripes are stored across the array of storage units in which each stripe has n+r elements that correspond to a symmetric code having a minimum Hamming distance d=r+1. Each respective element of a stripe is stored on a different storage unit. An element is selected when a difference between a minimum distance of the donor stripe and a minimum distance of a recipient stripe is greater or equal to 2. The selected element is also stored on a storage unit having no elements of the recipient stripe. A lost element of the recipient stripe is then rebuilt on the selected element.

Abstract: A method for calculating an extended hamming checksum and applying the extended hamming checksum to a data packet, the method comprising forming a packet extended hamming checksum mask, calculating a hamming code, calculating an extended hamming checksum using the packet extended hamming checksum mask and the hamming code, and inserting the extended hamming checksum into the data packet.

Abstract: A method and device for detecting and correcting errors in a data stream. For example, a method and device for detecting and correcting errors in a data stream including identifiers for a track address or identifiers for encoded words in a wireless transmission. The method and device employ a class of error correction codes to, for instance, encode track addresses on a surface of a data storage medium. The encoding modifies natural track addresses so that the difference between bit sequences in adjacent track addresses is constant while simultaneously enabling both error detection and error correction, thereby enabling more accurate head positioning in a data storage device, in one embodiment.

Abstract: A method of decoding possibly mutilated codewords (r) of a code (C) into information words (m?) including information symbols (m?1, m?2, . . . , m?k), the information words (m) being encoded into codewords (c) of the code (C). In order not to considerably deviate from the standard method and apparatus for decoding a standard Reed-Solomon code, a method of decoding is proposed including decoding the possibly mutilated codewords (r) into codewords (r?), reconstructing information symbols (m?1, m?2, . . . , m?k) from the codewords (r?), comparing the reconstruct information symbols (m?1, m?2, . . . , m?k) with information symbols (m1) known a priori before decoding, and verifying decoding errors based on the result of the comparison.

Abstract: Disclosed herein is a CRC generator polynomial select method for selecting a generator polynomial to be used in CRC coding processing and/or CRC processing of inspecting a CRC processing result, the CRC generator polynomial select method may include a first process of finding largest minimum Hamming distances Max.dmin; a second process of finding code lengths n for each of the largest minimum Hamming distances Max.dmin and determining a range expressed by relations nmin (r, Max.dmin)?n?nmax (r, Max.dmin); a third process of searching all generator polynomials G(x) for specific generator polynomials G(x); and a fourth process of selecting final generator polynomials G(x) each having a smallest term count w and a lowest code undetected-error probability Pud from the specific generator polynomials G(x).

Abstract: Systems, methods, and devices are disclosed, including a device that includes a plurality of data locations, a quantizing circuit coupled to the plurality of data locations, and an error detection module coupled to the quantizing circuit. In some embodiments, the error detection module includes an encoder configured to encode incoming data with redundant data derived from the incoming data and a decoder configured to detect errors in stored data based on the redundant data.

Abstract: A method and apparatus can detect errors within an incorrect media access control address and can prevent an Ethernet device from using the incorrect media access control address while it is fully operating. The method and apparatus can also correct some types of errors within the media access control address so that the Ethernet device may operate using a correct media access control address.

Abstract: A communications system includes an encoder that produces a plurality of redundant symbols. For a given key, an output symbol is generated from a combined set of symbols including the input symbols and the redundant symbols. The output symbols are generally independent of each other, and an effectively unbounded number of output symbols can be generated, if needed. Received output symbols can provide probabilistic information for error correction. A decoder calculates check symbols from the output symbols received. For each received output symbol, the decoder updates a running total of estimated information content and, in one or more rounds, generates a probability distribution for each input symbol over all or some of possible values. This process may be repeated until, for all of the input symbols, one of the many possible values is much more probable than others, or the process may be repeated a predetermined number of rounds, or other criteria is met.

Abstract: A system for measuring a property of a sample is provided. The system comprises a diagnostic measuring device having a memory and a diagnostic test strip for collecting the sample. The strip has embedded thereon a pattern representative of at least first data and second data, the first data being data representing at least one of parameters related to measuring the property, codes usable for calibration of the diagnostic measuring device, or parameters indicating proper connection between the measuring device and the test strip and the second data usable for detecting and rejecting potential errors affecting the proper measurement of the property.

Abstract: This invention relates to methods and devices for verifying the identity of a person based on a sequence of feature components extracted from a biometric sample. Thereafter, the feature components are quantized and assigned a data bit sequence in such a way that adjacent quantization intervals have a Hamming distance of 1. The data bit sequences are concatenated into a bit string, and said bit string is combined with a helper data set by using an exclusive disjunction (XOR) operation into a codeword. Finally, the codeword is decoded into a secret V and a secret S is matched with the secret V.

Abstract: A method, device, and computer program to generate operation codes having a maximum hamming distance between them. Utilizing these operation codes it is possible to detect errors immediately upon receipt of a first byte of data in a packet to allow the receiver to immediately act on the received data. This reduces the need for buffer space on both the transmitting and receiving devices. Further, this method reduces the latency for the receiver acting on the incoming data.

Abstract: A method for decoding a digital signal includes receiving a multiple-bit digital signal that includes information to be transmitted; arraying bit strings of the received multiple-bit digital signal to thereby generate a received signal image as a two-dimensional image; arraying all types of predetermined proper signals used for signals transmitted and bit strings of patterns including errors each derived from each proper signal to thereby generate a different two-dimensional image and disposing a set of received signal patterns, each comprised of an arbitrary proper signal and a group of two-dimensional images of patterns having the arbitrary proper signal added with an error, in a state that enables identification of each proper signal to thereby generate a received signal pattern image; using optical signal processing to evaluate a coefficient of correlation between the received signal image and the received signal pattern image to thereby obtain a correlation projection image in which depth and brightness

Abstract: A method, an apparatus and a carrier medium storing instructions to implement the method. The method is in a first wireless station of a wireless network, and includes wirelessly receiving a signal corresponding to a packet wirelessly transmitted by a second wireless station. The packet includes a subpacket and a check sequence. The method further includes verifying the integrity of the subpacket, the verifying at least using the check sequence. The method further includes, in the case that the subpacket fails the verifying, reducing the power consumption of at least one component in the first wireless station for a time interval.

Abstract: A semiconductor device is disclosed which includes a data memory which stores data and a code memory which stores an ECC code corresponding to the data. The semiconductor device includes an ECC unit which outputs, to the data memory as the data, a test pattern required to test the data memory, and which generates, from the test pattern, code information having an error checking function, and outputs the code information to the code memory as the ECC code.

Abstract: A matrix H for encoding data words is defined for wide word ECC with uniform density and a reduced number of components. The H-matrix is incorporated in an encode unit operable to Hamming encode a data word with a 10×528 matrix generated in groups of four columns wherein; a first column is a complement of a second column; the value of the second column ranges from 9 to 271 in increments of two; a third column is a complement of a fourth column; and the value of the fourth column is the same as the value of the second column less one; and wherein a 528-bit bottom row is added to the 10×528 matrix comprising alternating zeroes and ones starting with a zero creating an 11×528 matrix.

Abstract: Certain embodiments of the invention provide a method and system for TERC4 decoding using minimum distance rule. A plurality of bits may be received that may indicate addresses of samples of data. A lookup table may be generated based on the received plurality of bits to determine corresponding output samples of data. The received plurality of bits may be exclusive ORed with the generated corresponding output samples of data. A distance value for each sample of data may be calculated based on an output generated by the exclusive ORing of the received plurality of bits with the generated corresponding output samples of data. An error in each of the received samples of data may be corrected based on the calculated distance value.

Abstract: A system, method and computer software product are provided. One embodiment of the present invention provides a method for generating and employing numerical sequences that may be used for synchronization codes. In one embodiment of the present invention, the derivation of numerical sequences, or codes is based on an encoding algorithm. These codes enable synchronization between communicating devices, and may also be used for channelization. This Abstract is provided for the sole purpose of complying with the Abstract requirement rules that allow a reader to quickly ascertain the subject matter of the disclosure contained herein. This Abstract is submitted with the explicit understanding that it will not be used to interpret or to limit the scope or the meaning of the claims.

Abstract: A method and apparatus for generating an error correction code used in communicating over a channel, includes generating a set of candidate circulant blocks corresponding to a parity check matrix and a Hamming code wherein the Hamming code is initially unable to detect a predetermined error pattern without ambiguity due to one or more redundancies and eliminating columns of the parity check matrix and related redundancies in the detection of a predetermined error pattern as used by the resulting Hamming code.

Abstract: Improved memory devices, circuitry, and data methods are described that facilitate the detection and correction of data in memory systems or devices in combination with a stored record of known flaws, errors, or questionable data bits of a read memory row or block to allow for more efficient processing and correction of these errors. An embodiment of the present invention utilizes an erasure pointer that can store the location of N bad or questionable bits in the memory segment that is currently being read, where for each bit stored by the erasure pointer the embodiment also contains 2N ECC generators to allow the read data to be quickly checked with the know bad bits in each possible state. This allows the read data to then be easily corrected on the fly before it is transferred by selecting the bad bit state indicated by the ECC generator detecting an uncorrupted read.

Abstract: Methods, apparatus and systems for error correction of n-valued symbols in codewords of p n-valued symbols with n>2 and for n=2 and k information symbols have been disclosed. Coders and decoders using a Linear Feedback Shift Registers (LFSR) are applied to generate codewords and detect the presence of errors. An LFSR can be in Fibonacci or Galois configuration. Errors can be corrected by execution of an n-valued expression in a deterministic non-iterative way. Deterministic error correction methods based on known symbols in error are provided. Corrected codewords can be identified by comparison with received codewords in error. N-valued LFSR based pseudo-noise generators and methods to determine if an LFSR is appropriate for generating error correcting codes are also disclosed. Methods and apparatus applying error free assumed windows and error assumed windows are disclosed. Systems using the error correcting methods, including communication systems and data storage systems are also provided.

Abstract: Systems, methods and computer program products for providing a nested two-bit symbol bus error correcting code. Methods include constructing a nested error correcting code (ECC) scheme. The method includes receiving a Hamming distance n code. A symbol correcting code H-matrix is created by iteratively adding rows of H-matrix bits on a symbol column basis such that the symbol correcting code H-matrix describes a symbol correcting code, and the Hamming distance n code is preserved as a subset of the symbol correcting code H-matrix.

Abstract: Decoding that uses an extended Hamming code in one of the primary stages of static encoding uses a calculation of the r+1 Hamming redundant symbols for k input symbols from which Hamming redundant symbols are calculated, where r satisfies 2r?1?r?k<2r?r?1. This efficient method requires on the order of 2k+3r+1 XORs of input symbols to calculate the r+1 Hamming redundant symbols.

Abstract: A method for combining a simple forward error correction code i.e., a Hamming-like code with scrambling and descrambling functions is disclosed. Therefore, irrespective of the information to be transported, received data may be corrected, bit error spreading effects being handled, while providing desirable signal characteristics such as signal DC balance and enough signal transitions. The overhead introduced by the method is a modest increase over the original overhead of the 10 Gb Ethernet 64B/66B code.

Abstract: Error tolerance is increased for a storage system having a plurality of arrays by making local redundancy in a selected array globally available throughout the storage system. To achieve the increased error tolerance, a donor array is selected from the plurality of arrays when the difference between a minimum Hamming distance of the donor array and a minimum Hamming distance of a recipient array is greater or equal to 2. A donor storage unit is selected in the donor array and recipient information is then rebuilt from the recipient array on the selected storage unit. The selected storage unit is indicated to the donor array as having been donated before the lost information is rebuilt on the selected storage unit. Preferably, the minimum Hamming distance of the recipient array is d?2 before the donor array is selected from the plurality of arrays.

Abstract: The invention relates to a variable-length error-correcting (VLEC) code construction method, in which the main steps are: defining all the needed parameters, generating a code having a fixed length L1, storing in a set W thus obtained all the possible L1-tuples dista22nt of the minimum diverging distance d ‘min! from the codewords (one extra-bit being affixed at the end of all words if the new set W thus obtained is not empty), deleting all words of W that do not satisfy a distance criterion with all codewords, and verifying that all words of the final set W satisfy another distance criterion. Assuming that all distributions of number of codewords for the best VLEC codes have a similar curve allure of a bell shape type, it is then proposed, according to the invention, to define an optimal length value Lm until which the number of codewords increases with their length, whereas it decreases after said value Lm.

Abstract: A method, an apparatus and a carrier medium storing instructions to implement the method. The method is in a first wireless station of a wireless network, and includes wirelessly receiving a signal corresponding to a packet wirelessly transmitted by a second wireless station. The packet includes a subpacket and a check sequence. The method further includes verifying the integrity of the subpacket, the verifying at least using the check sequence. The method further includes, in the case that the subpacket fails the verifying, reducing the power consumption of at least one component in the first wireless station for a time interval.

Abstract: A semiconductor synchronous dynamic random access memory (SDRAM) device capable of correcting bits having a low error rate in a Pause Refresh Tail distribution and of reducing a data holding current by lengthening a refresh period so that the refresh period exceeds a period for a Pause Refresh real power. The semiconductor memory device is made up of a 16-bit SDRAM having a Hamming Code and including an ECC (Error Correcting Code) circuit made up of an encoding circuit controlled by a first test signal to output a parity bit corresponding to an information bit, a decoding circuit controlled by second test signal to output an error location detecting signal indicating an error bit in codeword, and an error correcting circuit controlled by a third test signal to input an error location detecting signal and to output an error bit in a reverse manner.

Abstract: A system and method to transmit and receive forward error corrected data in a diversity communications system is provided. Using diversity techniques, multiple copies of the transmitted data are received with varying degrees of corruption due to channel impairments. In addition to the multiple copies of forward error corrected data, an additional data set of implicit parity bits is used in the data decoding process, wherein the reliability of these parity bits is assumed to be very high. The implicit parity bits are not transmitted or received by the system, but are introduced in the receivers' decoding process. These implicit parity bits add an extra highly reliable dimension of forward error correction codes. Therefore the present system and methods provide an improved data decoding process with high coding gain and channel efficiency, while minimizing system resources.

Abstract: The invention relates to a variable-length error-correcting (VLEC) code technique, in which the main steps are: defining all the needed parameters, generating a code having a fixed length L1, storing in a set W thus obtained all the possible L1-tuples distant of the minimum diverging distance d[min] from the codewords (one extra-bit being affixed at the end of all words if the new set W thus obtained is not empty), deleting all words of W that do not satisfy a distance criterion with all codewords, and verifying that all words of the final set W satisfy another distance criterion. According to the invention, it is proposed to realize the codeword deletion not anymore only in the last obtained groupe of the code, but in the group of a given length value Ls to which the algorithm will skip back to in the codeword deletion operation, which allows to go back very quickly to smaller lengths and skip many steps of the previous methods.

Abstract: A method and apparatus are disclosed for MAP decoding of signals encoded using error correction codes to make maximum probability decisions about each transmitted bit. A disclosed MAP decoding algorithm extends the work of Hartman and Rudolph and exploits properties of Hamming error correction codes to provide a decoding algorithm having a complexity that is proportional to n log n for Hamming codes. The invention computes a difference, ?, of the probabilities the that transmitted symbol was zero and one based on characteristics of the channel and then determines the product of the ?l values corresponding to non-zero positions of codewords of the dual code using real vector and 2[2]-vector fast Walsh-Hadamard transforms. The invention also processes all positions of all codewords to determine a sum for each position that indicates the reliability that a received bit is a given value for a given position using the real vector fast Walsh-Hadamard transforms.

Abstract: One embodiment of the present invention provides a system that facilitates construction of a forward error correction (FEC) coded Ethernet frame. The system generates a number of FEC parity bits for the conventional Ethernet frame and inserts a start sequence before the conventional Ethernet frame. Next, the system appends an even- or odd-delimiter to the conventional Ethernet frame. The even-delimiter and the odd-delimiter are selected such that there is a sufficiently large Hamming distance between them, thereby reducing the probability of mistaking the even-delimiter for the odd-delimiter, or mistaking the odd-delimiter for the even-delimiter, if bit error occurs.

Abstract: A communications system includes an encoder that produces a plurality of redundant symbols. For a given key, an output symbol is generated from a combined set of symbols including the input symbols and the redundant symbols. The output symbols are generally independent of each other, and an effectively unbounded number of output symbols can be generated, if needed. Received output symbols can provide probabilistic information for error correction. A decoder calculates check symbols from the output symbols received. For each received output symbol, the decoder updates a running total of estimated information content and, in one or more rounds, generates a probability distribution for each input symbol over all or some of possible values. This process may be repeated until, for all of the input symbols, one of the many possible values is much more probable than others, or the process may be repeated a predetermined number of rounds, or other criteria is met.

Abstract: A method of turbo decoding using soft input-soft output information. A vector of data is sampled from a channel of data. The vector of data is then processed to output a final code word of bits. A final reliability vector of reliability values associated with the final code word is generated, such that each bit of the final code word of bits has a corresponding reliability value in the final reliability vector. Corresponding reliability values for one or more bit positions of the final code word are determined by a difference of distance metrics, and corresponding reliability values for one or more bit positions of the final code word are determined utilizing a numerical approximation.

Abstract: Architecture for enhancing the encoding/decoding of information of a channel. A stream of incoming information bits are arranged into a first array of information bits. The first array of information bits are processed into a first code of bits, which bits form a plurality of first code words having a minimum distance to neighboring error events. Selected bits of the first code are rearranged into a second array of bits by intermittent successive rotations of the selected bits of the first code. A second code is then generated from the second array of bits to increase the minimum distance to the neighboring error events.

Abstract: A method of selecting a generator matrix (G) for encoding information words (m) including information symbols (m1, m2, mk) into codewords (c) of a code (C) provides an enhanced error correction capability if at least one information symbol (m1, m2, m3) is known a priori to a decoder decoding received, possibly mutilated codewords (r). In order to design a code of which the correction power is enhanced if some information symbols are known to the decoder prior to decoding, the generator matrix (G) is selected such that the minimum Hamming distance of at least one subcode (C?) of the code (C) is larger than the minimum Hamming distance of the code (C), and that a subcode generator matrix (G?) of the at least one subcode (C?) is derived from the generator matrix (G) of the code (C) by omitting the at least one row from the generator matrix (G) corresponding to the at least one a priori known information symbol (m1, m2, m3).

Abstract: A system, method and computer program product is provided for mitigating the effects of burst noise on packets transmitted in a communications system. A transmitting device applies an outer code, which may include, for example, a block code, an exclusive OR (XOR) code, or a repetition code, to one or more packets prior to adaptation of the packets for transmission over the physical (PHY) layer of the communications system, wherein the PHY layer adaptation may include FEC encoding of individual packets. The outer coded packets are then separately transmitted over a channel of the communications system. A receiving device receives the outer coded packets, performs PHY level demodulation and optional FEC decoding of the packets, and then applies outer code decoding to the out6r coded packets in order to restore packets that were erased during transmission due to burst noise or other impairments on the channel.

Abstract: A hashing system produces hash values by manipulating n-bit sequences in accordance with a selected distance d error correction code (“ECC”) over an associated Galois Field. The current system produces a hash value for a given n-bit sequence by treating the sequence as either a corrupted n-bit ECC codeword or as “n” information bits of an (n+r)-bit ECC codeword. The hashing system may decode the n bits as a corrupted codeword of an (n, k, d) perfect ECC to produce an n-bit error-free codeword, and then use as the hash value the information bits of the error-free codeword. Alternatively, the hashing system may treat the n-bit sequence as a corrupted code word of a cyclic distance d ECC, and map the codeword to an (n?k)-bit “error pattern” that the system then uses as the hash value. The hashing system may instead treat the n-bit sequence as n “information” bits and encode the bits in accordance with an (n+r, n, d) ECC, to produce an r-bit hash value that consists of the associated redundancy bits.

Abstract: A method (and system) of finding byte synchronization over random data, which includes selecting a synchronization symbol maximizing the Hamming distance when slid over itself, and appending the synchronization symbol to random data.

Abstract: A memory system and method for processing a data structure comprising a plurality of data bits representing a line of memory, wherein the data bits are divided into a plurality of data chunks, each of the data chunks including at least an error correction code portion and a data portion; and a first chunk of said plurality of data chunks having a tag portion, wherein said tag portion includes tag information for the entire line of memory, and wherein subsequent ones of said data chunks do not include tag information.

Abstract: A method, device, and computer program to generate operation codes having a maximum hamming distance between them. Utilizing these operation codes it is possible to detect errors immediately upon receipt of a first byte of data in a packet to allow the receiver to immediately act on the received data. This reduces the need for buffer space on both the transmitting and receiving devices. Further, this method reduces the latency for the receiver acting on the incoming data.

Abstract: Correction and location information are determined from a number of data vectors. The location information comprises values determined from subsets of the data vectors. Two or more of the subsets have one or more data vectors in common, but also have one or more data vectors, in one or more of the subsets, that are not in other subsets. The subsets comprise groups of data vectors, and the groups of data vectors have a size that is a function of a power of two. Transmission codes are used on the data vectors and correction and location information. Received location information and determined location information are compared to determine a data vector having an error. Received correction information and determined correction information are compared to correct the data vector having the error. Failing optical lanes may be replaced efficiently by using a number of multiplexers coupled to electrical lanes and optical lanes.

Abstract: Generating a check matrix includes defining a set of column vectors. A matrix operable to have a plurality of entries is initiated. Each entry has a submatrix that includes a function of a subset of the set of column vectors. The following is repeated until a last entry of the matrix is reached. Subsets of the set of column vectors are generated from the set of column vectors, and an entry is generated from each subset. A weight associated with each entry is calculated, and an entry having a minimum weight is selected. The selected entry is added to the matrix, and the subset of column vectors associated with the selected entry is removed from the set of column vectors. The matrix is reported.