Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, data decoding systems are disclosed that include a data decoder circuit and a decode value modification circuit.

Abstract: A demodulation circuit includes a hard decision process unit and a soft decision process unit. The hard decision process unit is configured to perform a hard decision process using a demodulated signal, and the demodulated signal is a demodulated received signal. The soft decision process unit is configured to determine a range of assignment with respect to a transitioning part in the demodulated signal, calculate a likelihood value of a bit, and perform a soft decision process.

Abstract: A method and system for demapping a hierarchical signal is disclosed. The method includes receiving a hierarchical signal comprising first and second encoded, modulated signals. A conditional probability relating to the structure of the second encoded, modulated signal is determined. The hierarchical signal is demodulated using the conditional probability to generate a first encoded data stream. The first encoded data stream is decoded to recover information bits.

Abstract: A code word is received that was derived from a plurality of smaller code words that represent a data word of 2m data bits and a plurality of error correction code bits. The code word is converted into the plurality of smaller code words and syndromes are computed by multiplying each of the plurality of smaller code words by a check matrix. The syndrome words are processed to determine a number of errors that exist in each of the plurality of smaller code words. A portion of the syndrome words is processed to determine locations of possible errors within the plurality of smaller code words. Up to two errors may be corrected and up to three errors may be detected in the code word by using the number of errors and the locations of possible errors to determine erroneous bits in the code word.

Abstract: Apparatus and methods are disclosed for decoding data stored on a data storage medium. A disclosed decoding method and decoder include a radial incoherence (RI) detector that increases the probability of detecting RI and improves the decoding performance in terms of the bit error rate of the decoded signal. RI is detected by comparing an input signal to the decoder against a RI threshold value and generating a RI-type signal. The RI detector may include a filter for filtering out noise and error in the RI-type signal, an adaptive threshold unit that adjusts the RI threshold value based upon the RI-type signal, a transition-based threshold unit that adjusts the RI threshold value based upon each transition in the input signal, or a path-based threshold unit that adjusts the RI threshold value based upon a best surviving path corresponding to the input signal, in combination or alone.

Abstract: A wireless communications device includes a receiver, and a decoder coupled downstream from the receiver and using a modulation having memory for a received signal and to decode the received signal. The decoder decodes the received signal by at least determining a channel estimate for the received signal, generating partial sum tables based upon the channel estimate and possible values of a transmitted signal, correlating actual values of the received signal to the possible values from the partial sum tables to generate branch metrics associated with the modulation, and demodulating the received signal based upon the branch metrics using an iterative process based upon exchanging extrinsic information with an outer forward error correction (FEC) code.

Abstract: A modified soft output Viterbi algorithm (SOVA) detector receives a sequence of soft information values and determines a best path and an alternate path for each soft information value and further determines, when the best and alternate paths lead to the same value for a given soft information value, whether there is a third path departing from the alternate path that leads to an opposite decision with respect to the best path for a given soft information value. The SOVA detector then considers this third path when updating the reliability of the best path. The modified SOVA detector achieves max-log-map equivalence effectively through the Fossorier approach and includes modified reliability metric units for the first N stages of the SOVA detector, where N is the memory depth of a given path, and includes conventional reliability metric units for the remaining stages of the detector.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes a channel detector circuit. The channel detector circuit includes a branch metric calculator circuit that is operable to receive a number of violated checks from a preceding stage, and to scale an intrinsic branch metric using a scalar selected based at least in part on the number of violated checks to yield a scaled intrinsic branch metric.

Abstract: Devices, systems, methods, and other embodiments associated with generating a moving average are described. In one embodiment, a method calculates, using at least an accumulator, an average value of M sequential data values is calculated, where M is an integer. The M sequential data values are delayed before passing a delay output. The method detects a data value with an error in the M sequential data values that are delayed and controls the accumulator to correct the average value of the M sequential data values as a function of the error.

Abstract: A method includes, during a first iteration of a first decoder for decoding convolutionally encoded data elements, determining a first value of a first path metric. The method also includes, during a second iteration of the first decoder, determining a second value of the first path metric by using the first value of the first path metric as an initial value of the first path metric.

Abstract: A method for communication includes receiving at a receiver a signal from a transmitter embodying data encoded with an error correction code. The signal is processed in order to extract a sequence of samples in a complex signal space. Scalar values are extracted from the samples and the scalar values are processed so as to define one or more clusters of scalar data points. Gain and noise of the signal are estimated responsively to the defined clusters. Bit value metrics for the signal are computed based on the samples and the estimated gain and noise of the signal. The error correction code is decoded using the bit value metrics.

Abstract: A receiver system and method for recovering information from a symbol data sequence Y. The symbol data sequence Y corresponds to a symbol data sequence X that is transmitted onto the channel by a transmitter. The symbol data sequence X is generated by the transmitter based on associated information bits. At the receiver, a set of two or more processors operate in parallel on two or more overlapping subsequences of the symbol data sequence Y, where each of the two or more overlapping subsequences of the symbol data sequence Y corresponds to a respective portion of a trellis. The trellis describes redundancy in the symbol data sequence Y. The action of operating in parallel generates soft estimates for the associated information bits. The soft estimates are useable to form a receive message corresponding to the associated information bits.

Abstract: A method for operating a Viterbi decoder uses few data move operations to improve efficiency. The Viterbi decoder predicts a state in which the convolution encoder might have operated while generating a convolutionally encoded data stream. The Viterbi decoder maintains a first set of states and based on the received convolutionally encoded data stream, predicts second and third sets of states. The Viterbi decoder then calculates first and second sets of decision bits based on the transitions to the second and third sets of states. Path metric values associated with the third set of states are stored in a memory buffer. Thereafter, during trace-back, the Viterbi decoder extracts first and second decoded bits from first and second sets of decision bits respectively.

Abstract: In an aspect, in general, a forward error correction algorithm (FEC) utilizes an FEC block structure in a manner that extends the effective error correction such that it can approach an “infinite” length to obtain benefits typical of very large FEC block size without the commensurate computation cost.

Abstract: A method and apparatus for performing demapping in a wireless communication system utilizing a modulo operation are disclosed. The demapping method of a receiver in a wireless communication system includes receiving an input signal and first information indicating whether a first modulo operation is performed on the input signal from a transmitter; if the first information indicates execution of the first modulo operation, performing a second modulo operation of the input signal, and acquiring a reception signal; generating a maximum function value having a highest probability that the reception signal corresponds to a candidate constellation point of an extended constellation; and generating a log-likelihood ratio (LLR) using the generated maximum function value.

Abstract: A Viterbi decoder which is based on a special instruction set implemented in the processor, enabling it to handle the Viterbi processing with a much lower CPU loading without significantly increasing the hardware complexity. By careful application of appropriate design constraints specific to the SV navigation and analysis of the Viterbi algorithm an optimised architecture can be realized for embedding Viterbi acceleration logic efficiently into a GNSS chipset.

Abstract: Systems and methods for processing and decoding TCM/BCM-coded signal vectors. A multi-dimensional signal vector is received by, for example, a TCM or BCM decoder. The TCM/BCM decoder identifies the closest signal points in the signal constellation set, or “nearest neighbors,” for each dimension of the received signal vector. The TCM/BCM decoder then forms a test set that includes a plurality of multi-dimensional test vectors, where each dimension of each test vector is based on an identified nearest neighbor. In particular, each test point in the test set is based on a different combination of the nearest neighbors. The TCM/BCM decoder can compute branch metrics based on only the test points in the test set, and can make detection decisions using the computed branch metrics.

Abstract: A method and system for a sequence estimation in a receiver, such as for use when receiving a sample of a received inter-symbol correlated (ISC) signal corresponding to a transmitted vector of L symbols, with L being a integer greater than 1, and with symbol L being a most-recent symbol and symbol 1 being least recent symbol of the vector. A plurality of candidate vectors may be generated, wherein element L-m of each candidate vector holding one of a plurality of possible values of the symbol L-m, with m is an integer greater than or equal to 1, and elements L-m+1 through L of each candidate vectors holding determined filler values. A plurality of metrics may be generated based on the plurality of candidate vectors, and based on the generated plurality of metrics, a best one of the possible values of the symbol L-m may be selected.

Abstract: This invention relates to methods for obtaining a bin number of path metrics. When performing such methods, a histogram is provided, which composes a bin number of values, a maximum value and a tail region left or right of the maximum value. A bin number of path metrics is obtained from said values. According to an embodiment a local extremum is removed from said tail region. According to another embodiment the tail region is forced to be convex. According to a further embodiment a maximum metric difference between neighboring metrics is ensured.

Abstract: A decoding circuit, is provided, comprising: a turbo decoder configured to receive a input systematic bit soft information values and input parity bit information values, and to generate output systematic bit soft information values and hard decoded bits according to a turbo decoding operation; and a parity bit soft information generation circuit configured to receive the input systematic bit soft information values, the input parity bit soft information values, and the output systematic bit soft information values; to determine initial forward metrics, initial backward metrics, and branch metrics as a function of the input parity bit soft information values and the output systematic bit soft information values; to determine output parity bit soft information values based on the branch metrics, the initial forward metrics, and the initial backward metrics; and to provide the output parity bit soft information values as a signal output.

Abstract: This invention relates to a method and a circuit for estimating the bit error rate in a data transmission system. Symbols are detected (u) by a maximum likelihood detector (1), which provides path metrics of the decoded path and the best competitor at predetermined symbol positions. Absolute path metric differences (2) are calculated between the decoded path and the best competitor at said predetermined symbol positions. Events (5) are counted when an absolute path metric difference (2) is equal to one of a set of difference values. The bit error rate is estimated based on the number of counted (4) events (5). The invention further comprises a method and a circuit in which a function is applied onto said absolute path metric difference. The function maps quantized logarithms of probabilities to probabilities.

Abstract: The present disclosure describes a method, performed by a data processor comprising a cyclic redundancy check (CRC) module configured for calculating CRC remainders for encoded data and a comparator comprising a shift register, for making a cyclic redundancy check of an encoded data record of bit length L, in which at least A bits of the record represent content data and at least B bits represent check data. A system for performing a cyclic redundancy check is also described.

Abstract: The various embodiments provide circuitry and methods for packing Log Likelihood Ratio (“LLR”) values into a buffer memory in a compressed format which reduces the amount of buffer memory required. Various embodiments use a type of quantization which reduces the bit width of the LLR values that are stored, with the particular level of quantization depending upon the code rate of the data. The degree, pattern, and periodicity of bit width compression employed may depend upon the code rate of the received transmission. Bit width patterns use for LLR value quantization may be generated by a shift register circuit which provides an efficient mechanism for controlling an LLR packer circuit based upon the code rate of the received signal.

Abstract: A sequence estimator is described. In one embodiment, the sequence estimator includes a plurality of maximum a posteriori probability (MAP) decoding engines each arranged to process a series of windows of a transmitted signal where state metrics produced for an end of one window by one decoding engine are re-used for the initialization of a state metric calculation process performed by another decoding engine on another window of the signal.

Abstract: A method for soft remodulation in a receiver of transmissions over a wireless telecommunication system, the method including obtaining from a FEC decoder a-posteriori LLR values, converting the a-posteriori LLR values into bit probabilities and computing improved soft symbols estimates as expected values using the bit probabilities in a recursive algorithm. Preferably, the step of converting is implemented using a pre-computed Look Up Table (LUT). Preferably, the step of computing is implemented in a Multiplier-Accumulator having a SIMD structure.

Abstract: A plurality of columns for a check matrix that implements a distance d linear error correcting code are populated by providing a set of vectors from which to populate the columns, and applying to the set of vectors a filter operation that reduces the set by eliminating therefrom all vectors that would, if used to populate the columns, prevent the check matrix from satisfying a column-wise linear independence requirement associated with check matrices of distance d linear codes. One of the vectors from the reduced set may then be selected to populate one of the columns. The filtering and selecting repeats iteratively until either all of the columns are populated or the number of currently unpopulated columns exceeds the number of vectors in the reduced set. Columns for the check matrix may be processed to reduce the amount of logic needed to implement the check matrix in circuit logic.

Abstract: Various embodiments of the present invention provide systems and methods for generating a code format. One method discussed includes: Various embodiments of the present invention provide methods for generating a code format. Such methods include: receiving an indication of a low weight codeword having a trapping set; selecting an initial value for a base matrix; testing the low weight codeword after modification by the initial value to determine an updated weight of the low weight codeword; and testing the low weight codeword after modification by the initial value to determine whether the trapping set remains.

Abstract: The invention disclosed in this application describes an error detection method that can be used to identify an OFDM symbol that is interfered with. The method is based on computing a symbol by symbol path error metric from error correction code and by comparing the statistics of each individual symbol to the mean and the variance of the metric computed from the whole data packet.

Abstract: A pre-decoded tail-biting convolutional code (TBCC) decoder and a decoding method thereof are provided. The decoder includes a pre-decoder, a storage module, and a control module. The pre-decoder receives a current state, a neighboring state, and a current path status corresponding to sequential data encoded in TBCC, generates predicted decoded bits, and determines whether states corresponding to minimum path metrics of neighboring stages are in continuity according to the current state, the neighboring state, and a current path status. The storage module is connected to the pre-decoder and stores the predicted decoded bits. The control module is connected to the storage module and the pre-decoder. In addition, the control module selects to output the decoded bits from the storage module when the continuity between the states corresponding to the minimum path metrics of the neighboring stages reaches a truncation length.

Abstract: A low complexity List Viterbi algorithm (LVA) for decoding tail biting convolutional codes (TBCCs) has lower complexity than a solution of running the LVA algorithm for all states. In one aspect, a low complexity LVA-TBCC process includes finding a list of states from a single Viterbi algorithm and finding a list of potential codewords for each state in the state list using the LVA. A cyclic redundancy check may prune out false solutions. The disclosed method may be applied to many communication systems to improve error performance similar to LTE downlink PBCH decoding enhancements.

Abstract: An iterative decoder for decoding a code block comprises a computation unit configured to perform forward and backward recursions over a code block or a code sub-block in each decoding iteration. A first forward/backward decoding scheme is used in a first iteration and a second forward/backward decoding scheme is used in a second iteration. The first and second decoding schemes are different in view of forward and backward processing.

Abstract: An apparatus and method for high throughput unified turbo decoding comprising loading data from a first data window; computing a first forward state metric using the data from the first data window; storing the first forward state metric in a memory; computing a first reverse state metric using the data from the first data window; storing the first reverse state metric in the memory; and computing the log likelihood ratio (LLR) of the first forward state metric and the first reverse state metric. In one aspect, the above-mentioned steps are repeated with data from a second data window. In another aspect, extrinsic information for the first data window associated with the unified turbo decoding is computed.

Abstract: One embodiment of the present invention relates to a method of detecting potential performance degradation caused by neighboring identical scrambling codes. The method includes detecting an existence of identical scrambling codes in received signals from different cell at the user equipment, and selectively eliminating one or more signals from consideration in processing of received signals based upon the detection. The invention also includes a receiver configured to detect potential performance degradation caused by neighboring identical scrambling codes. The receiver includes a detection component configured to detect an existence of identical scrambling codes in received signals from different base stations at the user equipment, and an elimination component configured to selectively eliminate one or more signals from consideration in processing of received signals based upon the detection by the detection component.

Abstract: In a symbol mapping method, transmission data is encoded to generate information bits and redundancy bits. An average LLR value of bits on which the information bits are mapped is different from an average LLR value of bits on which the redundancy bits are mapped.

Abstract: Techniques are provided for transmitting and receiving a mother code in an incremental redundancy hybrid automatic repeat-request protocol. Each bit position of the mother code may be mapped to an output symbol, and each output symbol may be mapped to an antenna for transmission. One or more transmissions of symbols contained in the output symbols may be performed, where each transmission may include puncturing the mother code by selecting one or more symbols from the of output symbols, and transmitting each symbol in the one or more symbols on an antenna corresponding to that symbol. The mother code may be decoded, in part, by determining combinable bits contained within a set of received symbols, and computing one or more log-likelihood ratio values corresponding to each symbol in the set of received symbols.

Abstract: The device is used for decoding convolution-encoded reception symbols. In this context, transmission data are modulated with a modulation scheme to form symbols, which are encoded with a transmission filter to form convolution-encoded transmission symbols. A convolution-encoded transmission symbol contains components of several symbols arranged in time succession. These transmission symbols are transmitted via a transmission channel and received as reception symbols. The Viterbi decoder decodes the reception symbols by use of a modified Viterbi algorithm. Before running through the Viterbi decoder, the reception symbols are processed by a state-reduction device, which determines additional items of information relating to possible consequential states of the decoding independently of the decoding through the Viterbi decoder in every state of the decoding. The state-reduction device uses the additional items of information to restrict the decoding through the Viterbi decoder to given consequential states.

Abstract: A method of detecting received data in a communication system includes the steps of: performing a QR decomposition on a received input vector as a function of one or more characteristics of a communication channel over which the input vector was transmitted; generating a subset of best symbol candidates from a symbol constellation by comparing an input sample (corresponding to an element of the input vector) with one or more prescribed thresholds; identifying at least one symbol satisfying prescribed minimum Euclidian distance criteria among multiple ambiguity symbols in the subset of best symbol candidates; and generating a subset of best symbols including a prescribed number of symbols from the symbol constellation determined to be closest to the input sample. The subset of best symbols is used in a subsequent iteration of the steps of generating the subset of best symbol candidates and identifying at least one symbol satisfying the prescribed minimum Euclidian distance criteria.

Abstract: To decode a representation, imported from a channel, of a codeword that encodes K information bits as N>K codeword bits, estimates of the codeword bits are updated by exchanging messages between N bit nodes and N?K check nodes of a graph in a plurality of iterations. In each of one or more of the iterations, some or all values associated with the bit nodes, and/or some or all values associated with check nodes, and/or some or all messages are modified in a manner that depends explicitly on the ordinality of the iteration and is independent of any other iteration. Alternatively, the modifications are according to respective locally heteromorphic rules.

Abstract: A multi-tone transceiver with a components forming a transmit path and a receive path configured to couple via a subscriber line to an opposing multi-tone transceiver for frequency division multiplexed multi-tone modulated communications therewith is disclosed. A noise margin channel identifier is configured to identify within a received tone set, discrete tones each associated with a corresponding one of at least two channels differing from one another in a relative noise margin of associated tones. A Viterbi decoder is responsive to the channel identification provided by the noise margin channel identifier to discretely decode each of the at least two channels; thereby improving the fidelity of the error correction provided by the Viterbi decoder by discretely processing the identified channels within the received set of tones.

Abstract: Systems and methods are disclosed for detecting temporary high level impairments, such as noise or interference, for example, in a communications channel, and subsequently, mitigating the deleterious effects of the dynamic impairments. In one embodiment, the method not only performs dynamic characterization of channel fidelity against impairments, but also uses this dynamic characterization of the channel fidelity to adapt the receiver processing and to affect an improvement in the performance of the receiver. For example, in this embodiment, the method increases the accuracy of the estimation of the transmitted information, or similarly, increases the probability of making the correct estimates of the transmitted information, even in the presence of temporary severe levels of impairment. The channel fidelity history may also be stored and catalogued for use in, for example, future optimization of the transmit waveform.

Abstract: A decoding method decodes N received branchwords produced by a convolutional encoder using a tail-biting convolutional code. N received branchwords are in memory. Viterbi updates are performed on a sequence of branchwords. A first encoder determines a state at the end of the third block most likely to have generated the final branchword in the sequence from the best path metric. A Viterbi traceback procedure is performed from that first encoder state at the end of the third block to determine a second encoder state at the start of the third block of branchwords. A Viterbi traceback procedure is performed from that second encoder state at the start of the third block to determine a third encoder state at the start of the second block of branchwords. A derived tail-biting path is output, if the second and third encoder states are identical.

Abstract: A soft symbol decoder for use in a multiple input multiple output (MIMO) and OFDM (orthogonal frequency division multiplexing) system. The decoder generates soft symbol values for a digital signal that represents a number of source bits. The source bits are transmitted as symbols in corresponding to points in a signaling constellation. Soft metrics are determined by searching for all possible multi-dimensional symbols that could have been transmitted. The method includes transmitting a sample of the multi-dimensional symbol using K transmit antennas. The multi-dimensional symbol is represent-able as a complex, K-dimensional vector x. Each vector component of vector x represents a signal transmitted with one of the K transmit antennas. After transmission through a communication channel, a sample corresponding to the transmitted sample is received. The received sample is represented by a complex, N-dimensional vector y, where N is the number of receive antennas in the MIMO system.

Abstract: A memory system includes: a memory controller including an error correction decoder. The error correction decoder includes: a demultiplexer adapted to receive data and demultiplex the data into a first set of data and a second set of data; first and second buffer memories for storing the first and second sets of data, respectively; an error detector; an error corrector; and a multiplexer adapted to multiplex the first set of data and the second set of data and to provide the multiplexed data to the error corrector. While the error corrector corrects errors in the first set of data, the error detector detects errors in the second set of data stored in the second buffer memory.

Abstract: A reception apparatus including: a detection unit detecting extrinsic information based on a tentative symbol decision signal, a channel estimation signal, a noise variance estimation signal, and a received signal that are obtained from a previous iteration process; a Cyclic Redundancy Check (CRC) aided channel decoding unit outputting an interleaved bit or a posteriori information thereof based on the extrinsic information; a tentative symbol decision unit determining a tentative transmission symbol based on an output of the CRC aided channel decoding unit; a channel estimation unit estimating a channel based on an output of the tentative symbol decision unit; and a noise variance estimation unit estimating a noise variance based on the output of the tentative symbol decision unit and an output of the channel estimation unit is provided.

Abstract: Minimal hardware implementation of non-parity and parity trellis. More than one type of trellis can be represented using a minimal amount of hardware. In magnetic recording systems and other communication systems types, there is oftentimes a need to switch between trellises which support parity and ones which do not. Rules are presented herein which will ensure joint representation of more than one trellis while requiring minimal additional hardware when compared to representing only one trellis. To represent the non-parity trellis, emanating states, resultant states, and one or more expansion states (if needed) are all that is required. Any expansion states may also need to have its path metric and path memory corresponded to one of the resultant states to ensure proper detection according to the non-parity trellis.

Abstract: Apparatus and methods are disclosed for decoding data stored on a data storage medium. A disclosed decoding method and decoder include a radial incoherence (RI) detector that increases the probability of detecting RI and improves the decoding performance in terms of the bit error rate of the decoded signal. RI is detected by comparing an input signal to the decoder against a RI threshold value and generating a RI-type signal. The RI detector may include a filter for filtering out noise and error in the RI-type signal, an adaptive threshold unit that adjusts the RI threshold value based upon the RI-type signal, a transition-based threshold unit that adjusts the RI threshold value based upon each transition in the input signal, or a path-based threshold unit that adjusts the RI threshold value based upon a best surviving path corresponding to the input signal, in combination or alone.

Abstract: A method for a decoding device to decode a codeword matrix of a product code includes: generating a first extended parity check matrix for a vertical code; decoding a horizontal codeword of a plurality of rows in the codeword matrix to thus perform a first decoding process; generating a second extended parity check matrix by removing a column corresponding to a row of the first decoding-succeeded horizontal codeword from the first extended parity check matrix; and decoding the first decoding-failed horizontal codeword by using the second extended parity check matrix to thus perform a second decoding process. Therefore, the simple and reliable product code decoding method is provided.

Abstract: According to an example embodiment, a method of generating a soft decision value using an Analog-to-Digital Converter (ADC) having a given resolution may include receiving metric values calculated based on levels of a transmission signal and output levels of the ADC. Metric values corresponding to a level of a received signal may be selected from among the received metric values. A first maximum metric value may be detected from among the selected metric values when a transmission bit is a first level, and a second maximum metric value may be detected from among the selected metric values when the transmission bit is a second level. The soft decision value may be generated based on a difference between the first maximum metric value and the second maximum metric value.

Abstract: A method for decoding an Error Correction Code (ECC) includes accepting coefficients, including at least first and second coefficients, of an Error Locator Polynomial (ELP) that is defined over a vector space and has at least one root that is indicative of a location of an error in a set of bits, which represent data that has been encoded with the ECC. The first coefficient is represented using a first basis of the vector space, and the second coefficient is represented using a second basis of the vector space, different from the first basis. Using processing circuitry, the root of the ELP is identified by applying algebraic operations to the coefficients, such that the algebraic operations are applied to the first coefficient using the first basis, and to the second coefficient using the second basis. The error is corrected responsively to the identified root of the ELP.

Abstract: A decoding device allowing a high-speed decoding operation. In a decoding section (215), if a degree of a check equation by a check matrix is D and the relationship between the check equation of the j+first row of the check matrix and the cheek equation of the jth row is shifted by n-bit, row processing operation sections (405#1 to 405#3) and column processing operation sections (410#1 to 410#3) perform the operation of a protograph in which the columns of the check matrix are delimited for each “(D+1)×N (N: natural number),” and the rows of the check matrix are delimited for each “(D+1)×N/n,” and formed as the processing unit of the row processing operation and column processing operation.