Abstract: Compact pulse shape partial response (CPS PR) signaling is developed for trellis based signals like QM-MSK, and for PAM/QAM type signals to improve the performance to bandwidth tradeoff. Compact pulse shaped signals are partial response signals that employ a very short pulse shaping filter and use Viterbi decoding to optimally detect the CPS signal in presence of its inherent inter-symbol interference. The CPS filters considered herein have much shorter impulse response than the well-known raised cosine (RC) filter. There is no need to equalize the received signal to eliminate ISI or to allow a fixed amount of ISI between received signal samples as sampled at the symbol rate as is common in partial response maximum likelihood (PRML) systems. Numerical results indicate that CPS QM-MSK and CPS QAM provides between several dB of gain, depending on constellation size, over PR-CPM and RC QAM, when compared at a given value of bandwidth, i.e., B99Tb.

Abstract: An apparatus for determining a symbol estimate includes a detection unit, an information storage, a channel decoder, and an estimator. One or more detectors of the detection unit is configured to detect a first data stream and the one or more detectors or one or more other detectors are configured to detect a second data stream when interference cancellation is carried out and when interference cancellation is not carried out parallel to detection of a first data stream to obtain results of detection. The information storage is configured to store the results of the detection of the second data stream, and the channel decoder is configured to channel decode a detected first data stream. The estimator is configured to determine a symbol estimate by using the stored results of the detection of the second data stream and based on the success of the channel decoding of the first data stream.

Abstract: A high speed add-compare-select (ACS) circuit for a Viterbi decoder or a turbo decoder has a lower critical path delay than that achievable using a traditional ACS circuit. According to one embodiment of the invention, the path and branch metrics are split into most-significant and least-significant portions, such portions separately added in order to reduce the propagation delay.

Abstract: A disk drive is disclosed comprising a disk, a head actuated over the disk to generate a read signal, and a trellis detector for detecting an estimated data sequence from the read signal. The trellis detector comprises a sampling device operable to sample the read signal to generate a sequence of signal sample values, and a plurality of add/compare/select (ACS) circuits each corresponding to a state in a trellis. Each ACS circuit comprises a first and second branch metric calculators for computing first and second branch metrics in response to first and second errors adjusted in response to first and second deltas that compensate for a distortion in the read signal.

Abstract: A decoding apparatus includes a row processing unit 5 and a column processing unit 6 for performing a calculation and an update of probability information with row processing and column processing according to a Min-Sum algorithm on a received signal which is low-density parity-check coded in batches of 1 bit or a predetermined number of bits, a decoded result judgment unit 8 for determining a decoded result from a hard decision of a posterior value, for performing a parity check on the decoded result, and for judging whether or not the decoded result is correct, and a control unit for controlling iteration of decoding processing by the row processing unit 5 and column processing unit 6 on the basis of the judgment result of the decoded result judgment unit 8.

Abstract: A method and system are provided for improving the performance of a trellis-based decoder. States with reduced uncertainty (SRUs) are defined for one or more predetermined fields in an encoded message. Metrics are set for the SRUs such that candidate paths through a trellis-based decoding process are eliminated for those states that are not SRUs.

Abstract: Methods and corresponding systems in a Viterbi decoder include computing a maximum likelihood (ML) path in a Viterbi trellis in response to executing a first Viterbi algorithm. Thereafter, one or more merge points are selected on the ML path in a second Viterbi algorithm, wherein the merge points each have a path metric difference, which is a difference between an ML path metric at the merge point and a non-surviving path metric at the merge point. Merge points are selected based upon relative path metric differences associated with nodes on the ML path. Next, alternate paths in the Viterbi trellis are computed based on the ML path with alternate paths substituted at corresponding merge points. A passing decoded bit sequence is output in response to passing an error check, wherein the passing decoded bit sequence is associated with one of the one or more alternate paths.

Abstract: A pre-encoding apparatus and a pre-decoding apparatus are provided. The pre-encoding apparatus adopts a cascade structure constituted by a plurality of pre-encoding units and a plurality of interleavers for pre-encoding, and the pre-decoding apparatus adopts a cascade structure constituted by a plurality of pre-decoding units and a plurality of de-interleavers for pre-decoding. Therefore, the pre-decoding apparatus is featured with a lower error rate. Also, each of the pre-decoding units can be alternatively composed of a plurality of low dimensional pre-decoders so that a computation complexity of the pre-decoding apparatus can be reduced accordingly.

Abstract: A device and a method for turbo decoding, the method includes performing multiple iterations of a turbo decoding process until a turbo decoding process is completed; wherein the performing comprises repeating the stages of: (i) initializing at least one state metric of multiple windows of a channel data block for a current iteration of the turbo decoding process by at least one corresponding state metric that was calculated during a previous iteration of the turbo decoding process; and (ii) calculating in parallel, at least forward state metrics and backward state metrics of the multiple windows, during the current iteration.

Abstract: A non-linear detector for detecting signals with signal-dependent noise is disclosed. The detector may choose a data sequence that maximizes the conditional probability of detecting the channel data. Since the channel may be time-varying and the precise channel characteristics may be unknown, the detector may adapt one or more branch metric parameters before sending the parameters to a loading block. In the loading block, the branch metric parameters may be normalized and part of the branch metric may be pre-computed to reduce the complexity of the detector. The loading block may then provide the branch metric parameters and any pre-computation to the detector. The detector may then calculate the branch metric associated with the input signal and output the channel data.

Abstract: A channel impulse response is determined for a channel by receiving a signal from the channel, and by determining a least squares estimate of the channel impulse response. The received signal contains a training sequence and unknown data. The least squares estimate of the channel impulse response is determined by multiplying the received signal by a stored quantity. The stored quantity is based on (i) a stored replica of the training sequence, and (ii) an assumed covariance matrix that is based on a noise variance and an initial channel impulse response that assumes a unit physical channel.

Abstract: Methods and apparatus are provided for processing a plurality of data blocks. In accordance with embodiments of the invention, a correction flag for each of the data blocks can be received, along with information on at least one error event for each of the data blocks. Using this received information, a search trellis corresponding to the data blocks can be determined. Determining the search trellis can include determining a plurality of branches and computing a branch metric for each of the branches. A search on the search trellis can be performed to identify at most one error event for each data block, where the search is based on the branch metrics.

Abstract: Methods and apparatus are provided for storing survivor paths in a Viterbi detector. The invention maintains at least one register and at least one pointer for each state. Each register stores a bit sequence associated with a Viterbi state and each pointer points to one of the registers. One or more predefined rules based on a trellis structure are employed to exchange one or more of the pointers. A survivor path memory is also disclosed for a Viterbi detector. The survivor path memory comprises a plurality of columns, each associated with a different time step, and an input processor. Each column comprises a flip flop for storing one bit or portion of a bit sequence associated with a Viterbi state; and a multiplexer for each state controlled by a case signal indicating a time step, the multiplexer selecting a state from a previous time step, wherein an output of the multiplexer of a given state is connected to at least one data input of a flip flop of the given state.

Abstract: Provided are a detector for a multi-level modulated signal and a detection method using the same, and an iterative receiver for a multi-level modulated signal and an iteratively receiving method using the same. The detector includes: a channel estimator estimating a channel response of each of a plurality of bits included in at least one received signal based on multi-level modulation; a hard decision unit, for each bit, selecting at least one of a plurality of bits remaining by excluding the bit and performing a hard decision based on a pre-probability of the selected bit; and a reliability calculator calculating reliability of each of all the bits in the received signal based on the received signal from which the hard-decided bit component is cancelled and the estimated channel response. Accordingly, the computation amount according to detection can be reduced without the degradation of performance.

Abstract: A semiconductor memory device includes a memory cell array and an error correction code (ECC) engine. The memory cell array stores bits of normal data and parity data therein. The ECC engine performs a masking operation in a masking mode, the ECC engine calculating the parity data using the normal data. The normal data includes a first section that is to be updated and a second section that is to be saved by the masking operation.

Abstract: Devices, methods, and systems of a communications channel detector are disclosed that can compare a plurality of candidate sequences of bits and decisions to identify unlikely error events. The detector may then discard at least one candidate sequence based on an unlikely error event to produce a set of remaining paths. A branch metric calculator may be adapted to calculate metrics for a set of remaining paths.

Abstract: Various embodiments relate to a multi-standard Viterbi decoder. Based on programmable values for constraint length, generator polynomials, and code rate, the multi-standard Viterbi decoder may adhere to a specific convolutional code standard. At a given time, the multi-standard Viterbi decoder may receive a variety of convolutional codes through a channel and may process them using various forms of the trace back method. Various embodiments include a branch metric unit and path metric unit that include a variety of sub-units that may or may not be active based on the value of the programmable value. Various embodiments also enable the multi-standard Viterbi decoder to handle different forms of convolutional codes, such as tail-biting codes. In some embodiments, the multi-standard Viterbi decoder may also process at least two convolutional codes concurrently.

Abstract: A baseband processor is provided having Turbo Codes Decoders with Diversity processing for computing baseband signals from multiple separate antennas. The invention decodes multipath signals that have arrived at the terminal via different routes after being reflected from buildings, trees or hills. The Turbo Codes Decoder with Diversity processing increases the signal to noise ratio (SNR) more than 6 dB which enables the 3rd Generation Wireless system to deliver data rates from up to 2 Mbit/s. The invention provides several improved Turbo Codes Decoder methods and devices that provide a more suitable, practical and simpler method for implementation a Turbo Codes Decoder in ASIC (Application Specific Integrated Circuits) or DSP codes. A plurality of parallel Turbo Codes Decoder blocks is provided to compute baseband signals from multiple different receiver paths. Several pipelined max-Log-MAP decoders are used for iterative decoding of received data.

Abstract: According to one aspect of the present invention, an apparatus is provided to enable weather band radio signals to be received and processed using a digital signal processor (DSP). The DSP can include functionality to implement both frequency modulation (FM) demodulation and weather band data demodulation, i.e., specific area encoding (SAME) demodulation. In one such embodiment, soft decision samples of a SAME message can be combined, and based on a combined result, a hard decision unit can generate a bit value of weather band data.

Abstract: A Viterbi decoder includes a branch metric unit, an add-compare select unit coupled to the branch metric unit, and a trace-back unit coupled to the add-compare select unit. The branch metric unit includes a branch metric computation unit coupled to a thresholder unit. The branch metric computation unit is configured to compute a branch metric. The thresholder unit is configured to compare the branch metric with a threshold value. If the branch metric is greater than the threshold value, the thresholder unit is configured to forward the threshold value to the add-compare select and not forward the branch metric to the add-compare select unit. Implementing such a branch metric ceiling allows for a predictable reduction in the significant bits of calculations in the Viterbi decoder, which allows for reduction of complexity via elimination of gates and storage elements.

Abstract: Methods and corresponding systems in a Viterbi decoder include selecting an input symbol in an input block, wherein the input block has a plurality of input symbols, wherein each input symbol has a Boolean value, a quality value, and an associated stage, and wherein the selected symbol is selected based upon the quality value of the selected symbol relative to a quality value of other input symbols in the input block. Thereafter, the Boolean value of the selected symbol is complemented to produce a complemented symbol. The complemented symbol is substituted for the selected symbol to produce an alternate input block. A Viterbi algorithm is executed using the alternate input block to produce an alternate decoded bit sequence, which is then checked for errors using an error check. The alternate decoded bit sequence is output in response to the alternate decoded bit sequence passing the error check.

Abstract: A Viterbi decoder includes a decision generator configured to generate a full decision output. An error detector is configured to detect errors in the full decision output and generate a signal when the full decision output errors are detected.

Abstract: Techniques are provided to compute the carrier to interference-plus-noise ratio (CINR) in a wireless communication system using log-likelihood ratio (LLR) data generated from a received transmission. The LLR data are collected as they are sent from a detector to a forward error correction (FEC) decoder in a wireless communications device. In one embodiment, decision-aided LLR based CINR is computed using the decoded bits output from the FEC decoder as feedback. In another embodiment, blind LLR based CINR is computed without feedback. The CINR may be used to adjust a modulation and/or coding parameters associated with wireless communication between wireless communication devices.

Abstract: A wireless receiver detects signals generated with a multiple-input, multiple-output (MIMO) transmitter. The receiver applies maximum-likelihood detection (MLD) for soft-output signal detection, where an MLD exhaustive search across all candidate vectors is performed recursively by computing and accumulating the differences between, for example, the Euclidean metrics of consecutive candidate tests. Difference terms used for the accumulation are also calculated recursively. An ordering of candidates, such as by a triangular-waveform shaped ordering, is employed such that only one candidate variable is changed between any two consecutive candidate evaluations, leading to a reduced set of computations.

Abstract: Methods and apparatus are provided for reduced complexity Soft-Output Viterbi detection. A Soft-Output Viterbi algorithm processes a signal by determining branch metrics using a branch metrics unit; determining survivor paths for sequence detection using a first add-compare select unit; and determining survivor paths for generating one or more bit reliability values using a second add-compare select unit, wherein the first and second add-compare select units process the branch metrics determined by the branch metrics unit. The first and second add-compare select units can optionally process branch metrics having a different number of bits.

Abstract: Systems and methods are disclosed for detecting temporary high level impairments, such as noise or interference, for example, in a communications channel, and subsequently, mitigating the deleterious effects of the dynamic impairments. In one embodiment, the method not only performs dynamic characterization of channel fidelity against impairments, but also uses this dynamic characterization of the channel fidelity to adapt the receiver processing and to affect an improvement in the performance of the receiver. For example, in this embodiment, the method increases the accuracy of the estimation of the transmitted information, or similarly, increases the probability of making the correct estimates of the transmitted information, even in the presence of temporary severe levels of impairment. The channel fidelity history may also be stored and catalogued for use in, for example, future optimization of the transmit waveform.

Abstract: The present invention relates to a decoder for tail-biting convolution codes and a method thereof. The decoder receives an encoding bit sequence in a convolutional encoding method from a channel, generates an expanded encoding bit sequence, Viterbi decodes the expanded encoding bit sequence, and generates decoded data. In addition, the decoder selects a central bit sequence of the decoded data, rearranges the central bit sequence, and generates final decoded data. Accordingly, the decoder has a simplified configuration for decoding the bit sequence encoded in the tail biting convolutional encoding method, and the decoder also decodes a bit sequence encoded in a zero-tail convolutional encoding method.

Abstract: According to one embodiment, a data reproducing apparatus includes a reader, Viterbi decoder, metric difference calculator, an error correction decoder, and a detector. The reader reads data. The Viterbi decoder decodes the data read by the reader. The metric difference calculator calculates a metric difference between a maximum likelihood path and a competitive path, based on an output from the Viterbi decoder. The error correction decoder executes an error correction decoding for the output of the Viterbi decoder. The detector detects that an error detected by the error correction decoder is uncorrectable, and the metric difference detected by the metric difference calculator is larger than a predetermined value.

Abstract: Apparatus and methods are disclosed for decoding data stored on a data storage medium. A disclosed decoding method and decoder include a radial incoherence (RI) detector that increases the probability of detecting RI and improves the decoding performance in terms of the bit error rate of the decoded signal. RI is detected by comparing an input signal to the decoder against a RI threshold value and generating a RI-type signal. The RI detector may include a filter for filtering out noise and error in the RI-type signal, an adaptive threshold unit that adjusts the RI threshold value based upon the RI-type signal, a transition-based threshold unit that adjusts the RI threshold value based upon each transition in the input signal, or a path-based threshold unit that adjusts the RI threshold value based upon a best surviving path corresponding to the input signal, in combination or alone.

Abstract: A Viterbi decoder includes an early decision generator that generates an early decision output. An error detector detects errors in the early decision output and generates a signal when the early decision output errors are detected.

Abstract: Systems and methods for processing and decoding TCM/BCM-coded signal vectors. A multi-dimensional signal vector is received by, for example, a TCM or BCM decoder. The TCM/BCM decoder identifies the closest signal points in the signal constellation set, or “nearest neighbors,” for each dimension of the received signal vector. The TCM/BCM decoder then forms a test set that includes a plurality of multi-dimensional test vectors, where each dimension of each test vector is based on an identified nearest neighbor. In particular, each test point in the test set is based on a different combination of the nearest neighbors. The TCM/BCM decoder can compute branch metrics based on only the test points in the test set, and can make detection decisions using the computed branch metrics.

Abstract: One embodiment of the present invention relates to a method of monitoring impulse noise. In the method, clusters of corrupted symbols in a stream of symbols are characterized in accordance with a cluster parameter associated with the clusters. Other methods and systems are also disclosed.

Abstract: An improved Viterbi detector is disclosed in which each branch metric is calculated based on noise statistics that depend on the signal hypothesis corresponding to the branch. Also disclosed is a method of reducing the complexity of the branch metric calculations by clustering branches corresponding to signals with similar signal-dependent noise statistics. A feature of this architecture is that the branch metrics (and their corresponding square difference operators) are clustered into multiple groups, where all the members of each group draw input from a single, shared noise predictive filter corresponding to the group. In recording technologies as practiced today, physical imperfections in the representation of recorded user data in the recording medium itself are becoming the dominate source of noise in the read back data. This noise is highly dependent on what was (intended to be) written in the medium. The disclosed Viterbi detector exploits this statistical dependence of the noise on the signal.

Abstract: A reproducing device performs decoding by propagating the reliability, and detects micro medium defects to correct the reliability information. The decoder has an internal decoder, external decoder and a defect detector which calculates a moving average value of a soft-input signal, acquires a scaling factor from this, and manipulates the reliability information of the internal decoder. Since micro-defects can be detected accurately and the reliability information of the internal decoder is manipulated, error propagation due to micro defects can be suppressed.

Abstract: A sequence of cyclic redundancy check syndromes can be produced based on a received sequence of sets of parallel data wherein different ones of the sets can have respectively different parallel data widths. Some of the syndromes are produced based on respectively corresponding ones of the sets that each have a first parallel data width. At least one of the syndromes is produced based on a corresponding at least one of the sets that has a second parallel data width that is less than the first parallel data width. The last syndrome of the sequence of syndromes corresponds to all of the data in the received sequence of sets.

Abstract: A detector includes a Viterbi module that generates a first preliminary data estimate signal and a second preliminary data estimate signal based on a received data signal. A first loop generates a first error signal based on said first preliminary data estimate signal. A second loop generates a second error signal based on the second preliminary data estimate signal.

Abstract: A method and system for low-complexity implementation of a Viterbi Decoder with near optimal performance has been disclosed. The Viterbi decoding technique is diagrammatically represented as a trellis. The trellis includes various states at different time instants, and branches connecting these states. Each state has an associated state metric and a survivor path sequence, whereas each branch has a branch metric. The state metric for each current state is checked for crossing a predefined limit. If it crosses the predefined limit, the state metric is updated with a new metric that is obtained by subtracting a constant value from the state metric. Thereafter, the method finds a common path in the trellis at each state and updates the survivor path sequence of each state. The Most Significant Bits (MSBs) of the survivor path sequences of the states at a particular time instant are computed and the original data is decoded, based on the count of ‘0s’ and ‘1s’ in the MSBs.

Abstract: A method is provided for performing a MAP probability decoding of a sequence R(n) including N bits of encoded data. The method includes the steps of: (a) generating a sequence rn of sot-values by processing the sequence R(n); (b) performing a forward recursion by computing alpha values ?S,SG utilizing the soft-decision values; (c) performing a backward recursion by computing beta values ?S,SG utilizing the soft-decision values; and (d) performing an extrinsic computation by computing probability values p?k. The alpha values ?S,SG are relative log-likelihoods of an encoding process arriving at various states. The beta values ?S,SG are relative log-likelihoods of the encoding process arriving at various states. The probability values p?k represent a set of probabilities indicating that each data bit of an input sequence dK had a value equal to zero or one. The sequence R(n) represents an encoded form of the input sequence dK.

Abstract: A method and system for detecting and decoding multiple signals. A low-complexity MIMO detector that combines sphere decoding and m-algorithm approaches, while accounting for the effect of channel condition on the decoding operation, is provided. Taking into account the channel condition effectively controls the size of the search tree, and consequently the search complexity, in an adaptive manner. The channel condition is exploited in the construction of the tree to manage the number of branches in the tree and to avoid undesirable growth.

Abstract: A sequential decoding method and a decoding apparatus are provided. According to the method, an open stack is adopted for storing a plurality of paths. When the codeword generated by an internal decoder in the decoding apparatus is incorrect, a codeword is generated again by using the paths stored in the open stack. Accordingly, the complexity of decoding is reduced.

Abstract: System and methods for reducing the complexity or area of a non-linear Viterbi detector. In some embodiments, a Viterbi detector calculates branch metrics for a subset of the branches in a trellis diagram. This subset may be selected based on comparing an equalized signal with a signal level table of all the possible branches. These branch metrics may be calculated using high performance branch metric calculation techniques. The remaining branch metrics may be calculated based on the computed branch metrics using a technique that consumes fewer resources. The Viterbi detectors in the present invention may also be used in an iterative decoding scheme, where multiple detectors are cascaded. In these embodiments, a Viterbi detector may select a subset of the branches based on detection results from other Viterbi detectors.

Abstract: A majority voting Viterbi decoder includes a branch metric calculator (BMC) for measuring a difference between a received symbol and a reference symbol and outputting branch metrics from the difference; an add-compare-selection (ACS) unit for determining an optimal path using the branch metrics; a survival path memory unit for outputting decoded symbols by performing decoding based on the optimal path; and a majority voting unit for determining a final decoded symbol by performing majority voting for the decoded symbols output from the survival path memory unit. Accordingly, by adding the majority voting unit, a decoding depth can be reduced without the loss of an encoding gain required in a system, and by reducing the decoding depth, miniaturization is possible, power consumption can be reduced, and a processing delay in a memory can be minimized.

Abstract: A maximum a posteriori detector includes a single state metric engine that performs forward and backward processing to produce forward and backward state metrics. The state metric engine includes a plurality of processes that each perform both the forward and the backward processing operations. The system further includes memory that stores the forward and backward state metrics that are produced by the engine in appropriate orders for the forward and backward processing. A number of multiplexers provide the appropriate branch metrics and apriori values to adder strings in each of the processors in accordance with an associate decoding trellis.

Abstract: According to one embodiment, a maximum likelihood decoder includes a branch metric calculator, a processor configured to perform addition, comparison, and selection of an output from the branch metric calculator and a path metric memory, and outputs a selection signal for identifying a selection result, a path memory configured to store a time variation of the selection signal, and a path detection module configured to detect a decoding signal based on the time variation of the stored selection signal. A decoding method includes selecting operation modes of at least one of the branch metric calculator, the processor, and the path memory between a first operation mode in which an operation is performed at a channel rate frequency and a second operation mode in which an operation is performed at a specific frequency lower than the channel rate frequency.

Abstract: Described herein are one or more implementations of a high-throughput and memory-efficient “windowed” bidirectional Soft Output Viterbi Algorithm (BI-SOVA) decoder. The described BI-SOVA decoder uses the “window” technique to concurrently decode several different non-overlapping portions of a subject signal in parallel.

Abstract: Provided are an apparatus and method for efficiently computing a log likelihood ratio (LLR) using the maximum a posteriori (MAP) algorithm known as block combining. The method includes the steps of: calculating alpha values, beta values and gamma values of at least two time sections; calculating transition probabilities of respective states in the at least two time sections; performing a comparison operation for some of the transition probabilities to determine the highest value, selecting one of the other transition probabilities according to the determined high value, comparing the determined value with the selected value to select the higher value, and thereby obtaining the highest of the transition probabilities; and determining an operation to apply according to the highest transition probability and calculating an LLR.

Abstract: Systems and modules for use in trellis-based decoding of encoded sets of data bits. A memory system has multiple arrays for storing an index for each one of multiple states. With each array element being associated with a state through which a decoding path may pass through, the contents of each array element is an index which points to an immediately preceding state. This immediately preceding state is represented by another array element in another array. Each array is populated with array element entries as encoded data set are received by a separate decoder which generates the indices. For every given number of arrays in a group, a trace-back process traces back the path followed by an encoding procedure for encoding the encoded set. By tracing back this path through the various arrays, the original unencoded set of data bits can be found.

Abstract: In one embodiment, a signal processing receiver has a branch-metric calibration (BMC) unit that receives (i) sets of four hard-decision bits from a channel detector and (ii) a noise estimate. The BMC unit has two or more update blocks (e.g., tap-weight update and/or bias-compensation blocks) that generate updated parameters used by a branch-metric unit of the channel detector to improve channel detection. The two or more update blocks generate the updated parameters based on (i) the sets of four hard-decision bits, (ii) the noise estimate, and (iii) bandwidth values. The bandwidth values for at least two of the two or more update blocks are selected such that they are different from one another. Selecting different bandwidth values may reduce the bit-error rate for the receiver over the bit-error rate that may be achieved by selecting the bandwidth values to be the same as one another.

Abstract: A method and apparatus for the implementation of reduced state sequence estimation is disclosed, with an increased throughput using precomputation (look-ahead), with only a linear increase in hardware complexity with respect to the look-ahead depth. The present invention limits the increase in hardware complexity by taking advantage of past decisions (or survivor symbols). The critical path of a conventional RSSE implementation is broken up into at least two smaller critical paths using pipeline registers. Various reduced state sequence estimation implementations are disclosed that employ one-step or multiple-step look-ahead techniques to process a signal received from a dispersive channel having a channel memory.

Abstract: A chip architectural core is described for use in decoding one or more vectors received by the core in accordance with one or more recursive and/or non-recursive systematic trellis codes of varying sizes and constraints K, as well as generator polynomials. The core comprises: a decoder including (a) a reconfigurable network of ACS blocks, BMU generators and trace-back mechanisms for both recursive and non-recursive systematic forms, and (b) reconfigurable connections between the ACS blocks, BMU generators and trace-back mechanisms, arranged so that the precise number of network components can be continuously rearranged and interconnected in a network as a function of size and the constraint K and generator polynomial of each code used for encoding the vectors received by the core.