Abstract: A first serializing stage is provided with a stream of data words composed of sub-words that each have values that associate each of the sub-words with the same error detection code value. For example, the values selected for each sub-word may each be associated with even parity. One or more serializing stages time-multiplex the sub-words into a stream of sub-word sized data. At the serializing stage that receives sub-word sized data stream, the data is checked to determine whether any of the sub-words is no longer associated with the error detection code value. Serializing/deserializing stages are selectively controlled to replace one or more data bits from a word being serialized/deserialized with an error detecting code value (e.g., parity). A subsequent serializing/deserializing stage is enabled to use the inserted error detecting code values and the data in the received words to determine whether an error has occurred.

Abstract: The present disclosure relates to a method and an apparatus for map reduce. In some embodiments, an exemplary processing unit includes: a 2-dimensional (2D) processing element (PE) array comprising a plurality of PEs, each PE comprising a first input and a second input, the first inputs of the PEs in a linear array in a first dimension of the PE array being connected in series and the second inputs of the PEs in a linear array in a second dimension of the PE array being connected in parallel, each PE being configured to perform an operation on data from the first input or second input; and a plurality of reduce tree units, each reduce tree unit being coupled with the PEs in a linear array in the first dimension or the second dimension of the PE array and configured to perform a first reduction operation.

Abstract: A first serializing stage is provided with a stream of data words composed of sub-words that each have values that associate each of the sub-words with the same error detection code value. For example, the values selected for each sub-word may each be associated with even parity. One or more serializing stages time-multiplex the sub-words into a stream of sub-word sized data. At the serializing stage that receives sub-word sized data stream, the data is checked to determine whether any of the sub-words is no longer associated with the error detection code value. Serializing/deserializing stages are selectively controlled to replace one or more data bits from a word being serialized/deserialized with an error detecting code value (e.g., parity). A subsequent serializing/deserializing stage is enabled to use the inserted error detecting code values and the data in the received words to determine whether an error has occurred.

Abstract: A semiconductor device includes a data storage suitable for storing a training data for a training operation, a data bus inversion (DBI) calculator suitable for calculating DBI information for the training data input from the data storage through global transmission lines, generating a DBI flag signal based on the DBI information and outputting a DBI data, which is the training data inverted according to the DBI flag signal, in response to a DBI signal, a first multiplexer suitable for selectively outputting the training data input from the data storage through the global transmission lines or the DBI data to a first channel in response to a training signal and the DBI signal and a second multiplexer suitable for selectively outputting the training data input from the data storage through the global transmission lines or the DBI flag signal to a second channel.

Abstract: A method includes destructively reading bits of a spin torque magnetic random access memory, using error correcting code (ECC) for error correction, and storing inverted or non-inverted data in data-store latches. When a subsequent write operation changes the state of data-store latches, parity calculation and majority detection of the bits are initiated. A majority bit detection and potential inversion of write data minimizes the number of write current pulses. A subsequent write operation received within a specified time or before an original write operation is commenced will cause the majority detection operation to abort.

Abstract: The present invention provides a write circuit, a read circuit, a memory buffer and a memory module. The write circuit includes: a data collecting unit, a first check unit, a data restoring unit, a first check data generating unit, a first adjusting unit and a write unit; the read circuit includes: a data read unit, a second check unit, an output data generating unit, a second check data generating unit, a second adjusting unit and an output unit; the memory buffer includes the write circuit and the read circuit; the memory module includes the memory buffer and multiple memory chips connected to the memory buffer.

Abstract: An error correction method and system includes an Encoder and Syndrome-generator that operate in parallel to reduce the amount of circuitry used to compute check symbols and syndromes for error correcting codes. The system and method computes the contributions to the syndromes and check symbols 1 bit at a time instead of 1 symbol at a time. As a result, the even syndromes can be computed as powers of the odd syndromes. Further, the system assigns symbol addresses so that there are, for an example GF(28) which has 72 symbols, three (3) blocks of addresses which differ by a cube root of unity to allow the data symbols to be combined for reducing size and complexity of odd syndrome circuits. Further, the implementation circuit for generating check symbols is derived from syndrome circuit using the inverse of the part of the syndrome matrix for check locations.

Abstract: A method of feedback in a wireless transmit receive unit includes providing a precoding matrix index (PMI), error checking the (PMI) to produce an error check (EC) bit, coding the PMI and the EC bit and transmitting the coded PMI and EC bit.

Abstract: According to one embodiment, a storage device includes an error detector, a check module, and a replacement module. The error detector detects a bit error that occurs in entry data related to conversion to a physical address corresponding to a logical address based on an error detecting code assigned to the entry data. The check module checks, based on data obtained by inverting one bit among all bits of the entry data and on data read out from the physical address indicated by the obtained data, whether or not the obtained data is normal entry data. The replacement module replaces the entry data where the bit error is detected with the checked normal entry data.

Abstract: Systems and methods are provided for enhancing the performance and throughput of a low-density parity check (LDPC) decoder. In some embodiments, the enhanced performance and throughput may be achieved by detecting and correcting near-codewords before the decoder iterates up to a predetermined number of iterations. In some embodiments, a corrector runs concurrently with the decoder to correct a near-codeword when the near-codeword is detected. In alternate embodiments, the corrector is active while the decoder is not active. Both embodiments allow for on-the-fly codeword error corrections that improve the performance (e.g., reducing the number of errors) without decreasing the throughput of the decoder.

Abstract: A transmitting apparatus for transmitting user data, includes: an establishing section that establishes three or more transmission paths for a receiving apparatus; a first generation section that generates a user data unit which includes user data to be transmitted to the receiving apparatus; and a second generation section that generates an error correction data unit which includes error correction data to be used for error correction of the user data to be transmitted to the receiving apparatus. At least one of the three or more transmission paths transmits the error correction data unit, and at least two of the three or more transmission paths transmits the user data unit.

Abstract: A decoding apparatus for performing decoding processing of encoded data by using non-binary LDPC codes, includes: a logarithmic Fourier transform processing section, a variable node processing section, an edge coefficient processing section, and a check node processing section, wherein the logarithmic Fourier transform processing section performs Fourier transform processing and logarithmization processing on a probability vector of a symbol of an encoded frame data to output an initial value of logarithmic Fourier domain probability vector, and the variable node processing section, the edge coefficient processing section, and the check node processing section perform iteration processing by using a logarithmic Fourier domain probability vector.

Abstract: A memory system is provided. The memory system includes a memory element that is configured to selectively output data stored to and data fetched from the memory element. An error checking station is configured to receive the data stored to and the data fetched from the memory element. The error checking station is further configured to perform error checking on the data.

Abstract: The apparatus for appending CRC to the data or signaling to be transmitted in the communication systems is proposed in present invention. If the length of the CRC-bit sequence is 16, one of the CRC generation polynomials listed in present invention can be adopted. If the length of the CRC bit sequence is 18, one of the CRC generation polynomials listed in present invention can be adopted. If the length of the CRC bit sequence is 20, one of the CRC generation polynomials listed in present invention can be adopted. With the optimized CRC generation polynomials proposed in present invention, mistakes in signaling detection can be effectively reduced so that system spectrum utility can be improved.

Abstract: A plurality of information bits are encoded using a parity-check matrix that is equivalent to a modular code matrix. The modular code matrix is a diagonal sub-matrix structure immediately above a connection layer that includes a plurality of diverse connection layer sub-matrices, all but at most one of which are below corresponding diagonal matrix structure sub-matrices. The information bits are assembled with a plurality of parity bits produced by the encoding to provide a codeword that is exported to a medium. Preferably, all the diagonal matrix structure sub-matrices are identical. Preferably, some of the parity bits are computed using only diagonal matrix structure sub-matrices.

Abstract: A method and system for error management in a memory device. In one embodiment of the invention, the memory device can handle commands and address parity errors and cyclic redundancy check errors. In one embodiment of the invention, the memory can detect whether a received command has any parity errors by determining whether the command bits or the address bits of the received command has any parity errors. If a parity error or cyclic redundancy check error in the received command is detected, an error handling mechanism is triggered to recover from the errant command.

Abstract: A teletext decoder is provided which is suitable for decoding a packet of teletext signal to generate a teletext. The teletext decoder includes an error judgment device for judging the accuracy of a plurality of sliced bits, and correcting an error occurrence bit in the sliced bits on the basis of a plurality of sampling points and a slicer level when the plurality of sliced bits are incorrect.

Abstract: The present invention discloses a coding method, a coding device, a decoding method and a decoding device for low density generator matrix codes.

Abstract: Systems and methods are provided for enhancing the performance and throughput of a low-density parity check (LDPC) decoder. In some embodiments, the enhanced performance and throughput may be achieved by detecting and correcting near-codewords before the decoder iterates up to a predetermined number of iterations. In some embodiments, a corrector runs concurrently with the decoder to correct a near-codeword when the near-codeword is detected. In alternate embodiments, the corrector is active while the decoder is not active. Both embodiments allow for on-the-fly codeword error corrections that improve the performance (e.g., reducing the number of errors) without decreasing the throughput of the decoder.

Abstract: An advanced memory having improved performance, reduced power and increased reliability. A memory device includes a memory array, a receiver for receiving a command and associated data, error control coding circuitry for performing error control checking on the received command, and data masking circuitry for preventing the associated data from being written to the memory array in response to the error control coding circuitry detecting an error in the received command. Another memory device includes a programmable preamble. Another memory device includes a fast exit self-refresh mode. Another memory device includes auto refresh function that is controlled by the characteristic device. Another memory device includes an auto refresh function that is controlled by a characteristic of the memory device.

Abstract: Embodiments of an invention for verifying firmware using system memory error check logic are disclosed. In one embodiment, an apparatus includes an execution core, firmware, error check logic, non-volatile memory, comparison logic, and security logic. The error check logic is to generate, for each line of firmware, an error check value. The comparison logic is to compare stored error check values from the non-volatile memory with generated error check values from the error check logic. The security logic is to prevent the execution core from executing the firmware if the comparison logic detects a mismatch between the stored error code values and the generated error code values.

Abstract: To control operations of a resistive memory device, an input-output operation of an error check and correction (ECC) code is separated from an input-output operation of data. A condition of the input-output operation of the ECC code is determined stricter than a condition of the input-output operation of the data. reliability of the input-output operation of the ECC code may be enhanced, thereby reducing errors due to defect memory cells, noise, etc.

Abstract: Embodiments of a broadcast receiver and method for optimizing a scale factor in a log-likelihood ratio (LLR) mapper are generally described herein. In some embodiments, the broadcast receiver includes an LLR mapper to generate LLRs from demodulated data samples, a low-density parity-check (LDPC) decoder to generate decoded data from the LLRs, and an LLR optimizer to dynamically select a scale factor for the LLR mapper based on a number of iterations for convergence of the LDPC decoder. In some embodiments, the LLR optimizer iteratively revises the scale factor during receipt of broadcast signals until the number of iterations of the iterative decoder is either minimized for convergence or minimized for convergence failures.

Abstract: In order to correct errors of a first page on one plane in a two-plane NAND flash memory, use data of a second page on another plane to mix the encoding and leverage the error correction code of the first page. Each of the error correction codes of the first page and the second page is divided into an inner correction code and a cross correction code. The inner correction codes are used to correct errors of their own pages and the cross correction codes are used to correct errors of two distinct groups, grouped from the even and odd bytes of the two pages respectively. The second page, with fewer errors, is therefore used to enhance the correcting ability of the first page, without lengthening the error correction code of the first page.

Abstract: A method of feedback in a wireless transmit receive unit includes providing a precoding matrix index (PMI), error checking the (PMI) to produce an error check (EC) bit, coding the PMI and the EC bit and transmitting the coded PMI and EC bit.

Abstract: A parity checking circuit which includes a microprocessor, instruction memory, a parity checker, an address capture device, a data bus connected to the microprocessor, the instruction memory and the parity checker, and an address bus connected to the microprocessor, the instruction memory and the address capture device. The instruction memory sends a parity bit to the parity checker, and the parity checker compare an address it receives from the address bus to the parity bit it receives from the instruction memory. If a parity error is detected, an error signal is sent to the address capture device and the address capture device captures the address for subsequent storage in a storage device, such as flash memory. The circuit also includes registers and a watchdog reset device which facilitates a system level reset at the command of the microprocessor.

Abstract: A data recovery circuit for recovering data from a parity error without entirely rewriting the data. A write circuit is connected to memory regions including an actual data region and a copy region. A first parity generation circuit writes actual data with even parity to the actual data region. A second parity generation circuit writes backup data of the actual data with odd parity to the copy region. A read circuit reads data from the actual data region and the copy region. An even parity checker detects a parity error in the actual data based on the data read from the actual data region. An odd parity checker checks whether the data read from the copy region is backup data.

Abstract: Data that are stored in cells of a multi-bit-per cell memory, according to a systematic or non-systematic ECC, are read and corrected (systematic ECC) or recovered (non-systematic ECC) in accordance with estimated probabilities that one or more of the read bits are erroneous. In one method of the present invention, the estimates are a priori. In another method of the present invention, the estimates are based only on aspects of the read bits that include significances or bit pages of the read bits. In a third method of the present invention, the estimates are based only on values of the read bits. Not all the estimates are equal.

Abstract: An embedded DRAM ECC architecture for purging data errors. The embedded DRAM ECC architecture is based upon a two-dimensional linear parity scheme, and includes a plurality of memory blocks and a parity block. Each memory block includes additional columns for storing row parity bits, and the parity block stores column parity bits. A row parity circuit coupled in parallel to an existing local databus of each memory checks the parity of the local databus bits against a row parity bit during a refresh or read operation to identify parity failure. Identification of the incorrect bit of the word is achieved by iteratively transferring the data of the local databus of each memory block onto an existing global databus, and checking the parity across the global databus with a column parity circuit. When global databus parity failure is detected, all bits of the global databus are inverted to purge the incorrect bit from the memory block via the local databus.

Abstract: Semiconductor devices, a system including said semiconductor devices and methods thereof are provided. An example semiconductor device may receive data scheduled for transmission, scramble an order of bits within the received data, the scrambled order arranged in accordance with a given pseudo-random sequence. The received data may be balanced such that a difference between a first number of the bits within the received data equal to a first logic level and a second number of bits within the received data equal to a second logic level is below a threshold. The balanced and scrambled received data may then be transmitted. The example semiconductor device may perform the scrambling and balancing operations in any order. Likewise, on a receiving end, another semiconductor device may decode the original data by unscrambling and unbalancing the transmitted data. The unscrambling and unbalancing operations may be performed in an order based upon the order in which the transmitted data is scrambled and balanced.

Abstract: A method and apparatus for transmitting control information of a small block size with high reliability in a mobile communication system supporting uplink packet data service are provided. A 6-bit Absolute Grant indicating an allowed maximum data rate for uplink packet data transmission is generated and a 16-bit User Equipment Identifier Cyclic Redundancy Check is generated by combining a Cyclic Redundancy Check with a User Equipment Identifier. The User Equipment Identifier specific Cyclic Redundancy Check and 8 tail bits are added to the 6-bit Absolute Grant and the added bits are encoded at a coding rate of 1/3. The resulting 90 coded bits are rate-matched according to a predetermined rate matching pattern and transmitted to a User Equipment. The rate matching pattern is {1, 2, 5, 6, 7, 11, 12, 14, 15, 17, 23, 24, 31, 37, 44, 47, 61, 63, 64, 71, 72, 75, 77, 80, 83, 84, 85, 87, 88, 90}.

Abstract: The invention provides a channel coding method for encoding systematic data for transmission in a communication channel. The systematic data has a runlength constraint. In the method, data words are permuted. Error codes are generated based upon the permuted data words. The error codes are appended to original data words to form channel input for serial transmission in the communication channel. The number of error code bits is limited to ensure the channel input meets the runlength constraint. The error code can be a parity check bit.

Abstract: The invention includes a method and apparatus for aligning a plurality of data channels using a deskew bitstream. The method includes receiving the deskew bitstream, identifying an aligned deskew frame by processing the deskew bitstream, identifying a data channel alignment position associated with each of the plurality of data channels by comparing a deskew channel comparison bit from the aligned deskew frame to a data channel comparison bit from each of the plurality of data channels, and selecting the plurality of data channel alignment positions associated with the respective plurality of data channels for aligning the plurality of data channels. The plurality of data channels are aligned in a manner for substantially reducing skew associated with the data channels. The deskew bitstream comprises a plurality of data bits associated with the data channels and a plurality of parity bits generated using at least a portion of the data bits.

Abstract: Methods and apparatus for performing error correction code (ECC) coding techniques for high-speed implementations. The ECC code word is structured to facilitate a very fast single-error-detect (SED) that allows state machines to be stopped within a single cycle when an error is detected and enables a corresponding single-error-correct (SEC) operation to be performed over multiple cycles while the state machines are in a suspended mode.

Abstract: A burst error-correcting capability is largely improved. At least the even-number row and at least the odd-number row of the data block which is a set of data sectors are separated. An outer parity is created for each column and an inner parity is created for each row. Then, the outer parity is scattered with respect to each of the sectors of the data block to be interleaved.

Abstract: A burst error-correcting capability is largely improved. At least the even-number row and at least the odd-number row of the data block which is a set of data sectors are separated. An outer parity is created for each column and an inner parity is created for each row. Then, the outer parity is scattered with respect to each of the sectors of the data block to be interleaved.

Abstract: A storage system for storing data on a storage medium includes an encoder, a linear block encoder, a write circuit, a read circuit, a channel decoder, and a soft linear block code decoder. In a first iteration, the channel decoder decodes data read by the read circuit. In succeeding iterations, the channel decoder decodes the data read by the read circuit and utilizes information decoded by the soft linear block decoder from an immediately preceding iteration. The storage system includes a threshold check circuit to select (i) an output of the soft linear block code decoder if the number of parity-check violations has a first relationship with respect to a threshold, or (ii) an output of the channel decoder if the number of violations has a second relationship with respect to the threshold. The storage system includes a decoder to decode an output of the threshold check circuit.

Abstract: A dynamic parity distribution system and technique distributes parity across disks of an array. The dynamic parity distribution system includes a storage operating system that integrates a file system with a RAID system. In response to a request to store (write) data on the array, the file system determines which disks contain free blocks in a next allocated stripe of the array. There may be multiple blocks within the stripe that do not contain file system data (i.e., unallocated data blocks) and that could potentially store parity. One or more of those unallocated data blocks can be assigned to store parity, arbitrarily. According to the dynamic parity distribution technique, the file system determines which blocks hold parity each time there is a write request to the stripe. The technique alternately allows the RAID system to assign a block to contain parity when each stripe is written.

Abstract: A method uses an outer code that is a concatenation of code words generated by a parity check encoder. The outer code word is permuted by an interleaver. The high rate coding provides good performance with a simple structure. A parity check bit is generated for each data word of received systematic dates. Code words are formed by adding a generated parity bit to each data word. Groups of code words are permuted to form encoded input for transmission in a communication channel. The invention further includes encoding to maintain a runlength-limiting (RLL) constraint at the channel input. Interleaved runlength encoded system data is used to generate error code bits. Insertion of error code bits in the system data at the channel input is controlled. This guarantees that the channel input stream comprised of the runlength-limited system data and inserted error code bits meets the runlength constraints.

Abstract: Embodiments of the present invention are implemented in memory systems. In one embodiment, the memory comprises an array of memory cells and a control circuit. The control circuit is configured to read error correction coded data from the array of memory cells, provide error correction code decoding to selected error correction coded data and discard unused error correction code parity data of unselected error correction coded data.

Abstract: A simplified Viterbi detector for maximum likelihood detection of nine-bit QPSK symbols, employing a difference metric and two comparators, instead of using two state metrics and four comparators. The detector is used to process the outputs of synchronously sampled matched filters. A multiplexer is employed to select the difference metric from amongst the input sample, the fed back value of the difference metric itself, or the inverses of either, depending on decision signals output from the comparators, which in turn compare the difference metric with the input sample and it's inverse. The even path history then represents the most likely value of the detected symbol.

Abstract: Systems and methods for encoding and decoding serial bit streams are provided. A parity bit is computed for each nibble, with the parity alternating between odd and even in a regular manner for normal data, and with parity having predetermined different patterns to indicate the start of a packet or the end of a packet. Special code words indicate the idle state and an error state. In some systems an extra vertical parity channel is provided in association with a group of data channels, the vertical parity channel effectively providing a protection channel.

Abstract: A method uses an outer code that is a concatenation of code words generated by a parity check encoder. The outer code word is permuted by an interleaver. The high rate coding provides good performance with a simple structure. An odd parity check bit is generated for each data word of received systematic dates. Code words are formed by adding a generated parity bit to each data word. Groups of code words are permuted to form encoded input for transmission in a communication channel. The invention further includes encoding to maintain a runlength-limiting (RLL) constraint at the channel input. Interleaved runlength encoded system data is used to generate error code bits. Insertion of error code bits in the system data at the channel input is controlled. This guarantees that the channel input stream comprised of the runlength-limited system data and inserted error code bits meets the runlength constraints.

Abstract: Systems and methods for encoding and decoding serial bit streams are provided. A parity bit is computed for each nibble, with the parity alternating between odd and even in a regular manner for normal data, and with parity having predetermined different patterns to indicate the start of a packet or the end of a packet. Special code words indicate the idle state and an error state. In some systems an extra vertical parity channel is provided in association with a group of data channels, the vertical parity channel effectively providing a protection channel.

Abstract: The present invention relates to a coding system characterized by various combinations of the following properties: 1) Even parity at the output of d of the precoder; 2) A coding rate of 32/34; 3) At least 9 ones per codeword; 4) No more than 13 consecutive zeros in the stream of encoded data (G=13); 5) No more than 13 consecutive zeros in any run of every-other-bit in the stream of codewords (I=13); 6) For closed error events in y or y′ having squared-distance≦(1 to 1.5)×dmfb2 in the detector, the decoder produces at most 4 corresponding erroneous data bytes; 7) Decoding of a 34 bit codeword may begin when 19 of its bits have been received; 8) If the Viterbi detector 108 outputs Non-Return to Zero (NRZ) symbols, then its output is filtered by (1⊕D{circumflex over ( )}2) before being decoded, but if the Viterbi detector outputs NRZ Inverter (NRZI) symbols, then its output is decoded directly; and 9) The even parity is on NRZ symbols.

Abstract: Systems and methods for encoding and decoding serial bit streams are provided. A parity bit is computed for each nibble, with the parity alternating between odd and even in a regular manner for normal data, and with parity having predetermined different patterns to indicate the start of a packet or the end of a packet. Special code words indicate the idle state and an error state. In some systems an extra vertical parity channel is provided in association with a group of data channels, the vertical parity channel effectively providing a protection channel.

Abstract: A method and apparatus for detecting an error rate of a data stream. The data stream is divided into a sequence of blocks, and a detection interval is defined including a predetermined number of blocks in the sequence. For one or more of the blocks in the detection interval, respective error measures are computed responsive to the error rate of the data stream. The one or more blocks in the detection interval are classified as good or bad blocks by comparing the respective error measures to a first threshold. It is estimated that an error condition exists in the data stream by comparing a count of the bad blocks in the interval to a second threshold.

Abstract: The present invention pertains to a distance-enhancing coding method that can be applied to digital recording and digital communications. It improves the time-varying maximum transition run method used in a conventional distance-enhancing coding to avoid main error events ±(1,−1) from happening. Under the premise of maintaining a code gain of 1.8 dB, the code rate can be increased from ¾ to ⅘. The invention also provides a method of using an enumeration algorithm and an exhaustive method to search for block codes for distance-enhancing coding, which can find required codes by following specific steps.

Abstract: A method and system for providing parity protection to data. The method and system includes transmitting pairs of groups of bits. Each one of the groups of bits has bits representing the data and a parity bit. The parity sense of one of the pair of groups of bits is opposite to the parity sense of the other one of the pair of groups of bits. The transmitted pair of groups of bits are received. The received pair of groups of bits are parity checked to determine whether the parity sense of one of the received pair of groups, of bits is opposite to the parity sense of the other one of the received pair of groups of bits. With such an arrangement, a failure in the data driver or data receiver which causes the output of all bits produced by such driver to assume the same logic state can be detected because the received pair of groups of bits will have, with such failure, the same parity sense. The method and system also includes transmitting successive groups of bits in response to clock pulses.

Abstract: In a method for encoding payload bits for transmission over communications link, data and control information are assembled into n-bit data words, where n is an even number and words for control information are constrained to have zero disparity (equal numbers of binary zero and one digits). The n-bit data words are then encoded into n+2-bit code words by adding a two-bit label; for words carrying control information the label has a value of 10. For other data words the disparity is evaluated; if it is zero, the label bits are 01; if the disparity is non-zero and opposite in sense to the running digital sum of the code words transmitted already, the label bits are 11; otherwise, the data word is inverted, and the label bits are 00.