Even And Odd Parity Patents (Class 714/802)
  • Patent number: 6388587
    Abstract: A data storage channel encoder includes a data word input, a code word output and an encoder. The encoder is coupled between the data word input and the code word output and is adapted to encode successive data words received on the data word input into successive code words on the code word output according to a selected code having combined maximum transition run and parity constraints. The maximum transition run constraint constrains the successive code words such that, when the successive code words are concatenated to form an encoded bit stream, the encoded bit stream has a maximum of one consecutive transition beginning at either odd or even indexed bit positions in the encoded bit stream and a maximum of two consecutive transitions beginning at the other of the odd or even indexed bit positions.
    Type: Grant
    Filed: December 31, 1999
    Date of Patent: May 14, 2002
    Assignee: Seagate Technology LLC
    Inventors: Barrett J. Brickner, Pradeep R. Padukone
  • Patent number: 6374389
    Abstract: Disclosed is a solid state disk emulator system for significantly improving access time, i.e., improving both the seek time and the rotational latency. An error correction process is incorporated in the disk emulator which corrects single bit hard memory errors using only a single parity bit. The error correction process corrects single bit hard errors in a stored digital data word of “n” bits according to the following steps. The process generates a parity bit for the n-bit word according to a predetermined algorithm prior to storing the word. The process then stores the digital data word in a selected storage location and also stores the parity bit. The process retrieves the stored n-bit word from the selected storage location. The process also retrieves the stored parity bit for the n-bit word. Then, the process generates a new parity bit for the retrieved word according to the predetermined algorithm. The new parity bit is compared with the retrieved parity bit.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: April 16, 2002
    Assignee: Solid Data Systems, Inc
    Inventors: George B. Tuma, Wade B. Tuma, Robert E. Warne
  • Patent number: 6282685
    Abstract: A communications system for communicating a serial bit stream and parity is disclosed which enables the use of the parity bit for signaling between the transmitter and receiver by selectively inducing parity errors. The system includes a first parity generator used to generate a first parity bit on the data to be communicated. The first parity and the data are transmitted in a communications medium by a data transmitter to a data receiver. A second parity generator generates a second parity bit using the communicated data. A comparator then compares the first parity bit with the second parity bit and a parser parses the received data in response to the comparison.
    Type: Grant
    Filed: November 20, 1997
    Date of Patent: August 28, 2001
    Assignee: Ericsson Inc.
    Inventors: Jack S. Petty, David Rand Irvin
  • Patent number: 6145114
    Abstract: The invention comprises an enhancement to max-log-APP processing that significantly reduces performance degradation associated with introducing the "max" approximation into log-APP computations, while still maintaining lower computational complexity associated with max-log-APP processing. This enhancement is achieved by adjusting extrinsic information produced by a max-log-APP process where the magnitude of the extrinsic information is reduced, for example, by multiplying it with a scale factor between 0 and 1.
    Type: Grant
    Filed: August 14, 1998
    Date of Patent: November 7, 2000
    Assignee: Her Majesty the Queen in right of Canada, as represented by the Minister of Industry through Communications Research Centre
    Inventors: Stewart Crozier, Andrew Hunt, John Lodge