Abstract: A third secure computing apparatus generates data Wb associated with each bit b of a segment t that satisfies a relation mA=s*t for a first input value mA and an operator * and data W(1-b) associated with an inversion bit (1-b) of the bit b, transmits the data Wb to a first secure computing apparatus, and transmits data W including the data Wb and the data W(1-b) to a second secure computing apparatus. The second secure computing apparatus uses a segment s that satisfies the relation mA=s*t, a logic circuit function f and the data W to generate data T in which a logic circuit function f(s*X), which is the logic circuit function fin which the segment s is substituted, is concealed, and transmits the data T to the first secure computing apparatus. A computation result f(mA) can be determined from the data T and the data Wb. The first secure computing apparatus obtains the computation result f(mA) using the data T and the data Wb.

Abstract: A decoding apparatus has an on-chip buffer, an external buffer interface, and a turbo decoder. The on-chip buffer is arranged for buffering each code block to be decoded. The external buffer interface is arranged for accessing an off-chip buffer. The turbo decoder is arranged for decoding a specific code block read from the on-chip buffer. The specific code block is not transmitted from the on-chip buffer to the off-chip buffer via the external buffer interface unless decoding fail of the specific code block is identified.

Abstract: A communication system having a main control portion (MCP) to transmit information destined to a device n cascade levels down, and create an error detection code (CRC code) for data that contains a count of remaining cascade levels until an n-th cascade level and the information. The code is transmitted to an upstream sub-control portion (USCP) with the data. The USCP creates a CRC code for the data, and compares the created and received codes. For a match, the USCP determines whether the information is destined to itself based on the remaining cascade level count. When the information is not so destined, the USCP creates new data with the remaining cascade level count reduced by 1, and a CRC code for the new data, and transmits the created code to a further device, with the new data.

Abstract: Systems and method relating generally to data processing, and more particularly to systems and methods for utilizing multiple data streams for data recovery from a storage device. In some cases the systems include a low density parity check data decoder circuit including at least a first data decoder engine and a second data decoder engine each electrically coupled to a common circuit. The common circuit is operable to: shift a combination of both a first sub-message from the first data decoder engine and the second sub-message from the second data decoder engine to yield an shifted output, and disaggregate the shifted output to yield a third sub-message to the first data decoder engine and a fourth sub-message to the second decoder engine.

Abstract: A method of feedback in a wireless transmit receive unit includes providing a precoding matrix index (PMI), error checking the (PMI) to produce an error check (EC) bit, coding the PMI and the EC bit and transmitting the coded PMI and EC bit.

Abstract: A method of feedback in a wireless transmit receive unit includes providing a precoding matrix index (PMI), error checking the (PMI) to produce an error check (EC) bit, coding the PMI and the EC bit and transmitting the coded PMI and EC bit.

Abstract: A transmitting apparatus for transmitting user data, includes: an establishing section that establishes three or more transmission paths for a receiving apparatus; a first generation section that generates a user data unit which includes user data to be transmitted to the receiving apparatus; and a second generation section that generates an error correction data unit which includes error correction data to be used for error correction of the user data to be transmitted to the receiving apparatus. At least one of the three or more transmission paths transmits the error correction data unit, and at least two of the three or more transmission paths transmits the user data unit.

Abstract: Failing bus lane detection using syndrome analysis, including a method for receiving a plurality of syndromes of an error detection code, the error detection code associated with a plurality of frames that have been transmitted on a bus that includes a plurality of lanes and is protected by the error detection code. The method includes performing for each of the lanes in each of the syndromes: decoding the syndrome under an assumption that the lane is a failing lane, the decoding outputting a decode result; determining if the decode result is a valid decode; and voting for the lane in response to determining that the decode result is a valid decode. A failing lane is then identified in response to the voting, with the failing lane being characterized by having more votes than at least one other lane on the bus.

Abstract: A method for computing a X-bit cyclical redundancy check (CRC-X) frame value for a data frame transmitted over a N-bit databus is provided. The method includes receiving a N-bit data input with an end-of-frame for the data frame at bit position M on the N-bit databus, performing a bitwise XOR on X most significant bits of the N-bit data input with a CRC-X feedback value to form a first N-bit intermediate data. The method also includes shifting the first N-bit intermediate data by M bit positions to align the end-of-frame of the data frame with a least significant bit (LSB), and padding M number of zero bits to a most significant bit (MSB) of the first N-bit intermediate data to form a second N-bit intermediate data.

Abstract: A method performed by an I/O unit connected to another I/O unit in a network device. The method includes receiving a packet; segmenting the packet into a group of data blocks; storing the group of data blocks in a data memory; generating data protection information for a data block of the group of data blocks; creating a control block for the data block; storing, in a control memory, a group of data items for the control block, the group of data items including information associated with a location, of the data block, within the data memory and the data protection information for the data block; performing a data integrity check on the data block, using the data protection information, to determine whether the data block contains a data error; and outputting the data block when the data integrity check indicates that the data block does not contain a data error.

Abstract: A simulator is partitioned into a functional component and a behavior prediction component and the components are executed in parallel. The execution path of the functional component is used to drive the behavior prediction component and the behavior prediction component changes the execution path of the functional component.

Abstract: A method for activating a semi-persistent scheduled (SPS) resource using a user agent (UA) is presented. A downlink (DL) communication may be received by a UA using a physical downlink control channel (PDCCH). The DL communication may include a control message. When the control message is associated with an SPS Cell-Radio Network Terminal Identifier (C-RNTI) of the UA, the method may include retrieving a value of a New Data Indicator (NDI) field. When the value of the NDI field is equal to 0, the method may include inspecting the control message to determine whether the control message indicates an SPS activation. When the control message indicates an SPS activation, the method may include activating an SPS resource identified by the control message.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for reliability, availability, and serviceability solutions for memory technology. In some embodiments, a host determines the configuration of the memory subsystem during initialization. The host selects a write cyclic redundancy code (CRC) mechanism and a read CRC mechanism based, at least in part, on the configuration of the memory subsystem. Other embodiments are described and claimed.

Abstract: In one embodiment, circuitry is provided to generate a residue based at least in part upon operations and a data stream generated based at least in part upon a packet. The operations may include at least one iteration of at least one reduction operation including (a) multiplying a first value with at least one portion of the data stream, and (b) producing a reduction by adding at least one other portion of the data stream to a result of the multiplying. The operations may include at least one other reduction operation including (c) producing another result by multiplying with a second value at least one portion of another stream based at least in part upon the reduction, (d) producing a third value by adding at least one other portion of the another stream to the another result, and (e) producing the residue by performing a Barrett reduction based at least in part upon the third value.

Abstract: Embodiments of an invention for verifying firmware using system memory error check logic are disclosed. In one embodiment, an apparatus includes an execution core, firmware, error check logic, non-volatile memory, comparison logic, and security logic. The error check logic is to generate, for each line of firmware, an error check value. The comparison logic is to compare stored error check values from the non-volatile memory with generated error check values from the error check logic. The security logic is to prevent the execution core from executing the firmware if the comparison logic detects a mismatch between the stored error code values and the generated error code values.

Abstract: Input data (1A) having an integral multiple of 8 bits is divided into symbols in units of b bits (b is an integer of 5 to 7) in a register file 10, an error detecting code is added in an error detection calculation circuit 20, and then encoding (such as Reed Solomon (RS) encoding) having an error correction capability of two or more symbols is performed in a parity calculation circuit 30 to record the data in a storage 40. In the reproduction, error correction in units of symbols is performed to reproduced data from the storage 40 in an error correction circuit 70, error detection processing is performed in an error detection calculation circuit 80, and then data having the integral multiple of 8 bits is recovered in a register file 90 to output the same. By this means, it is possible to provide a storage system with high reliability to a soft error that occurs in a storage such as semiconductor memory.

Abstract: A method of feedback in a wireless transmit receive unit includes providing a precoding matrix index (PMI), error checking the (PMI) to produce an error check (EC) bit, coding the PMI and the EC bit and transmitting the coded PMI and EC bit.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for reliability, availability, and serviceability solutions for memory technology. In some embodiments, a host determines the configuration of the memory subsystem during initialization. The host selects a write cyclic redundancy code (CRC) mechanism and a read CRC mechanism based, at least in part, on the configuration of the memory subsystem. Other embodiments are described and claimed.

Abstract: A decoding apparatus includes a decoder register for receiving data having a codeword including null data bits, and decoding the received data while shifting Bit Under Decoding (BUD) by one bit. A connection unit outputs a check result by applying a predetermined check equation to the data output from the decoder register. A majority logic unit for determines if an error is detected according to the check result output from the connection unit, and outputs the determination result. An error information unit determines if there is an error in the received data and if there is an uncorrectable error in the decoded data.

Abstract: A data processing method includes the steps of: initializing a syndrome vector to be an (n?1)th symbol; finding a corresponding mask based on the syndrome vector, wherein the mask is zero when the (n?1)th symbol is zero; correcting a known constant, which is zero when the syndrome vector is zero, based on the mask; inputting the syndrome vector to a log look-up table to correspondingly find log data; performing a modulo addition operation corresponding to log maximum data to find a log sum based on the log data and a log known constant; and inputting the log sum to an anti-log look-up table to correspondingly find operational data.

Abstract: A method, transceiver, and computer program storage product transfer data over fiber between a first transceiver and a second transceiver. The second transceiver is determined to support a high integrity cyclic redundancy check associated with substantially an entire data set in a Fiber Channel Protocol exchange between the first transceiver and the second transceiver. A last data frame in a plurality of data frames is formatted for communication to the second transceiver during the Fiber Channel Protocol exchange. The last data frame includes a plurality of data and at least one cyclic redundancy check field associated with the plurality data and at least one additional cyclic redundancy check field associated with the plurality of data frames.

Abstract: An apparatus generally having a lookup table and a circuit is disclosed. The lookup table may be configured to store a plurality of results including remainders of divisions by a particular polynomial. The circuit may be configured to (i) parse a first polynomial into a plurality of data blocks and an end block, (ii) fetch a plurality of results from the lookup table by indexing the lookup table with each of the data blocks and (iii) generate a second polynomial by adding the results fetched from the lookup table to the end block. The second polynomial generally has a second degree that is lower that a first degree of the first polynomial.

Abstract: This disclosure relates to method, device and system for detecting errors in a communication system. A signal is received from a transmitter at a receiver wherein the signal includes a data portion and a result of a hash function. The hash function is computed in part from a transmitter identification code. The receiver determines if the result of the hash function matches both the data portion and the transmitter identification code. The receiver discards the signal if the result of the hash function does not match both the data portion and the transmitter identification code of the transmitter.

Abstract: Aspects of a method and system are provided for error detection for improving data integrity in protocol offloading. Aspects of the invention may enable receiving a block of data having a modulo-based input error detection code and an error correction term appended thereto, calculating an output error detection code of the block, combining the input error detection code and the error correction term to produce a modified error detection code, and comparing the calculated error detection code to the modified error detection code so as to detect an error in the block. The error correction term may be equal to a binary difference between the input error detection code and the output error detection code. The input error detection code and the error correction term may be combined by applying an XOR operation.

Abstract: A method of discovering a fault in a circuit is disclosed. The method comprises generating a first result of a selected function by performing the selected function on an operand, wherein the selected function employs a mask. Once the function is performed, an antimask of the mask is created, and the modulo of the antimask is calculated. A modulo function of the first result of the selected function is calculated to obtain a third result. A modulo of the operand is then calculated to obtain a fourth result, and a second function is then performed on the second result and the third result to obtain a fifth result. In response to comparing the fifth result to the fourth result, a signal is propagated to indicate a fault in the circuit.

Abstract: A non-transitory computer readable medium includes a computer program, which when executed by a processor performs a method, the method including processing a data message to extract segments of data and computing a checksum by applying gray code conversions to one or more of the data segments, wherein only one bit changes on each count when consecutive integers are represented as bits. The method further includes extracting remaining data segments and adding bitwise to the previously calculated gray code checksum to provide the next checksum, converting the next checksum to gray code, and adding a final gray code conversion to a final data message including all remaining data segments and transmitting the final data message.

Abstract: A system and method provides extended convolutional coding for packets/frames or superframes used in wireless transmission. A wireless system has an extended convolutional encoder/decoder, a wireless network, a server having an extended convolutional encoding/decoding module, one or more clients, at least one of which performs extended convolutional encoding/decoding; and a wireless transmission unit for the server and one or more clients to communicate via the wireless network. A method for providing the extended convolutional encoding includes the steps of retrieving a set of codes from a database that has a maximal-minimal free distance within a certain range; selecting a subset of the retrieved codes that have the smallest number of paths at the maximal-minimal free distance; and finding extended convolutional codes by selecting a code having a certain rate from the subset of codes that have the smallest number of paths at increased free distances to provide the best candidates.

Abstract: A method and apparatus is disclosed wherein a user equipment (UE) receives control information on a first channel and uses the control information to process a second channel.

Abstract: A system and method for self-test of an integrated circuit are disclosed. As one example, an integrated circuit is disclosed. The integrated circuit includes a digital signal processing chain, a random sequence generator coupled to an input of the digital signal processing chain, and a checksum calculator coupled to an output of the digital signal processing chain.

Abstract: In one embodiment, circuitry is provided to generate a residue based at least in part upon operations and a data stream generated based at least in part upon a packet. The operations may include at least one iteration of at least one reduction operation including (a) multiplying a first value with at least one portion of the data stream, and (b) producing a reduction by adding at least one other portion of the data stream to a result of the multiplying. The operations may include at least one other reduction operation including (c) producing another result by multiplying with a second value at least one portion of another stream based at least in part upon the reduction, (d) producing a third value by adding at least one other portion of the another stream to the another result, and (e) producing the residue by performing a Barrett reduction based at least in part upon the third value.

Abstract: A method to design parallel TH precoders and a circuit architecture to implement parallel TH precoders have been presented. The parallel design relies on the fact that a TH precoder can be viewed as an IIR filter with an input equal to the sum of the original input to the TH precoder and a compensation signal. The parallel design also relies on the fact that the compensation signal has finite levels. Therefore, precomputation techniques can be applied to calculate intermediate signal values for all possible values of the compensation signal.

Abstract: A semiconductor integrated circuit has a cell array, a redundancy cell capable of replacing a defective cell, a redundancy control circuit, a plurality of first fuses, a plurality of second fuses, a plurality of third fuses, a first shift register configured to hold states of the plurality of first fuses, a second shift register configured to be connected in cascade to the first shift register and to hold states of the plurality of second fuses, a third shift register configured to be connected to the first and second shift registers in cascade and to hold states of the plurality of third fuses, a CRC remainder calculator configured to sequentially input information held by the first to third shift registers to a CRC generating equation to calculate a remainder obtained by division, and a CRC determination part that outputs information indicative of whether the first to third fuses are correctly programmed.

Abstract: In one aspect, circuitry to determine a modular remainder with respect to a polynomial of a message comprised of a series of segment. In another aspect, circuitry to access at least a portion of a first number having a first endian format, determine a second number based on a bit reflection and shift of a third number having an endian format opposite to that of the first endian format, and perform a polynomial multiplication of the first number and the at least a portion of the first number.

Abstract: Techniques are disclosed to limit short-term correlations associated with outputs of stream cipher keystream generators. Output values of a generator are paired such that the paired outputs are sufficiently far apart to be considered independent. In one described implementation, a method includes sequentially storing a plurality of results provided by a stream cipher output rule in a first, second, and third storage units. A pairing function pairs individual values from the first and third storage units that are at least a threshold value apart. Upon reaching the threshold value of the output rule results, the contents of the first, second, and third storage units are rotated serially.

Abstract: Provided are codes that may be applied to a sheet of paper or other surface, as well as techniques for decoding such codes. Using such codes and decoding techniques permits identification of the position of a pen (e.g., a digital pen) on the paper or other surface, by observing only a small field of the surface. Moreover, the position often can be identified even in the presence of arbitrary rotation and certain errors (e.g., due to dust or stray markings on the paper).

Abstract: A method for storing streaming media data packets in a cache includes receiving a first streaming media data packet from a streaming media server, the first streaming media data packet comprising first header data and first payload data, pre-determining a first payload checksum in response to at least a portion of the first payload data, storing at least a portion of the first header data and the first payload checksum as first packet meta data in a first data object in the cache memory, and storing the first payload data in the first data object in the cache memory, wherein the first data object is directly addressable in the cache memory via an associated object handle.

Abstract: A method of discovering a fault in a circuit is disclosed. The method comprises generating a first result of a selected function by performing the selected function on an operand, wherein the selected function employs a mask. Once the function is performed, an antimask of the mask is created, and the modulo of the antimask is calculated. A modulo function of the first result of the selected function is calculated to obtain a third result. A modulo of the operand is then calculated to obtain a fourth result, and a second function is then performed on the second result and the third result to obtain a fifth result. In response to comparing the fifth result to the fourth result, a signal is propagated to indicate a fault in the circuit.

Abstract: An circuit arrangement and method for reducing the number of processing loops needed to generate an error correction parameter used in the Montgomery method. An initial input to a processing loop is set to a value equal to the modulus, left shifted one register position. Values of the working register are shifted multiple positions during a single loop iteration, and a shifted result is subtracted and compared to zero to determine subsequent contents of the working register.

Abstract: A non-iterative technique for calculating the remainder of modulo division, which requires significantly fewer operations than the traditional iterative technique for the same calculation. The number of calculations required in the present invention is independent of the number of bits of the divisor in the modulo operation. Two requirements of the non-iterative technique are that the value of the divisor D should be equal to 2n?1 (where n is the number of bits of the divisor D) and the value of the dividend N should be less than or equal to (D?1)2, but greater than or equal to zero. If these two conditions are met, the remainder R of N mod D is determined by summing the upper n 2 and lower n 2 bits of the dividend N.

Abstract: Cyclic redundancy codes are obtained to verify the integrity of a message transmitted between a sender and a receiver. One method for obtaining a cyclic redundancy code includes separating the message into segments. Remainders are obtained for those segments based on a generator polynomial. The remainders for those segments are multiplied by a segment-constant to obtain segment-remainders for each segment. The segment-remainders are accumulated into an accumulated-remainder. The accumulated-remainder is moduloed by the generator polynomial to obtain a remainder for the accumulated-remainder. The remainder for the accumulated-remainder is the cyclic redundancy code for the message.

Abstract: A method for performing CRC calculations on packets with dynamic headers is disclosed. The header may be changed during transmission across a network. When the header is changed, a CRC associated with the header is recalculated such that a residue of the initial seed value is always obtained. A final CRC covers the entire packet including the header and its header CRC, or just the data portion of the packet. The final CRC remains valid and unchanged during transmission of the packet, allowing an endpoint along the network to confirm the validity of the entire packet. By only changing the CRC associated with the changed portion of the packet (the header CRC), the introduction of errors during transmission of the packet is minimized.

Abstract: Received data is provided to a pipelined network in which a one's complement checksum is computed. The computed checksum is stored in a register. In further embodiments, at least one intermediate result in the pipelined network is stored in at least one corresponding register. Other embodiments include determining whether the digital data to be included in the checksum is odd or even based on a number of valid bytes, and selectively swapping bytes in the pipelined checksum network based on whether the digital data is determined to be odd or even. In some embodiments, the received digital data is masked to selectively choose received digital data to be included in the checksum.

Abstract: In packet communications that employ header compression/decompression, the computational complexity of checksum generation can be reduced by re-using static checksum information associated with header bits that do not change from header to header. The static checksum information can be used together with information about header bits that do change from header to header, in order to generate a desired checksum. The checksum can then be used to verify a reconstructed header produced from a compressed header by a header decompressor.

Abstract: A procedure for determining an absolute position of an object, which includes scanning a code pattern from a series of code patterns, wherein each code pattern of said series of code patterns unambiguously defines one absolute position and comprises a plurality of code elements. Forming a code word with a plurality of bits by the scanning the code pattern. Checking the plurality of bits of the code word for reliability, and if one of said plurality of bits fails to attain predetermined criteria, it is assigned an error code. Predetermining a series of bit strings, with one absolute position being unambiguously assigned to each one of the series of bit strings. Comparing the bits of the code word with the predetermined series of bit strings, and if a match of all of the bits of the code word and the predetermined series of bits strings occurs, assigning a corresponding absolute position to the code word, and upon comparison for a match, any bits assigned an error code are not taken into account.

Abstract: Multi-dimensional packet recovery systems and methods that permit recovery of lost packets and packets containing transmission errors that are transmitted over a network. The packet recovery systems and methods transmit a multi-dimensional array comprising rows, columns and hyperdimensional volumes of data packets between a source node and one or more destination nodes.

Abstract: A process is provided for monitoring the conversion of numerical values from a first to a second format, where before and after the conversion, the modulo residue of the corresponding numerical value is calculated and compared with the corresponding residue after the conversion. In this way it is possible to effect error-free monitoring of such a conversion, especially of computer data, without great hardware expenditure.

Abstract: Received data is provided to a pipelined network in which a one's complement checksum is computed. The computed checksum is stored in a register. In further embodiments, at least one intermediate result in the pipelined network is stored in at least one corresponding register. Other embodiments include determining whether the digital data to be included in the checksum is odd or even based on a number of valid bytes, and selectively swapping bytes in the pipelined checksum network based on whether the digital data is determined to be odd or even. In some embodiments, the received digital data is masked to selectively choose received digital data to be included in the checksum.

Abstract: A method of determining an offset, modulo n, of at least one point with respect to a sequence 50 of at least n symbols, the sequence consisting of a repeating codeword of a cyclic position code, the cyclic position code having length n and minimum distance dmin, the method including: obtaining, from the sequence 50 and at a position corresponding to the at least one point, a subsequence 52 of length w symbols, where w≧n−dmin+1; mapping the subsequence 52 to a codeword 58 of the cyclic position code most likely to match the subsequence in the presence of symbol errors 60, 62 in the subsequence; and determining an offset 54, in the sequence 50, of the codeword 58 thus obtained, and thereby determining the offset of the at least one point.

Abstract: In an error generating circuit and method for generating a 10-bit error character to test 8B/10B decoders, a character generator receives a two-state mode control signal and a two-state disparity control signal and generates a 10-bit error character of a type dependent upon the states of the disparity control signal and the mode control signal. The four types of error characters that can be generated are an invalid 10-bit character having positive disparity, an invalid 10-bit character having negative disparity, a valid 10-bit character having positive disparity, and a valid 10-bit character having negative disparity. A test circuit incorporates the error generating circuit and an 8-bit/10-bit encoder and provides a valid 10-bit character or an 10-bit error character, depending upon the state of an enable signal.

Abstract: A CRC generation unit includes a number of CRC calculation assemblies to be selectively employed to incrementally calculate a CRC value for a first sequence of N data bytes. The calculation is iteratively performed, one iteration at a time. Further, the selection of the CRC calculation assemblies is made in accordance with the group size of each of a number of data word groups of the N data bytes. In one embodiment, the CRC calculation assemblies include a first assembly for incrementally calculate the CRC value for an iteration, whenever the group size is n/2 bytes or less for the iteration, and a second assembly for incrementally calculate the CRC value for an iteration, whenever the group size is more than n/2 bytes for the iteration. In one embodiment, the CRC generation unit is a shared resource to multiple network traffic flow processing units of a network traffic routing IC.