Abstract: A method by which a terminal receives downlink data in a wireless communication system is disclosed. Particularly, the method comprises: receiving information related to downlink data transmitted during a specific time period; receiving downlink control information (DCI) on the basis of the information related to the downlink data; and receiving the downlink data on the basis of the DCI.

Abstract: A method for receiving a signal by a terminal in a wireless communication system according to an embodiment of the present invention can comprise a step for determining REGs, which are to be assumed that the same precoding is used, among REGs comprised in a control resource set on the basis of information relating to precoder granularity, and thus monitoring a control channel candidate. Particularly, if a part of resource blocks overlaps another resource region and particular resource blocks in the resource blocks are no longer contiguous due to the overlapping, the terminal can comprise an assumption that the same precoding is used with respect to the REGs comprised in the particular resource blocks even if the information relating to the precoder granularity corresponds to first configuration.

Abstract: An intelligent electronic device (IED) of an electric power delivery system includes processing circuitry a memory that includes instructions. The instructions, when executed by the processing circuitry, are configured to cause the processing circuitry to receive first data via parallel redundancy protocol (PRP), generate a first integrity check value using a media access control security (MACsec) integrity check function based on the first data, receive second data via PRP, generate a second integrity check value using the MACsec integrity function based on the second data, compare the first integrity check value and the second integrity check value with one another, and output a notification in response to determining that the first integrity check value and the second integrity check value do not match one another.

Abstract: A memory control method, a memory storage device and a memory control circuit unit are provided. The method includes: determining a retry threshold value according to decoding history information which includes information related to at least one first decoding operation previously performed; and determining whether to enter a second decoding mode according to the retry threshold value after at least one second decoding operation performed based on a first decoding mode is failed. A decoding ability of the second decoding mode is higher than a decoding ability of the first decoding mode.

Abstract: This application discloses a data transmission method, apparatus, and system. The method includes: generating a to-be-sent bit sequence, where the to-be-sent bit sequence includes one or more bits in a bit sequence having a length of (N?M), where N is a length of a mother code for polar encoding, M is a length of encoded bits obtained after rate matching is performed on a bit sequence having a length of N, N is m raised to the power of an integer, m is a positive integer greater than 1, M is a positive integer, and N>M; and sending the generated bit sequence. A corresponding apparatus and system are further disclosed. In this application, in this data transmission solution, an additional coding gain is generated during decoding, so that a decoding FER is reduced, and decoding performance is improved.

Abstract: A wireless network interface device selects a guard interval from a set of guard intervals including a first guard interval, a second guard interval, and a third guard interval. The first guard interval has a length that is different than a length of the second guard interval and a length of the third guard interval, and the length of the second guard interval is different than the length of the third guard interval. The wireless network interface device generates a preamble of a data unit to include: a legacy signal field, a repetition of the legacy field, and a non-legacy field that includes a field that indicates the selected guard interval. The wireless network interface device generates a data portion of the data unit, including generating orthogonal frequency division multiplexing (OFDM) symbols of the data portion using the selected guard interval.

Abstract: Examples of the present disclosure provide apparatuses and methods for error code calculation. The apparatus can include an array of memory cells that are coupled to sense lines. The apparatus can include a controller configured to control a sensing circuitry, that is coupled to the sense lines, to perform a number of operations without transferring data via an input/output (I/O) lines. The sensing circuitry can be controlled to calculate an error code for data stored in the array of memory cells and compare the error code with an initial error code for the data to determine whether the data has been modified.

Abstract: Disclosed are a method for transmitting a sidelink signal encoded on the basis of a polar code, by a terminal in a wireless communication system supporting a sidelink according to various embodiments, and a device therefor. Disclosed are a method for transmitting a sidelink signal encoded on the basis of a polar code and a device therefor, the method comprising the steps of: mapping, to bit indices of a polar code, information bits of input information including information on a plurality of fields; encoding the mapped information bits on the basis of the polar code; and transmitting a sidelink signal including the encoded information bits, wherein information bits corresponding to a particular field among the plurality of fields are mapped to a bit index lower than a bit index to which the information bits corresponding to the remaining fields are mapped.

Abstract: A method for receiving a signal by a terminal in a wireless communication system according to an embodiment of the present invention can comprise a step for determining REGs, which are to be assumed that the same precoding is used, among REGs comprised in a control resource set on the basis of information relating to precoder granularity, and thus monitoring a control channel candidate. Particularly, if a part of resource blocks overlaps another resource region and particular resource blocks in the resource blocks are no longer contiguous due to the overlapping, the terminal can comprise an assumption that the same precoding is used with respect to the REGs comprised in the particular resource blocks even if the information relating to the precoder granularity corresponds to first configuration.

Abstract: Disclosed in the present invention are a data transmission method and a network device. The method comprises: sending first information to a second network device, the first information being used to assist the second network device to determine whether to perform early sending of called data targeting a terminal.

Abstract: The disclosure relates to a method and system for memory testing to detect memory errors during operation of a memory module. Example embodiments include a method of detecting an error in a memory module (101), the method comprising the sequential steps of: i) receiving (302) a request from a processor executing an application for a read or write operation at a location of the memory module (101) identified by an address; ii) outputting data (304) from, or writing to, the location of the memory module (101); iii) generating (306) by an error detection module (102) a further read request for the location of the memory module (101) identified by the address; iv) receiving (307) at the error detection module (102) an error correction code from the memory module (101) for the location identified by the address; and vi) providing (311) by the error detection module (102) an alert output for the address if the error correction code indicates an error.

Abstract: A linear driving system for LED with high power factor including a rectifying circuit receiving an AC voltage and generating a DC voltage to a power supply bus having a protection circuit coupled thereto. The protection circuit includes a detection unit for acquiring a voltage signal based on a power supply bus voltage, and to generate a detection result which indicates undesirable oscillation on the power supply bus voltage. A control unit includes a delay control module connected with the detection unit, and is coupled to the detection unit and for generating a control signal based on the detection result. The delay control module is for outputting a first control signal when undesirable oscillation happens, and outputting a second control signal after a protection period when undesirable oscillation disappears. A switch circuit controlled by the first control signal and the second control signal turns off for the protection period.

Abstract: An apparatus of user equipment (UE) includes processing circuitry coupled to a memory, where to configure the UE for Ultra-Reliable Low-Latency Communication (URLLC) in a New Radio (NR) network, the processing circuitry is to decode higher layer signaling indicating a UE-specific DL SPS configuration. The DL SPS configuration including a periodicity of control information communication and a number of DL data repetitions for a transport block. A DCI format received via a PDCCH based on the periodicity in the DL SPS configuration is decoded. Multiple PDSCH slot allocations are detected in the DCI format using the number of DL data repetitions. DL data received via the PDSCH within the multiple PDSCH slot allocations is decoded.

Abstract: In one aspect, a computer-implemented method includes detecting, by a server includes one or more processors, a request to perform a hash join operation on a data structure stored in a data storage device, forming a hash lookup dictionary based on lookup results in a hash table, storing the hash lookup dictionary in a cache, and probing, during a probing phase of the hash join operation, the cache.

Abstract: Provided are a Cyclic Redundancy Check (CRC) circuit, and a method and an apparatus thereof, a chip and an electronic device, which belong to the technical field of computers. Herein, the cyclic redundancy check circuit may include: a configuration module configured to acquire configuration information and an information field, a CRC arbitration module configured to determine a generator polynomial according to the configuration information, a CRC control module configured to respond to triggering of the CRC arbitration module and output a clock signal, a coefficient corresponding to each power in the generator polynomial and the information field, a parallel iteration module configured to respond to the clock signal and implement parallel iteration for the information field according to the coefficient corresponding to the each power in the generator polynomial, as to output an iteration result, and a CRC output module configured to package the information field according to the iteration result.

Abstract: Data symbols in an input signal are detected with a slicer of a DFE of a transceiver device. An output of a feedback filter of the DFE is generated, during a particular clock cycle, based on a first set of one or more data symbols detected during first one or more previous clock cycles and a second set of one or more data symbols detected during second one or more previous clock cycles. The second set is separated from the first set by a third set of one or more data symbols detected during third one or more clock cycles that occur after the first one or more clock cycles and before the second one or more clock cycles, where the output is generated without use of the third set of symbols. The output is subtracted from the input signal to generate an equalized input to the slicer.

Abstract: In a memory controller included in a memory system for processing a program operation fail, the memory controller controls a plurality of memory devices commonly coupled to a channel, the plurality of memory devices respectively performing preset program operations, and includes: a buffer memory for storing data to be stored in the plurality of memory devices, based on a buffer memory index; and a program error processor for acquiring fail data corresponding to a program operation fail from a fail memory device and acquiring reprogram data that is data to be stored together with the fail data, based on the buffer memory index.

Abstract: This disclosure provides systems, methods and apparatuses, including computer programs encoded on computer storage media, for ranging procedures performed using antenna switching. In one aspect, a device initiating a ranging procedure may transmit a ranging request, which may include antenna switching capabilities of the initiating device, a request for antenna switching by a responding device during the ranging procedure, or both. Ranging signaling may be communicated between the initiating device and the responding device using different transmit antennas, receive antennas, or both. In some implementations, ranging messages transmitted by the responding device may include transmit antenna indices used for transmission of different ranging messages, and receive antenna indices used for reception of different ranging response messages.

Abstract: A redundant bit generating device that generates redundant bits for error detection, that are added to a block of information bits, includes: a redundant bit calculation function that generates a predetermined number of redundant bits from the information bits according to a CRC polynomial; and a bit interleaving function that dispersedly arranges the predetermined number of redundant bits within the information bits using a permutation pattern determined based on the CRC polynomial.

Abstract: The application provides a channel encoding method, an encoding apparatus, and a system. A bit sequence X1N is output by using X1N=D1NFN, where D1N is a bit sequence obtained after an input bit sequence u1N is encoded based on locations of K to-be-encoded information bits in an encoding diagram that has a mother code length of N, u1N is a bit sequence obtained based on the K to-be-encoded information bits, and FN is a Kronecker product of log2 N matrices F2. A design considers that the locations of the K to-be-encoded information bits in the encoding diagram that has a mother code length of N include a row location index set H of the information bits in the encoding diagram and a layer location index set M of the information bits in the encoding diagram, where 0?H?N, and 0<M?logm N?1.

Abstract: A communication system includes a transmission-side processing device, and a reception-side processing device, the transmission-side processing device and the reception-side processing device communicate using a plurality of communication lines, wherein the transmission-side processing device concurrently transmits the same telegraphic messages via each of the plurality of communication lines, and the reception-side processing device is capable of concurrently receiving telegraphic messages via each of the plurality of communication lines, and when a same telegraphic message as a previously received telegraphic message is received later, invalidates the same telegraphic message received later while processing the previously received telegraphic message.

Abstract: Examples of the present disclosure provide apparatuses and methods for error code calculation. The apparatus can include an array of memory cells that are coupled to sense lines. The apparatus can include a controller configured to control a sensing circuitry, that is coupled to the sense lines, to perform a number of operations without transferring data via an input/output (I/O) lines. The sensing circuitry can be controlled to calculate an error code for data stored in the array of memory cells and compare the error code with an initial error code for the data to determine whether the data has been modified.

Abstract: A technique of protecting data in a data storage system includes, in response to receiving a write request that specifies data to be written in the data storage system, calculating an error detection code (EDC) of the specified data. The technique further includes persisting the specified data and the EDC in persistent cache and, in response to receiving a read request for reading the specified data, validating the specified data using the EDC before returning the specified data in satisfaction of the read request.

Abstract: Techniques for calculation of CRC values for very large Ethernet packets in a quick manner are disclosed. Portions of CRC values are calculated each frame and are combined to arrive at a final CRC value for the frame. The CRC values for each frame are also combined to arrive at the final value for the packet. The use of the zero-wheeling function allows for each CRC value calculation to be a calculation of a limited set of data (e.g., one chunk of a frame), which allows such calculations to be completed quickly.

Abstract: This application provides an encoding method and apparatus in a wireless communications system. The method includes: performing cyclic redundancy check (CRC) encoding on A to-be-encoded information bits based on a CRC polynomial, to obtain a first bit sequence, where the first bit sequence includes L CRC bits and the A information bits; and performing polar encoding on the first bit sequence, where L has a value of one of 3, 4, 5, 8, and 16. Based on an improved CRC polynomial, coding satisfying a false alarm rate (FAR) requirement is implemented.

Abstract: Embodiments are described for performing online migration of backup appliances in automated and monitored process from a backup application. The data migration process uses certain Mtree replication methods. It is configured to provide capabilities a backup application server would control, such as Mtree replication configuration from the backup application, a policy driven approach for data center migration, and accommodation of specific customer data recovery needs, and providing a choice to end users for leveraging both Managed File Replication and Mtree replication based on the customer data movement requirements. Such a solution is configured to be generic and applicable to any data protection applications with a policy driven implementation that leverages certain integration points of the system.

Abstract: The present teaching relates to method, system, medium, and implementations for storage management. A hash table is constructed, having an index file having one or more slots, each of which includes one or more buckets. Each bucket stores one or more types of records, including a direct record, an indirect record, and a forwarding record. A direct record stores data directly in a bucket of a slot of the index file. When a storage request is received related to some relevant data, the request is handled based on the constructed hash table.

Abstract: A polar code transmission method and apparatus, the method including performing, by a transmit end, polar code encoding on at least one of to-be-encoded bit sequences U to generate an encoded sequence, wherein a length of U is N, and scrambling and interleaving, by the transmit end, the encoded sequence by using a scrambling sequence SX and an interleaving matrix PX.

Abstract: Techniques for efficient communication packet generation in internet of things (IOT) include presenting an application programming interface to each of a plurality of protocols in a plurality of different layers of a network communications protocol stack. A single packet buffer is configured in memory to hold headers for all of the plurality of protocols for a packet directed to a first destination node. Pointers are also stored in memory to tables maintained by the plurality of protocols. In response to receiving input at the application programming interface from a first protocol, at least one bit is updated in the single packet buffer based on the input and on data in a table maintained by a different second protocol of the plurality of protocols.

Abstract: Embodiments provide a data transmission method and a related device. Under the method, after determining a first data packet to be sent to a receive end, a transmit end may generate a second data packet based on the first data packet, encode the second data packet, and send an encoded second data packet. A length of the second data packet is greater than a length of the first data packet. In various embodiments, when sending a data packet to the receive end, the transmit end may generate a longer data packet from a shorter data packet through combination, and send the longer data packet to the receive end after channel coding. In this way, a relatively high channel coding gain can be obtained during data transmission, and a relatively high bit error rate of short packet transmission is avoided, so that data transmission reliability can be improved.

Abstract: A checksum negotiation unit selects as a candidate polynomial, a candidate for a generator polynomial to be used in communication between a safety master device and a safety slave device from a plurality of polynomials. A communication cycle verification unit determines whether or not a calculation using the candidate polynomial is completed in each of the safety master device and the safety slave device by a predetermined deadline. The communication cycle verification unit designates the candidate polynomial as the generator polynomial when it is determined that the calculation using the candidate polynomial is completed in each of the safety master device and the safety slave device by the deadline.

Abstract: In a wireless communication system, a transmission device inputs, in some of N input bit positions of a polar code having the size N, input bits including D-bit information and X-bit user equipment (UE) ID according to a predetermined bit allocation sequence. The transmission device encodes the input bits by using the polar code. The transmission device transmits an encoded output sequence.

Abstract: A semiconductor device includes an error detection circuit configured to generate fixed data by fixing any one of a first group and a second group included in internal data to a preset level based on a burst chop signal and an internal command address in response to a read command, and generate an error detection signal by detecting an error of the fixed data; and a data output circuit configured to generate latch data by latching the internal data based on a first latch output control signal, and generate output data by serializing the latch data and the error detection signal based on a second latch output control signal.

Abstract: The application relates to methods and devices for use in a receiver circuit (200) configured to receive data in transport blocks where each transport block comprises a set of individually decodable code blocks is provided. The receiver circuit comprises a decoder (102) for decoding the received data and at least one on-chip FIFO memory (210). The receiver circuit also comprises a Layer 2 decipher unit (104), and a buffer memory (106). In the receiver circuit, a controller (220) is provided. The decoder is configured to store a correctly decoded code block in the at least one on-chip FIFO memory, and when a code block of a transport block is incorrectly decoded, store any subsequent correctly decoded code block of the same transport block in the buffer memory. Hereby an efficient receiver circuit that can be implemented using a small on-chip memory is provided.

Abstract: A synchronization method and apparatus, for verifying whether data cached by a base station and data cached by a terminal are synchronized. In embodiments of the present invention, a transmitting device and a receiving device generate cache check values on the basis of a predetermined acquisition mode; the receiving device compares the cache check values, and according to the comparison result, determines whether a decompression cache area and a compression cache area are synchronized. According to the present invention, a transmitting device and a receiving device sample some data from a data cache area by means of the same acquisition mode to generate cache check values, and the receiving device compares the cache check values, and according to the comparison result, determines whether the decompression cache area and the compression cache area are synchronized.

Abstract: Methods, systems, and devices for wireless communications are described. A user equipment (UE) may determine to decode or refrain from decoding a transport block (TB) transmitted from a base station based on a decodability condition. The decodability condition may include whether an effective UE throughput for decoding the TB is greater than a predetermined decoding throughput threshold or not. If the effective UE throughput is greater than the predetermined decoding throughput threshold, the UE may refrain from decoding the TB. In some cases, the TB may be a subsequent transmission from the base station based on an initial transmission not being correctly decoded, and the UE may refrain from decoding the subsequent transmission.

Abstract: Embodiments of the present invention provide a control information transmission method and apparatus. The control information transmission method includes: determining, by a network device, N pieces of to-be-jointly-coded downlink control information DCI, where N is an integer greater than or equal to 2; coding, by the network device, the N pieces of DCI in a polar coding manner, to obtain one codeword; and mapping, by the network device, the codeword to a time-frequency resource of a downlink control channel for sending. According to the embodiments of the present invention, not only a relatively high coding gain can be obtained, but a relatively low average processing latency on a decoder side can also be obtained.

Abstract: According to certain embodiments, a method by a transmitter is provided for adaptively generating precoder bits for a Polar code. The method includes acquiring at least one configuration parameter upon which a total number of precoder bits depends. The at least one configuration parameter comprising at least one of an information block length K, a code block length N, and/or a code rate R=K/N. The total number of precoder bits is determined, and the precoder bits for a code block are generated according to the determined total number of precoder bits. The precoder bits are placed within the code block.

Abstract: A method for authentication is disclosed. The method may be implemented by a terminal device. The method may comprise generating, by a starting unit of the terminal device, process information of a process of the terminal device before starting the process, transmitting, by the starting unit, the process information to an authentication proxy of the terminal device, requesting, by the process, the authentication proxy to authenticate the process after the process is started, obtaining, by the authentication proxy and from system resources of the terminal device, process information corresponding to the process, and determining, by the authentication proxy, that the process is legal if the obtained process information is the same as the process information transmitted to the authentication proxy.

Abstract: A communication method used by a terminal apparatus includes the step of separately generating first coded bits fk of a transport block, second coded bits q0 of control information, and third coded bits q1 of a rank indicator, and multiplexing the first coded bits fk and the second coded bits q0 to generate multiplexed bits gk, and the step of multiplexing the multiplexed bits gk and the third coded bits q1 to generate a first sequence hk, wherein the position where the third coded bits q1 are mapped is given at least based on a part of a first condition, a second condition, and a third condition, the first condition is whether a search space detecting the PDCCH is a CSS or a USS, the second condition is which RNTI is used to scramble CRC parity bits attached to the DCI format, and the third condition is whether the first method or the second method is used for the first coded bits.

Abstract: A method for receiving a signal by a terminal in a wireless communication system according to an embodiment of the present invention can comprise a step for determining REGs, which are to be assumed that the same precoding is used, among REGs comprised in a control resource set on the basis of information relating to precoder granularity, and thus monitoring a control channel candidate. Particularly, if a part of resource blocks overlaps another resource region and particular resource blocks in the resource blocks are no longer contiguous due to the overlapping, the terminal can comprise an assumption that the same precoding is used with respect to the REGs comprised in the particular resource blocks even if the information relating to the precoder granularity corresponds to first configuration.

Abstract: A bit assignment estimating device that accurately estimates bit assignment of a payload with fewer division patterns is provided. The bit assignment estimating device: divides a payload of received communication data to generate a plurality of blocks; estimates bit assignment of a block to be a certain value type; concatenates a block, which is adjacent to either of a block or a concatenation block which is estimated to be the continuous value type at a higher-order bit side, to the block or the concatenation block which is estimated to be the continuous value type when the block adjacent is estimated to be the status value type or the continuous value type; estimates whether the concatenation block is the continuous value type or not; and separates an immediately-close-concatenated block from a corresponding concatenation block when the concatenation block is estimated not to be the continuous value type.

Abstract: A data processing method and apparatus, a server, and a controller, where the method includes receiving, by a server, a data processing request, where the data processing request includes a request sequence number, and the request sequence number marks the data processing request, generating at least one input/output (I/O) request according to the data processing request, adding the request sequence number to each of the at least one I/O request, merging the I/O requests having the request sequence number, and generating an aggregation instruction when a quantity of I/O requests having the request sequence number is greater than a preset threshold, and sending the aggregation instruction to a controller of a storage system. Hence, a time taken to perform monitoring and management using a transaction mechanism can be reduced, thereby simplifying the transaction mechanism.

Abstract: An example operation may include one or more of receiving a request to modify a governance policy of a blockchain, identifying a principal identity that controls the governance policy, determining an allowable combination of signatures of the principal identity required for modifying the governance policy based on a graph data structure storing signature policies for endorsing modifications to governance policies, and modifying the governance policy of the blockchain based on the request in response to an allowable combination of signatures being received.

Abstract: A semiconductor device includes a read control circuit configured to generate first and second output control signals including pulses which are selectively generated, from first and second strobe signals depending on burst information; and a data output circuit configured to latch first internal data depending on the pulse of the first output control signal, transfer second internal data at a time when the second output control signal level-transitions, and generate output data from the latched first internal data and the transferred second internal data.

Abstract: Systems, methods, and instrumentalities may be provided for an infrastructure node to transmit and a wireless transmit/receive unit (WTRU) or a group of WTRUs to receive a first downlink control information (DCI) a second DCI. The first DCI may carry time critical DCI, whereas the second DCI may carry non-time critical DCI. Each of the first DCI and the second DCI may be polar encoded. The second DCI may be polar encoded may be received with an embedded first DCI as part of frozen bits. The second DCI may be mapped to a plurality of bit channels having higher reliability than the plurality of bit channels to which the embedded first DCI is mapped. The WTRU may discard the decoded first DCI, if decoding of the DCI using the embedded first DCI is not successful.

Abstract: A communication device for handling a code block group (CBG)-based communication operation comprises at least one storage device; and at least one processing circuit, coupled to the at least one storage device. The at least one storage device stores, and the at least one processing circuit is configured to execute instructions of receiving an indication configuring at least one CBG-based communication operation to the communication device from a network; receiving a maximum number of CBGs in a transport block (TB) for the at least one CBG-based communication operation from the network; and performing the at least one CBG-based communication operation with the network according to the maximum number of CBGs.

Abstract: The invention relates to a method for displaying a notification for a user in which first image data associated with the notification is displayed on a display unit in a normal display mode. The method also includes displaying second image data associated with the notification on the display unit in a safety display mode as soon as a predetermined fault condition is satisfied in the normal display mode. The predetermined fault condition being satisfied is checked by comparing a current display of the first image data by the display unit in the normal display mode, with respect to a presence of image faults, with a reference display of the first image data by the display unit in the normal display mode. The current display and the reference display are subdivided into regions and/or pixels for the comparison, said regions and/or pixels being associated with classes as background, foreground, image edge and/or irrelevant.

Abstract: A terminal apparatus includes a coding unit configured to divide a transport block into one or more code blocks and generate coded bit(s) by coding the one or more code blocks; and a transmitter configured to transmit the coded bit(s) by using a channel, wherein multiplex bit(s) are given based on at least coupling of the coded bit(s) generated by coding of the one or more code blocks, the coding unit maps the multiplex bit(s) to a matrix in a first-axis prioritized manner and reads the multiplex bit(s) from the matrix in the first-axis prioritized manner or in a second-axis prioritized manner, and whether the first axis or the second axis is prioritized in a case that the multiplex bit(s) are read from the matrix is given based on at least whether a signal waveform applied to a prescribed channel is an OFDM.

Abstract: A frequency signal generator includes a controllable oscillator unit, a frequency control unit and an error detection unit. The controllable oscillator unit generates and provides a frequency signal. The frequency control unit generates a frequency control signal and the controllable oscillator unit varies a frequency of the frequency signal based on the frequency control signal. Further, the error detection unit receives the frequency control signal, detects an error within the frequency control signal and provides an error signal. The error signal comprises information on a detected error.