Abstract: A camera includes a lens-camera communication controller and an adapter-camera communication controller. The camera-lens communication channel includes a first data communication channel used during a data communication and a first notification channel used for a notification of a timing of a communication via the first data communication channel. The camera-adapter communication channel includes a second data communication channel used during the data communication and a second notification channel used for a notification of a timing of a communication via the second data communication channel.

Abstract: A clock monitor includes a test clock input, as a reference clock input, another clock input, a measurement circuit, and control logic. The measurement circuit generates a measurement of a frequency or a duty cycle of the test clock input using the reference clock input, which is compared to a threshold. The control logic determines whether the measurement exceeded the threshold and, based on the measurement exceeding the threshold, cause generation of another measurement of a frequency or a duty cycle using the third clock input in combination with the first clock input or the reference clock input. The control logic may determine whether the other measurement exceeded a threshold and, based on such a determination, further determine that the test clock input or the reference clock input are faulty.

Abstract: A signal acquisition of a signal based on specific trigger events is provided. In particular, a separate segment of an input signal is stored for each trigger event. Thus, each trigger event generates separate data comprising data relating to a specific period of time in association with a corresponding trigger event.

Abstract: A system may include a data acquisition hardware device (DAQ) for acquiring sample data and/or generating control signals, and a host system with memory that may store data samples and information associated with the DAQ and host system operations. The DAQ may push hardware status information to host memory, triggered by predetermined events taking place in the DAQ, e.g. timing events or interrupts. The DAQ may update dedicated buffers in host memory with status data for any of these events. The pushed status information may be read in a manner that allows detection of race conditions, and may be used to handle data acquisition, output control signaling, and interrupts as required without the host system having to query the DAQ. The DAQ may also detect data timing errors and report those data timing errors back to the host system, and also provide improved output operations using counters.

Abstract: Embodiments are directed to a method and system for testing and optimizing integrated circuit devices. Latches within an integrated circuit device that fail to operate properly are found using observed data from a test. Thereafter, a directed graph of the layout of the integrated circuit is used to find clock controllers that feed into the latches. The clock controllers that are the most likely to be at issue are ranked, then testing can be performed to confirm that a critical path can be found. The critical path can be excluded from further power optimization to maintain the performance of the integrated circuit device. Other embodiments are also disclosed.

Abstract: An information processing apparatus includes a first memory, a determiner, and a controller. The first memory stores therein a current state of a system running on the information processing apparatus and a target state that is a post-transition state of the system. The determiner determines, upon receiving, from an event notifier, an event notice indicating that a condition for making transition to a specific state is satisfied, whether the current state and the target state match. The controller performs exclusive control when the determiner determines that the current state and the target state of the system do not match, the exclusive control preventing the system from making transition to the specific state.

Abstract: A system may include a processing unit executing program instructions (SW), a data acquisition (DAQ) hardware device for acquiring sample data and/or generating control signals, and host memory configured to store data samples and various data associated with the DAQ and processor operations. The DAQ device may push HW status information to host memory upon being triggered by predetermined events taking place in the DAQ device, e.g. timing events or interrupts, to avoid or reduce SW reads to the DAQ device. The DAQ device may update dedicated buffers in host memory with status data on any of these events. The status information pushed to memory may be read in a manner that allows detection of race conditions. Interrupts generated by the DAQ device may be similarly handled. Upon generating an interrupt, the DAQ device may gather information required to handle the interrupt, and push the information into system memory, along with information identifying the interrupt.

Abstract: This disclosure provides an automation controller method, system and apparatus including a redundant watchdog utilizing a safety partner controller. According to an exemplary controller, the controller includes a first processing unit, a second processing unit, and an integrated circuit configured to receive as inputs fault indicator signals from the first and second processing units, and the integrated circuit configured to disable I/O communications for a fault condition detected by the first or second processing units.

Abstract: Various aspects include a clock monitoring unit/component that is configured to repeatedly/continuously monitor a clock with the speed required to support automobile automation systems without the use of a reference clock. The clock monitoring unit/component may be configured to identify, report, and/or respond to variations or abnormalities in the monitored clock, and initiate an action to prevent the variation from causing or resulting in a failure or a vulnerability to attack. The clock monitoring unit/component in the various aspects may be configured, organized, or arranged to operate so that the circuit is immune or resistant to manipulation, modification, tampering, hacks, and other attacks.

Abstract: According to one embodiment, a semiconductor storage device includes a plurality of semiconductor chips and a control unit. The plurality of semiconductor chips is configured to connect to a signal transmission path and is controlled individually by individual chip enable signals. The plurality of semiconductor chips each includes a termination circuit connected to the signal transmission path. When one of the semiconductor chips is selected to input or output data, the control unit activates the termination circuit provided in the semiconductor chip that is not selected based on a first instruction signal and the chip enable signal.

Abstract: During application of data quality rules to a data set obtained from a data source, data is retrieved from the data source along with a common set of rules configured to format the retrieved data in a manner in accordance with one or more predefined data quality rules of the common set of rules. At least one predefined data quality rule is adjusted utilizing at least one editable widget to form a modified set of data quality rules adapted for use with a specified application. The modified set of data quality rules is applied to the retrieved data.

Abstract: In described embodiments, a method for producing sample decisions with a digital signal processing-based SERDES device includes converting an analog signal to a digital signal, equalizing the digital signal, selecting inputs for a phase detector in a main CDR loop, computing a phase difference signal, producing a phase skew to signals for a last equalization stage by a first interpolation filter bank, generating a control signal to control the phase provided by the first interpolation filter bank by a phase skew adaptation loop, and updating the phase skew values to generate a resulting decision. A device includes a first interpolation filter bank inserted between the equalization stages is configured to generate phase skew signals to a last equalization stage and a phase skew loop responsive to the last equalization stage is configured to adjust the phase skew provided by the first interpolation filter bank.

Abstract: Systems and methods are provided for improved multifunction sensing. In these embodiments a multifunction sensing device (100) includes a microelectromechanical (MEMS) gyroscope (110) and at least a second sensor (112). The MEMS gyroscope (110) is configured to generate a first clock signal, and the second sensor includes a second clock signal. The multifunction sensing device further includes a reset mechanism (114), the reset mechanism (114) configured to generate a reset signal to set the relative periodic phase alignment of the second clock signal to the first clock signal. Consistently setting the relative periodic phase alignment of the clocks for the other sensor devices (112) to the clock of the MEMS gyroscope (110) can improve the performance of the devices by reducing the probability that varying output offsets will occur in the multiple sensing devices.

Abstract: A method and system for automated clock wind-back recovery are disclosed. According to one embodiment, a computer-implemented method comprises requesting a license to access an application and storing a time anchor, the time anchor comprising a recent system time observation. Clock modification is detected, wherein detecting clock modification comprises comparing a license expiration date to a current system time. The time anchor is compared to a trusted time authority value, the trusted time authority value comprising the current system time and a tolerance. The time anchor is updated, clock modification is corrected, and access to the application is retrieved.

Abstract: Component signal values are derived from component signals and fed to at least one fixed equalizer which generates equalizer output signals. The signals are fed to phase error detectors generating phase error signals. The phase error signals are combined with further phase error signals derived by further error detectors receiving signal values from further equalizers and/or the component signal values directly from sample units.

Abstract: Method and system of adjusting a first phase shift between a first data signal and a clock signal at a sending device. First and second test signals representing first and second test data, respectively, are transmitted to a receiving device. The test signals have respective phase shifts relative to the clock signal. An error detection code is calculated from first and second received data carried by the transmitted signals. The error detection code is transmitted from the receiving device to the sending device. An estimated first received data is calculated from the error detection code, wherein the estimated first received data are calculated under the assumption that the second received data are identical to the second test data. The first phase shift is adjusted on the basis of a comparison of the estimated first received data and the first test data.

Abstract: A difference signal calculating unit of a noise detecting device calculates a difference between the amplitudes of a residual signal at each sample timing and a residual signal at the preceding sample timing. A difference signal comparing unit determines whether or not an impulsive noise is present on the basis of the difference signal at the current sample timing, and the difference signal at each sample timing within a predetermined duration from the current sample timing.

Abstract: Provided is a method and apparatus for encoding and decoding in which block coding is applied. According to a method and apparatus for block coding encoding and decoding, a minimum quality seamless service may be provided by reliably recovering high importance data even though continuous data loss occurs in a wired and wireless transmission line. A transposed duplication calculation or a post duplication calculation may be performed with respect to the high importance data. Data of a predetermined lost time zone may be recovered by duplicated data of another time zone.

Abstract: This invention relates to a method of receiving a first potentially unreliable clock signal having a first frequency; receiving a second reliable clock signal having a second frequency; wherein the first frequency and the second frequency have an expected relationship; determining whether the first potentially unreliable clock signal has changed with respect to the second reliable clock signal by: determining an actual relationship between the first potentially unreliable frequency and the second reliable frequency; and generating an alarm signal if the actual relationship is different to the expected relationship.

Abstract: A system for signal processing includes: a plurality of signal processing units associated with corresponding channels; a feedback channel for receiving a selected feedback signal through a selector of an output associated with each of the signal processing units; and a correlator connected to the feedback channel and having a receiving unit to receive the selected feedback signal, an error calculating unit to calculate an error based at least in part on the selected feedback signal, and a correction calculation unit to generate a correcting information based at least in part on the error. In some cases, the association between the signal processing units and the signal channels is configured based on a mode.

Abstract: A method of iteratively decoding data transferred through a channel is provided. The method may include iteratively decoding each sector of 1 to N sectors of the data in continuous succession until all N sectors are decoded, wherein upon determination of successful completion of iterative decoding corresponding to a current sector of the N sectors, immediately initiating iterative decoding a next sector of the N sectors.

Abstract: A path monitor, a method of monitoring a path, an integrated circuit and a library of standard logic elements. In one embodiment, the path monitor includes: (1) a delay element having an input couplable to an input of a clocked flip-flop associated with a path to be monitored and configured to provide a predetermined delay and (2) a clocked exclusive OR gate having a clock input, a first input coupled to an output of the delay element, a second input couplable to the output of the clocked flip-flop and an output at which the clocked exclusive OR gate is configured to respond to a clock signal to provide an error signal only when logic levels of the first input and the second input differ.

Abstract: An electronic device is described which receives data from a transmitting device via a communications channel. The electronic device comprises digital processing circuitry arranged to process the data received via the communications channel to generate output data, error detection circuitry arranged to detect errors in the output data, and monitoring circuitry arranged to monitor the quality of digital processing conducted by the digital processing circuitry and generate digital performance data indicative of the monitored quality of digital processing. The electronic device also comprises control circuitry responsive to error information comprising errors detected by the error detection circuitry and the performance data generated by the monitoring circuitry to modify the operation of one or both of the transmitting device and the electronic device.

Abstract: An arbitration diagnostic circuit and method provide diagnostic information in arbitration-based systems and/or provide detection of and response to excessive arbitration delays. For example, in one embodiment, an arbitration diagnostic circuit maintains a chronological memory trace of arbitration events, including resource request events and corresponding resource grant events for two or more entities having arbitrated access to a shared resource. The trace, which may be regarded as a running, ordered list, may comprise time-stamped event identifiers, which aid the analysis of arbitration related errors or failures. Indeed, in one or more embodiments, an arbitration diagnostic circuit is configured to track elapsed times for resource requests, and to detect resource grant delay violations.

Abstract: In described embodiments, a transceiver supports two or more rates using an oversampling clock and data recovery (CDR) circuit sampling high rate data with a predetermined CDR sampling clock. A timing recovery circuit detects and accounts for extra or missing samples when oversampling lower rate data. An edge detector detects each actual data symbol edge and provides for an edge decision offset in a current instant's block of samples. An edge error is generated from the previous instant's actual and calculated edges; and an edge distance between actual edges of the current and previous instants is generated. Filtered edge distance and error are combined to generate a calculated edge position for the data symbol edge for the current instant. The edge decision offset is applied to the current calculated edge position to identify a sample value to generate a decision for the data symbol to detect the current data value.

Abstract: A measured device coupled to test equipment providing at least two test factors and receiving a test result is disclosed. The measured device includes a combinatorial logic circuit and a main circuit. The combinatorial logic circuit includes a first storage module and a second storage module. The first storage module stores the test factors according to a first operation clock. The second storage module stores and outputs at least two output factors according to a second operation clock. The frequency of the second operation clock is higher than the frequency of the first operation clock. When the test factors are stored in the first storage module, the test factors stored in the first storage module are served as the output factors and the output factors are output and stored in the second storage module. The main circuit generates the test result according to the output factors output by the second storage module.

Abstract: A clock and data recovery device recovers data from a sequential stream of data that includes bursts of data separated by gaps. Each burst of data arrives with its own phase and with its own deviation from a nominal frequency. The bursts of data begin with a preamble that is utilized to determine the timing of the burst. The clock and data recovery device determines the timing of a burst of data using signals from one or more demultiplexers or samplers. At the start of each burst of data, sampled input signals are analyzed by an edge detector to determine a sample phase for the burst. A selector utilizes the sample phase determined by the edge detector to choose which of the sampled input signals to use to produce output data signals from the clock and data recovery device.

Abstract: A device and a method detect an acceleration of a logic signal expressed by a closeness, beyond a closeness threshold, of at least two variation edges of the logic signal. A first control bit and a second control bit are provided. At each edge of the logic signal, the value of the first control bit is inverted after a first delay and the value of the second control bit is inverted after a second delay. An acceleration is detected when the two control bits have at the same time their respective initial values or their respective inverted initial values. Application is in particular but not exclusively to the detection of error injections in a secured integrated circuit.

Abstract: A reception apparatus that receives a signal, including, a correction section, an error detection section, a filtering section, and a setting section is provided.

Abstract: Systems, controllers, and methods are disclosed, such as an initialization system including a controller configured to receive patterns of read data coupled from a memory device through a plurality of read data lanes. The controller is operable to detect lane-to-lane skew in the patterns of read data. The controller then adjusts the manner in which the read data received through the read data lanes during normal operation are divided into frames. The controller can also couple patterns of command/address bits to the memory device through a plurality of command/address lanes. The memory device can send the received command/address bits back to the controller through the read data lanes. The controller is operable to detect any lane-to-lane skew in the patterns of command/address bits received through the read data lanes to adjust the manner in which the command/address bits coupled through the command/address lanes during normal operation are divided into frames.

Abstract: A digital broadcasting system and a method for transmitting and receiving digital broadcast signal are disclosed. The method of transmitting digital broadcast signal includes convolutional encoding mobile data to build SCCC blocks, generating signaling data, forming a first data group and a second data group which includes mobile service data and the signaling data, interleaving data including the mobile service data in the first and second data groups and outputting a interleaved first data group and an interleaved second data group, wherein at least one of the SCCC blocks include an extension data block from the interleaved first data group and a data block from the interleaved second data group, transmitting the digital broadcasting signal including the first data group and the second data group.

Abstract: An integrated circuit 2 includes logic circuitry 10 and sequential storage elements 8. Both the logic circuit 10 and sequential storage elements 8 can be subject to particle strikes giving rise to single event upset errors. These single event upset errors can be detected by detecting a transition in the stored value stored by the sequential storage elements 8 occurring outside of a valid transition period associated with that sequential storage element 8.

Abstract: A method and system for using a magnitude comparator circuit and a flag bit, for detecting and preventing errors from occurring in the FSM state bits that could otherwise cause the system to hang. Preferably, the flag bit is set with all the valid state transitions, and a magnitude comparator is used to continuously monitor the value of the current state bits. When a FSM state transition occurs based on the flag bit and the output of the magnitude comparator, a potential error condition can be detected and the FSM transition can be blocked or the FSM can be safely transitioned into a predetermined “reset state”.

Abstract: A delay measuring device according to the present invention comprises a memory cell, a delay element and a selector. The memory cell is provided with a non-inversion output terminal and an inversion output terminal, and the memory cell fetches a data value inputted from outside in synchronization with a clock, retains the fetched data value and outputs the retained data value from the non-inversion output terminal and the inversion output terminal. The delay element is connected to the inversion output terminal. The selector selects one of the data value and a delayed data value outputted from the delay element and supplies the selected data value to the memory cell. In the present invention, a comparison result of making a comparison between a delay amount generated in the delayed data value and a time length defined based on the clock is outputted from the non-inversion output terminal.

Abstract: An integrated circuit includes a plurality of processing stages each including processing logic 1014, a non-delayed signal-capture element 1016, a delayed signal-capture element 1018 and a comparator 1024. The non-delayed signal-capture element 1016 captures an output from the processing logic 1014 at a non-delayed capture time. At a later delayed capture time, the delayed signal-capture element 1018 also captures a value from the processing logic 1014. An error detection circuit 1026 and error correction circuit 1028 detect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator 1024. The comparator 1024 compares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value.

Abstract: A shift amount measuring apparatus for measuring a phase shift amount of a signal under measurement which is input thereto includes a PLL circuit that generates a strobe signal which is synchronized with a reference signal, a CDR circuit that inputs, into the PLL circuit, a control signal which has a level determined in accordance with a difference in phase between the signal under measurement and the strobe signal, so as to achieve a predetermined difference in phase between the signal under measurement and the strobe signal, and a measuring circuit that, before and after the signal under measurement is phase-shifted, measures a value of the control signal when the predetermined difference in phase is achieved between the signal under measurement and the strobe signal, and calculates the phase shift amount of the signal under measurement based on a difference between the measured levels of the control signal.

Abstract: First data representing user data and third data use the same error correction codes. The first data has a first error correction block structure and the third data has a second error correction block structure. That is to say, the first data and the third data have their respective error correction block structures proper for them. In particular, the recording density of the third data is made less dense than the recording density of the first data, and the number of correction codes in the first error-correction block is set at a multiple of m whereas the number of correction codes in the second error-correction block is set at n/m times the number of correction codes in the first error-correction block so that a data-piece count in the second error-correction block is also n/m times a data-piece count in the first error-correction block. As a result, it is possible to provide a good technique of recording shipping-time information onto a high-recording-density disc.

Abstract: Method and system of adjusting a first phase shift between a first data signal and a clock signal at a sending device. First and second test signals representing first and second test data, respectively, are transmitted to a receiving device. The test signals have respective phase shifts relative to the clock signal. An error detection code is calculated from first and second received data carried by the transmitted signals. The error detection code is transmitted from the receiving device to the sending device. An estimated first received data is calculated from the error detection code, wherein the estimated first received data are calculated under the assumption that the second received data are identical to the second test data. The first phase shift is adjusted on the basis of a comparison of the estimated first received data and the first test data.

Abstract: A test apparatus for testing a device under test includes a first timing comparator obtaining a device output signal output from the device under test at a timing designated by a first strobe signal, a second timing comparator obtaining the device output signal at a timing designated by a second strobe signal supplied later than the first strobe signal, a preceding edge judging circuit, when rising and falling signals are input at the same timing as the device output signal, judging which one of the rising and falling signals arrives at the first and second timing comparators at an earlier timing, a preceding edge detecting circuit adjusting a timing at which the first strobe signal is supplied so that the first timing comparator obtains, at a timing of a rising or falling edge, one of the rising and falling signals which is judged to arrive earlier, and a following edge detecting circuit adjusting a timing at which the second strobe signal is supplied so that the second timing comparator obtains, at a timing

Abstract: An apparatus for locking out a source synchronous strobe receiver, including a delay-locked loop (DLL) and one or more receivers. The DLL receives a reference clock, and generates a select vector and an encoded select vector that both indicate a lockout time. The select vector is employed to select a delayed version of the reference clock that lags the reference clock by the lockout time. The lockout time is slightly less than a number of cycles of the reference clock. The one or more receivers are each coupled to the delay-locked loop. Each of the one or more receivers receives the encoded select vector and a corresponding strobe, and locks out reception of the corresponding strobe for the lockout time following transition of the corresponding strobe. The encoded select vector is employed to determine the lockout time by selecting a delayed version of the corresponding strobe.

Abstract: During a trace the timing stream has the active and stall information, PC stream has all the discontinuity information, and the data stream has all the data log information. The various streams are synchronized using markers called sync points. The sync points provide a unique identifier field and a context to the data that will follow it. After data corruption a sync point is inserted into the data stream. The ID of this sync point may repeat a previous sync point ID.

Abstract: A detector for detecting information carried by a signal having a sawtooth-like shape. The detector includes a first band-pass filter with center frequency around a first frequency value for filtering the signal and generating a first filtered signal, a second band-pass filter with center frequency around a second frequency value for filtering the signal and generating a second filtered signal, a first comparator for comparing the first filtered signal with a reference level and generating a first compared signal, a second comparator for comparing the second filtered signal with the reference level and generating a second compared signal, a clock generator for generating a reference clock having a frequency close to the first frequency value according to the second compared signal, and a detection module for generating a bit signal representing the information according to the first compared signal and the reference clock.

Abstract: The invention relates to a decoding device particularly adapted to decode a digital input signal (E) in a transmission system using direct sequence spread spectrum, this digital input signal (E) being composed of symbols, each symbol representing a bit satisfying a Barker code, and comprising several symbol elements. This device comprises several finite response filters (FLT1 to FLT4) each of which receives the digital input signal (E), a clock circuit (CLK_GEN) outputting clock signals (CLK1 to CLK4) to the filters with a frequency equal to the frequency at which symbol elements are produced and uniformly distributed phase shifts, and an analysis circuit (ANL) designed to identify which of the filters is best tuned to the input signal (E) and to control the clock circuit to make it generated a clock signal (CLK5) optimised for decoding and an analysis circuit.

Abstract: The present invention provides a transceiver for receiving and transmitting data over a network, and a method for testing the same. In particular, the present invention provides a physical layer transceiver having a built-in-self-test (BIST) device that allows for, among other things, pulse density/width variation and jitter control.

Abstract: A circuit may be used for testing for faults in a programmable logic device. The circuit may include a clock generator coupled to receive a reference clock signal and generate a high speed clock signal; a circuit under test coupled to receive selected pulses of the high speed clock signal; and a programmable shift register coupled to receive a pulse width selection signal and generate an enable signal for selecting the pulses the high speed clock signal, wherein the pulse width of the enable signal is selected based upon the value of the pulse width selection signal. A method of testing for faults in a programmable logic device is also disclosed.

Abstract: A method implemented in a test system comprises a test debug system and a target system, said target system comprising a test access port that functions according to a plurality of states and also comprising an adapter. The method comprises the adapter transferring data to the test debug system while the test access port remains in a predefined state. The predefined state comprises a state in which no scans occur.

Abstract: Static timing analysis attempts to exhaustively analyze all critical paths of a design. With ever decreasing geometries and ever increasing design complexity, manually identifying timing violations with standard static timing analysis can be very complex and time consuming. A static timing analysis tool can advantageously manage multiple runs having different modes and corners and automatically merge the results generated by the runs. The STA tool can perform the runs either in parallel or in series. Advantageously, the STA tool can save the full timing analysis generated by each run and then extract information from these saved results to form merged results for the design. These merged results can provide different levels of analysis coverage, supply path information at various levels of detail, allow selectable accessibility to information, and highlight propagation of timing changes/violations in the design.

Abstract: A scan test circuit includes tester inputs that receive scan test data. Scan chains are coupled to the tester inputs. The tester outputs are coupled to the scan chains and provide output test data based on the scan test data. A first clock generates a first clock signal. A sampling circuit samples each of the tester outputs at least twice per clock cycle of the first clock signal.

Abstract: The apparatus includes a first variable delay circuit that delays a data signal from a device under test (DUT) to output a delay data signal; a second variable delay circuit that delays a clock signal to output a first delay clock signal; a first FF that acquires the delay data signal based on a reference clock; a second FF that acquires the first delay clock signal based on the clock; a first delay adjusting section that adjusts a delay amount of at least one of the first and second variable delay circuits so that the first and second FFs acquire the delay data signal and the first delay clock signal when the signals are changed; a third variable delay circuit that delays the clock signal to output a second delay clock signal; a second delay adjusting section that adjusts a delay amount of the third variable delay circuit based on the acquired first delay clock signal of which a phase is adjusted by the first delay adjusting section when the second delay clock is changed, in order to adjust a phase differenc

Abstract: An integrated circuit and a method for testing an integrated circuit.