Abstract: Provided are an acknowledgement (ACK) method and apparatus of an aggregated frame in a wideband high frequency wireless system. The ACK method of a destination apparatus in the wideband high frequency wireless system includes reading subframes included in an aggregated frame during a predetermined period of time when receiving the aggregated frame, and generating an ACK frame including information about a reading result of the aggregated frame during the predetermined period of time.

Abstract: A data storage controller for controlling each data access of a data storage element is disclosed. The data storage controller includes a processing unit and a storage unit. The processing unit is utilized for executing an automated testing program on the data storage element for automated testing. The storage unit is coupled to the processing unit and utilized for storing the automated testing program.

Abstract: Novel, computationally efficient schemes for deterministic wavelet thresholding with the objective of optimizing maximum-error metrics are provided. An optimal low polynomial-time algorithm for one-dimensional wavelet thresholding based on a new dynamic-programming (DP) formulation is provided that can be employed to minimize the maximum relative or absolute error in the data reconstruction. Directly extending a one-dimensional DP algorithm to multi-dimensional wavelets results in a super-exponential increase in time complexity with the data dimensionality. Thus, novel, polynomial-time approximation schemes (with tunable approximation guarantees for the target maximum-error metric) for deterministic wavelet thresholding in multiple dimensions are also provided.

Abstract: Disclosed is a method for processing a DCD content in a DCD (Dynamic Content Delivery). When a DCD content is delivered between a server and a terminal in a DCD service system, a client of the terminal delivers the DCD content to a DECA (DCD Enabled Client Application) of the terminal. If the DECA cannot play (execute) the content, the DECA sends to the client an error notification message and a generated status value (information about device capabilities of the terminal), and the client sends the error notification message and the status value to the server. Accordingly, if an error informing that the content received from the server cannot be played has occurred, the error is processed between the terminal and the server from the point of the terminal.

Abstract: A semiconductor device includes circuits to be tested, an input terminal for receiving a tester clock signal from outside, a built-in self-test (BIST) circuit for logically testing the circuit at every cycle of a tester clock signal, and an output terminal for outputting a test result signal representing a result of testing performed in the BIST circuit. Before generating a test result signal, the BIST circuit generates a marker signal, whose phase is identical to the phase of the test result signal, instead of the test result signal.

Abstract: Plural scan test paths (401) are provided to reduce power consumed during testing such as combinational logic (101). A state machine (408) operates according to plural shift states (500) to control each scan path in capturing data from response outputs of the combinational logic and then shifting one bit at a time to reduce the capacitive and constant state power consumed by shifting the scan paths.

Abstract: Apparatus methods for capturing flow control errors in FIFO exchanges between producing and consuming circuits operating in different clock domains. Tag information at the start of an exchange is transferred to a synchronizing component before data of a transfer transaction is entered in the FIFO. The tag information is also associated with each unit of data transferred to the FIFO by the producing circuit. The synchronizing component verifies the each unit of data retrieved by the consuming circuit has the expected tag information associated therewith and signals an error is the tag information does not match. Thus an error by the producing circuit in entering too much or too little data for a transfer is detected before erroneous data is retrieved and processed by the consuming circuit.

Abstract: A computer system including: a memory configured to store various kinds of data; a use setting data memory means for storing use setting data indicating a use of each of a plurality of memory blocks into which the memory is divided by a certain length; a memory diagnosis means for diagnosing the memory so as to detect a bad area in each of the memory blocks; and a memory use setting means for setting the use setting data of each of the memory blocks stored in the use setting data memory means in accordance with a result of detecting the bad area in each of the memory blocks by means of the memory diagnosis means.

Abstract: A system and method for generating an orthogonal array (OA) for software testing is disclosed. In one embodiment, the method for generating an OA of test cases for testing a system includes accepting a user input from a user, the user input including multiple factors and multiple levels associated with the system, accessing a reference table to determine a set of parameters based on the user input for testing each level of a factor against all levels of all other factors in the system, and performing a predetermined number of iterations based on the set of parameters to generate the OA of the test cases. The OA of the test cases includes combinations of the multiple factors and the multiple levels required for testing pair-wise interactions between the multiple levels and the multiple factors in the system.

Abstract: A data transport system for transporting data between a server (21) and a client receiver (27) over a network (23) includes a receiving proxy cache (25) coupled to a client receiver (27) via a reliable connection (29), such as a cable connection. The majority of data is transported from the server (21) to the receiving proxy cache (25) over an efficient data transmission channel (41). The receiving proxy cache (25) verifies the status of the data transmitted over the efficient channel (41). If there is an error in the data transmission, a portion of the data associated with the error is retransmitted from the server (21) to the receiving proxy cache (25) over a reliable data transmission channel (43). The complete data at the receiving proxy cache (25) is delivered to a client receiver (27) over a reliable connection (29).

Abstract: Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments detect receive errors for input data streams of unknown patterns, and can thus be used for in-system margin testing. Such systems can be adapted to dynamically alter system parameters during device operation to maintain adequate margins despite fluctuations in the system noise environment due to e.g. temperature and supply-voltage changes. Also described are methods of plotting and interpreting filtered and unfiltered error data generated by the disclosed methods and circuits. Some embodiments filter error data to facilitate pattern-specific margin testing.

Abstract: A compression subsystem for a computed tomography system compresses projection data to for efficient data transfer and storage. The compression includes applying an attenuation profile to an array of projection data samples. The attenuation profile is a function of sample coordinates and determines attenuation values applied to the samples. The attenuated samples are encoded and packed for data transfer. Alternatively, difference operators are applied to the attenuated samples and the differences are encoded. The average number of bits per compressed sample is monitored and the attenuation profiles can be modified to achieve a desired number of bits per compressed sample. The compressed samples are decompressed prior to image reconstruction processing. Decompression includes decoding the compressed samples and applying a gain profile to the decoded samples to restore the original dynamic range. This abstract does not limit the scope of the invention as described in the claims.

Abstract: A system comprises a circuit analysis module configured to analyze a device under test (DUT), the DUT comprising a plurality of latches coupled together in a scan chain. A don't-care analysis module identifies absolute don't-care latches within the DUT, assigns a weighted value to the bit positions of identified don't-care latches, and identifies absolute don't-care bits within a general test pattern. The circuit analysis module replaces identified absolute don't-care bits in the general test pattern according to the weighted value of the associated bit position, generating a weighted test pattern. A test vector module generates a test vector based on the weighted test pattern and an input module applies the test vector to the DUT.

Abstract: Systems and methods are described which allow the detection of gaps in a set of data. These systems and methods may include defining streams of data from a network topology, associating incoming data with one or more of these streams, and processing these streams. A gap may be detected by comparing the times of events in the stream. If a gap is detected remedial action may be taken, and processing of the streams temporarily halted. Processing of the streams may continue when data for a certain stream is received, or after the lapse of a certain period of time.

Abstract: The innovation relates to a system and/or methodology for the configuration and creation of industrial automation designs. The system providing for the generation of functional specifications, software and hardware designs, as well as testing and testing schemas. Additionally, the innovation provides a user interface for modification of the designs and specifications.

Abstract: In a first embodiment a TAP of IEEE standard 1149.1 is allowed to commandeer control from a WSP of IEEE standard P1500 such that the P1500 architecture, normally controlled by the WSP, is rendered controllable by the TAP. In a second embodiment (1) the TAP and WSP based architectures are merged together such that the sharing of the previously described architectural elements are possible, and (2) the TAP and WSP test interfaces are merged into a single optimized test interface that is operable to perform all operations of each separate test interface. One approach provides for the TAP to maintain access and control of the TAP instruction register, but provides for a selected data register to be accessed and controlled by either the TAP+ATC or by the discrete CaptureDR, UpdateDR, TransferDR, ShiftDR, and ClockDR WSP data register control signals.

Abstract: A method for dynamically broadcasting configuration information to controllers connected in a scan topology in a target system is provided in which a selection event followed by the configuration information is received from a signal line at each of the controllers, wherein the plurality of controllers are connected in parallel to the signal line and the configuration information is stored within each controller that matches a selection criteria following the selection event when the selection event initiates a selection sequence.

Abstract: A method, system, and computer-readable medium for self-healing a software factory are presented. Factory metrics that describe resources and operations within the software factory are collected and analyzed. If the analysis reveals a significant problem within the software factory, then corrective measures are taken and stored, thus enabling the software factory to evolve and improve over time.

Abstract: A memory test circuit includes a counter circuit that outputs a set signal that is set to the first set value or the second set value alternately in a cycle of the clock signal, an OR circuit that calculates a logical sum of the set signal and the input signal each time when the set signal is output from the counter circuit and outputs a control signal indicating the logical sum of the set signal and the input signal, and a test pattern generation circuit that generates the test pattern for causing the memory to operate in each first cycle if a set value of the control signal is the first set value, or generates the test pattern for causing the memory to operate in each second cycle if the set value of the control signal is the second set value.

Abstract: According to some embodiments, characterization data can be loaded onto a programmable device. The characterization data can be configured to cause the programmable device to perform one or more functions if executed on the programmable device. It can then be determined whether or not loading the characterization data onto the programmable device caused the programmable device to be successfully programmed. An indication can be transmitted for receipt by an external device, the indication indicating whether or not the programmable device was successfully programmed.

Abstract: An audio codec and a BIST method adapted for the audio codec are provided. The BIST method includes the following steps. A first channel digital-to-analog converter (DAC) of the audio codec converts a test signal into an analog signal. A first channel analog-to-digital converter (ADC) of the audio codec converts the analog signal into a digital signal. Use a second channel DAC of the audio codec and a second channel ADC of the audio codec to calculate the magnitudes of a plurality of spectral components of the DFT of the digital signal. Determine whether the audio codec passes the test according to the magnitudes of the spectral components.

Abstract: A digitally controlled circuit and method includes an error input coupled to a proportional path. The proportional path includes a selector which directly receives the error input as a select signal. The selector receives a proportional control weight from a location other than the proportional path wherein the proportional control weight is input to a digitally controlled oscillator (DCO).

Abstract: A test system for testing various functions of electronic devices includes a master device and a simulation control device. The master device is connected to an input device and the electronic devices through the simulation control device. The master device records input signals of the input device and generate simulation signals according to the input signals. The simulation control device simulates the input signals of the input device according to the simulation signals to test the electronic devices.

Abstract: Progress of a development cycle, such as for the development of a release of a software product, is tracked and managed using a release management system. Such a system allows groups and managers to retain any project planning or status files, in any appropriate structure. A manager can simply upload the file to the system as information is updated, and the system will apply appropriate templates and store the information in such a way that reporting and tracking can be done for any aspect of the development process at any level. For example, a single system can provide a high-level executive overview down to a detail level view of a particular group, using substantially current data for all aspects the process.

Abstract: A device for processing test data, the device having a data input interface adapted for receiving primary test data indicative of a test carried out for testing a device under test, the primary test data being provided in a primary format, a processing unit adapted for generating secondary test data in a secondary format by transforming, by carrying out a coordinate transformation, the primary test data from the primary format into the secondary format, and a data output interface adapted for providing the secondary test data in the secondary format for storing the secondary test data in a plurality of storage units.

Abstract: A system for debugging a device under test may include a processor register with a program count and a debug program register that receives the program count upon execution of an instruction by a processor. In one implementation, a microcontroller under test by a debugger is accessed using a serial interface, such as a JTAG interface. The interface can communicate directly with a debug register to retrieve program count values, both when the microcontroller is halted and when it is executing instructions. The polling interval to retrieve the program count values may be adjusted by a user of the debugger based on considerations such as bandwidth and accuracy. The microcontroller may transmit the program count value to the debug register from a processing register that is not accessible to the debugger.

Abstract: A multi-clock system-on-chip (D) comprises i) a core (CE) comprising asynchronous clock domains provided for exchanging test data therebetween, ii) a clock generator unit (CGU) arranged for delivering primary clock signals (clk1-clko) for at least some of the clock domains, and iii) clock control modules (CCl-CCo), arranged respectively for defining the functional clock signals from the primary clock signals and from control signals (intended for setting the clock control modules (CCl) in a normal mode allowing test data transmission from the corresponding emitter clock domain to at least one receiver clock domain or a shift mode forbidding such a test data transmission).

Abstract: A TAP linking module (21, 51) permits plural TAPs (TAPs 1-4) to be controlled and accessed from a test bus (13) via a single TAP interface (20).

Abstract: An apparatus for data communication that receives a plurality of pulses from a remote communications device, determines a pulse puncturing rate based on the pulses, and punctures or discards subsequent pulses based on the pulse puncturing rate. During intervals when punctured pulses are expected, the apparatus operates in a lower power consumption mode for the purpose of conserving power. In another aspect, a receiving apparatus determines the pulse puncturing rate based on received pulses, and transmits the pulse puncturing rate information to a transmitting apparatus. In response, the transmitting apparatus sends a subset of the pulses it would have transmitted based on the pulse puncturing rate. Because the receiving apparatus receives fewer pulses (e.g., a subset), the receiving apparatus may operate in a lower power consumption mode for longer periods in order to conserve power.

Abstract: Systems and methods for providing automated computer support are described herein. One described method comprises receiving a plurality of snapshots from a plurality of computers, storing the plurality of snapshots in a data store, and creating an adaptive reference model based at least in part on the plurality of snapshots. The described method further comprises comparing at least one of the plurality of snapshots to the adaptive reference model, and identifying at least one anomaly based on the comparison.

Abstract: A processing device, processing system, method, and design structure for an enhanced microprocessor interconnect with bit shadowing are provided. The processing device includes shadow selection logic to select a driver bit position as a shadowed driver value, and line drivers to transmit data for the selected driver bit position and the shadowed driver value on separate link segments of a bus. The processing device also includes shadow compare logic to compare a selected received value with a shadowed received value from the bus and identify a miscompare in response to a mismatch of the compare, and shadow counters to count a rate of the miscompare relative to a bus error rate over a period of time. A defective link segment is identified in response to the rate of the miscompare within a predefined threshold of the bus error rate.

Abstract: Memory systems, systems and methods are disclosed that may include a plurality of stacked memory device dice and a logic die connected to each other by through silicon vias. One such logic die includes an error code generator that generates error checking codes corresponding to write data. The error checking codes are stored in the memory device dice and are subsequently compared to error checking codes generated from data subsequently read from the memory device dice. In the event the codes do not match, an error signal can be generated. The logic die may contain a controller that records the address from which the data was read. The controller or memory access device may redirect accesses to the memory device dice at the recorded addresses. The controller can also examine addresses or data resulting in the error signals being generated to identify faults in the through silicon vias.

Abstract: There is described an automation network, a remote access server for an automation network and a method for transmission of operating data between an automation system with one or more automation devices and a remote computer with the operating data of the automation device being transmitted via the Internet or an intranet and displayed and/or changed on the remote computer by an Internet browser. The remote access server provides the operating data for the remote computer and, for a session-oriented access, creates a software object as an image of the automation device and, if changes are to be made to the operating data by the access, a software object for simulation of the automation device and/or of the process to be controlled by the automaton device, so that any changes can be checked for permissibility and/or validity before being forwarded to the automation device.

Abstract: Methods and systems for simplified error recovery in a SAS device. A SAS device (e.g., a SAS/SSP target device such as a storage device) enhanced in accordance with features and aspects hereof NAKs a received frame that has an error and then NAKS all subsequently received frames, regardless of whether received with or without error, until the connection is closed. The second SAS device (e.g., a SAS/SSP initiator) then performs required error recovery by re-establishing a connection and re-transmitting all previously NAKed frames. The enhanced SAS thereby simplifies logic for error recovery.

Abstract: A system for automatically attaching a radio frequency identification (RFID) tag label and a method thereof are provided.

Abstract: A test management application on a test management server includes a user interface on a Web-based portal by which a user can define one or more tests, selecting any desired configuration of operating system, connection type, and/or application, which are then saved in a test management database in the central server. Multiple tests involving the same configuration can be defined and saved for later selection, either individually or as a group of tests. A client agent engine on a test device can query the test management server for tests that can be conducted using the device's current configuration. If no such tests are found, the device can then query the test management server for the next available test. Upon allocation of the next available test to the device, the necessary system configuration for that test can be automatically retrieved, installed, and verified by the device. The device under test is automatically rebuilt to have the proper configuration for the test to be run.

Abstract: According to one embodiment, a semiconductor integrated device which stores secret data and is capable of operating in a test mode in which a scan test with respect to an internal circuit is executed, the semiconductor integrated device comprises a mode signal receiving module configured to receive a scan mode signal designating the test mode, a mask module configured to mask the secret data when the mode signal receiving module receives the scan mode signal, and an error detection module configured to detect presence or absence of error in the secret data and to store detection result in a first flip-flop.

Abstract: The invention provides a packet error detecting method for a serial link. When a start framing symbol of a packet appears at the serial link, the start framing symbol is ignore if a predetermined error condition is satisfied.

Abstract: A method and apparatus for comparing two computing platforms installed with instances of an application, a portal or another computerized unit, wherein one computerized unit malfunctions when executed by the corresponding computing platform. The method and apparatus query the two computing platforms and the two instances for a multiplicity of values associated with a multiplicity of parameters that may influence the functionality, compare the parameter values and report the differences to a user, in order to enable the user to locate the root cause of the problem. The parameters may relate to the instances as well as to the computing platforms and their environment. The parameter retrieval and comparison can be performed by the apparatus, or by components of the instances for handling proprietary data types.

Abstract: Described are techniques for providing an application program interface that leverages the terminal services session broker infrastructure to support third party plug-in applications. In a typical scenario, when a user requests for a connection to access third party plug-in applications, the application program interface may override the session broker logic and interacts with the session broker process to identify sessions or suitable servers to which the user can be connected. The user may access the third party plug-in applications through the identified sessions or suitable servers.

Abstract: A system includes a plurality of devices that are connected in series and a controller that communicates with the devices. Each of the devices has a plurality of input ports and corresponding output ports. The outputs of one device and the inputs of a next device are interconnected. The controller is coupled to the first device and the last device of the series-connection. The controller applies a test pattern to the plurality of input ports at the first device connected in series, by the controller. Each data channel defines a data path between corresponding pairs of input and output ports of the first and last devices. A data channel is enabled if the test pattern is detected at its corresponding output port.

Abstract: A method for fail-safe transmission of information between a transmitter and a receiver is disclosed. At least two telegrams relating to the information are transmitted as a first telegram via a first channel and a second telegram via a second channel from the transmitter to the receiver. To identify an error affecting the information during transmission, a first identifier is generated from a first subset of the first telegram being used at the receiver to identify the information contained in the first telegram. This method is used for communication from a safety switching device to a control unit.

Abstract: In another embodiment, a method for securing a field-programmable logic chip or circuit (FPLC) is disclosed. Information is cryptographically processed within the FPLC. An error condition is detected outside of the FPLC and the error condition is communicated to the FPLC to disrupt an image(s) within the FPLC. Optionally, at least a portion of a key can be erased such that cryptographic processing is curtailed or eliminated.

Abstract: The method is executed by a call control server that establishes a media session for sending and receiving media data between a calling terminal and a called terminal. The method includes exchanging messages with calling terminal and called terminal for establishing the media session, generating a session information necessary for establishing the media session based on the messages exchanged with the calling terminal and/or the called terminal, monitoring a media information included in the messages, the media information containing a definition specifying a way of exchanging the media data, determining, based on the monitoring result, whether the media session has been established, and transferring the session information to at least one other call control server different from the call control server if the media session has been established.

Abstract: The invention provides a method and apparatus for predicting the failure of a component using a probabilistic model of a material's microstructural-based response to fatigue. The method predicts the component failure by a computer simulation of multiple incarnations of real material behavior, or virtual prototyping. The virtual prototyping simulates the effects of characteristics that include grain size, grain orientation, micro-applied stress and micro-yield strength that are difficult to simulate with real specimens. The invention provides an apparatus for predicting the response of a component to fatigue using the method.

Abstract: A method and a system for streaming multi channel digital isochronous data. The method is used for streaming multi channel digital isochronous data, e.g. audio data, in a standard wireless local area network transmission system where bandwidth is reserved for both contention-based traffic and contention free traffic and the audio data formed by samples is organized in audio frames and sent to receivers using multicasting, within consecutive beacon intervals. The contention free traffic of the beacon interval is adjusted to an optimum value, and the length of the beacon interval is adjusted such that a required amount of audio data can be sent to the receivers with minimum system delay.

Abstract: Provided is a control device including: a storage portion for storing binary data transmitted from outside and received successively; and a control portion for carrying out processing including: production processing of producing a frame where of the stored binary data, pieces of data expressing events occurring in a predetermined period are placed into a group among which pieces of data expressing events each having a small degree of variation are arranged so as to be close to each other; difference computing processing of arranging the frames produced at intervals of the predetermined time in a predetermined order and of computing a difference between two adjacent frames; compression processing of compressing a result of the computation by a run length method; and recording processing of recording, to a recording portion, a first frame in the difference computing processing, a number of difference computations, and the compressed data.

Abstract: There is provided a test apparatus for testing a plurality of devices under test. The test apparatus includes a signal input section that applies a test signal to the devices under test so as to cause the devices under test to concurrently output response signals, a combining section that generates a single combination signal by using the response signals output from the devices under test, and a judging section that judges whether the devices under test operate normally with reference to the combination signal.

Abstract: A method for testing a high-speed serial interface, comprising: generating a customized stress test pattern configured to violate an 8bit/10bit-encoding scheme into an expander, the customized stress test pattern is configured to stress the high-speed serial interface beyond marginal limits resulting in less testing to force errors within the high-speed serial interface; transmitting the customized stress test pattern from a transmit port of a first serializer/deserializer device of the high-speed serial interface; and monitoring a receive port of a second serializer/deserializer device to detect errors within the high-speed serial interface.

Abstract: A method and system for cache-based dropped write protection in data storage systems are provided. An implementation involves detecting undetected write errors in a storage system, by writing data to a storage medium from a data cache; maintaining a copy of the data in the data cache until said data on the storage medium is validated or said data needs to be evicted from the data cache; and prior to eviction of said data from the data cache, maintaining metadata for said data in a metadata cache until the data written to the storage medium has been validated against the metadata.