Abstract: A method uses an integrated circuit having a debug status register. The integrated circuit is for being debugged by a hardware debugger external to the integrated circuit and has a processing unit for executing debug software. The debug status register is coupled to the processing unit and is for being coupled to the hardware debugger. The method includes updating the debug status register with hardware status flags arising from running the hardware debugger and software status flags arising from running the debug software. The method further includes masking locations in the debug status register where the hardware status flags are located from being read by the debug software while allowing the hardware status flags and the software status flags to be read by the hardware debugger. This is particularly useful in using the hardware debugger in debugging the debug software.

Abstract: A structural design-for-test for diagnosing broken scan chain defects of long non-scannable register chains (GPTR) The GPTR and the system for testing and diagnosing the broken LSSD scan-only chains rapidly localize defects to the failing Shift Register Latch (SRL) pair. The GPTR modifies the latches used in the GPTR scan chain to standard LSSD L1/L2 master-slave SRL type latch pairs; connects all the system ports of the L1 latches to the Shift Register Input (SRI) and clocked by the system C1-clk while the L1 scan port is clocked by the A-clk and L2 scan port is clocked only by the B-clk. The L1 latches are connected to at least one multiplexer having a first output connected to an input of each odd SRL, and a second output connected to an input port of each even SRL.

Abstract: System-accessible frequency measuring circuits and procedures permit on-chip testing of the oscillators and provide test results observable off chip via LSSD scan paths. This allows a rapid ensemble of ring oscillators in a standard ASIC test flow without the need for on chip analog test equipment (the test apparatus has effectively been created on device and can be digitally configured, operated and read). Frequency measuring logic that can 1) functionally operate to measure the frequency of the ring oscillators; 2) participate in traditional logical tests such as LSSD and LBIST to verify that the circuit is manufactured correctly and is likely to operate and 3) operate in a special ring-oscillator test mode, that allows the logic to operate on a tester very similarly to the way it does functionally. In this mode, the frequency measuring logic can be scanned to a specific state, started by pulsing a digital I/O, and the measured analog value can be scanned out sometime later after the test has completed.

Abstract: A method and system for instruction address parity comparison are provided. The method includes calculating an instruction address parity value for an instruction, and distributing the instruction address parity value to one or more functional units in processing circuitry. The method also includes receiving the distributed instruction address parity value from the one or more functional units, and calculating a completing instruction address (CIA) parity value associated with completing the instruction. The method further includes generating an error indicator in response to a mismatch between the received instruction address parity value and the CIA parity value.

Abstract: Systems and methods are provided for identifying memory leaks in a computer system. Testing software is inserted into one or more memory routines of a computer system to cause at least two successive tests of the memory routines during which the memory routines perform memory operations to allocate and de-allocate memory from a plurality of memory areas, such as pools or heaps. Information is captured that identifies at least a number of memory allocations and a number of memory de-allocations performed by the memory routines during the pendency of the tests. The captured information is compared to identify one or more candidate memory areas from the plurality of memory areas. A candidate memory areas is identified when the difference between the number of memory allocations and the number of memory de-allocations increases from one test to the next. Each candidate memory area is then evaluated further to identify any specific memory leaks within the memory area.

Abstract: This invention involves the use of the JTAG functional test patterns and exercisors to solve the problem of diagnosing broken scan chains in either a serial or a lateral broadside insertion manner across all latch system ports and to analyze the response data efficiently for the purpose of readily identifying switching and non-switching latches with the next to last non-switching latch being the point of the break within a defective scan chain(s). This comprehensive latch perturbation, in conjunction with iterative diagnostic algorithms is used to identify and to pinpoint the defective location in such a broken scan chain(s). This JTAG Functional test function and the JTAG test patterns ultimately derived therefrom, can take on different forms and origins, some external to a product and some internal to a product.

Abstract: A self-service terminal comprises a watchdog timer coupled to a clock; and a reset driver for resetting the watchdog timer. The reset driver is operable to monitor a count reached by the watchdog timer, and to instigate a diagnostic action, such as writing information to a system event log, in the event that the count reaches a first predefined number.

Abstract: Systems, methods, and media for outputting data based on anomaly detection are provided. In some embodiments, methods for outputting data based on anomaly detection include: receiving a known-good dataset; storing distinct n-grams from the known-good dataset to form a binary anomaly detection model; receiving known-good new n-grams; computing a rate of receipt of distinct n-grams in the new n-grams; determining whether further training of the anomaly detection model is necessary based on the rate of receipt on distinct n-grams; using the binary anomaly detection model to determine whether an input dataset contains an anomaly; and outputting the input dataset based on whether the input dataset contains an anomaly.

Abstract: An image data test unit includes a data acquisition unit configured to acquire image data having individual frames, an image data temporary storage unit configured to receive the acquired image data from the data acquisition unit to store a certain amount of the image data, and a test calculation unit configured to sequentially receive the image data from the image data temporary storage unit to store a certain amount of the image data, and compare the stored image data with pre-set test elements. In addition, an image apparatus having the image data test unit and a method of testing image data using the image data test unit are also provided.

Abstract: A system and method for verifying operation of a target system to be inspected. The system includes an abstract binary tree generation unit and a matching unit. The abstract binary tree generation unit obtains information about a functional specification of the target system and generates one or more binary trees that associate one or more states that can occur in the target system with respective nodes and that associate state transitions of objects constituting the target system and interactions between the objects with connection relationships between the nodes. The matching unit receives an event sequence in an application model of the target system obtained in response to the operation of the target system and matches the event sequence against the binary trees generated by the abstract binary tree generation unit. The method includes steps for accomplishing the functionality of the system.

Abstract: For some data processing systems, it is important to be able to handle overlapping debug events generated by a shared set of debug resources which are trying to cause both exception processing and debug mode entry. However, exception processing and debug mode entry generally have conflicting requirements. In one embodiment, exception priority processing is initially given to the software debug event. Normal state saving is performed and the first instruction of the debug exception handler is fetched, but not executed. Priority is then switched from the software debug event to the hardware debug event and a debug halted state is entered. Once processing of the hardware debug event has been completed, priority is returned to the software debug event and the debug exception handler is executed.

Abstract: A method and system for container identification are disclosed. The method comprises obtaining a plurality of digital images of a character sequence on the container, extracting the character sequences from the images, combining the character sequences into at least one identification code candidate, and selecting one of the candidates as the identification code. The system comprises at least one camera and a computer system that is electrically coupled to the camera, whereby when the computer system receives a trigger signal, said computer system takes a plurality of digital images from the camera, produces character sequences as partial recognition results for the plurality of digital images, and combines the partial recognition results together to produce the identification code.

Abstract: A method and apparatus for decoding encoded data bits of a wireless communication transmission are provided. A set of a-priori bit values corresponding to known bit values of the encoded data bits may be generated. Decoding paths that correspond to decoded data bits that are inconsistent with the a-priori bit values may be removed from the possible decoding paths to consider, and decoding the encoded data bits by selecting a decoding path from remaining decoding paths of the possible decoding paths that were not removed. A-priori bit values may be extracted from various messages, such as DL-MAP, UL-MAP, RNG-REQ, and BW-REQ messages.

Abstract: A scan chain cell 24 is provided with a built-in delay testing capability. An inverter 32 generates an inverted form of the cell output which is available within the scan chain cell 24 for rapid use in forming a transition at the cell output Q. Clock gating circuitry 36, 38 is responsive to a hold signal to block the functional path 34, 26, 28 through the scan chain cell and hold the output signal when desired. The functional clock clk may be clocked twice at speed to trigger capture of the results of processing the output of the scan chain cell 24 for the non-inverted value followed by the (internally generated) inverted value, i.e. a signal transition. In this way delay testing of the functional circuitry 18 can be performed.

Abstract: Methods for context sensitive detection of failing I/O devices sample and record a response time of an I/O device for each of a first plurality of time intervals to generate a first plurality of sampled and recorded response times, and to determine whether or not at least one I/O error has occurred in each of the first plurality of time intervals. A mathematical model is applied which characterizes the first plurality of sampled and recorded response times. The mathematical model is applied in accordance with an I/O device category corresponding to the I/O device. The mathematical model provides a frame of reference for defining an I/O failure.

Abstract: A system and method provide for test automation of a process running on separated systems. The systems may be separated physically and/or logically separated. The system and method provide that all information required for a test run are made available on one system. In an embodiment, a central component is used to provide all required status and result information regarding the test status of every system in the test landscape. In further embodiment, an extension of the capabilities of existing test tools is made so that the test tool communicates with the central component via an appropriate protocol.

Abstract: Various new and non-obvious apparatus and methods for testing embedded memories in an integrated circuit are disclosed. One of the disclosed embodiments is an apparatus for testing an embedded memory in an integrated circuit. This exemplary embodiment comprises input logic that includes one or more memory-input paths coupled to respective memory inputs of the embedded memory, a memory built-in self-test (MBIST) controller, and at least one scan cell coupled between the input logic and the MBIST controller. The scan cell of this embodiment is selectively operable in a memory-test mode and a system mode. In memory-test mode, the scan cell can apply memory-test data to the memory inputs along the memory-input paths of the integrated circuit. Any of the disclosed apparatus can be designed, simulated, and/or verified (and any of the disclosed methods can be performed) in a computer-executed application, such as an electronic-design-automation (“EDA”) software tool.

Abstract: The invention provides an error detection method for data transmission in a transmission system with a first device, a second device and a data line. The method comprises the following steps. Firstly, a clock signal is sent to synchronize the first and second devices. Secondly, at least one serial data is sent from the first device to the second device in response to the clock signal. After sending the serial data, the first device sends an acknowledgement signal to the second device. After sending the acknowledgement signal, the first device reads the data line to obtain a reading value and determines whether the serial data is correct according to the reading value and a default value of the data line.

Abstract: A device that includes a first memory unit adapted to store encrypted instructions, a processor adapted to execute decrypted instructions, a second memory unit accessible by the processor, and a decryption unit. The device is characterized by including a key database and a key selection circuit, wherein the key selection circuit is adapted to select a selected decryption key from the key database for decrypting encrypted instructions. The selection is responsive to a fixed selection information stored within the integrated circuit and to received key selection information. A method that includes a stage of receiving encrypted instructions; and executing decrypted instructions by a processor. The method is characterized by receiving key selection information, selecting a selected decryption key out of a key database in response to fixed selection information and to the received key selection information, and decrypting encrypted instructions using the selected decryption key.

Abstract: Systems, circuits and methods for adapting word line (WL) pulse widths used in memory systems are disclosed. One embodiment of the invention is directed to an apparatus comprising a memory system. The memory system comprises: a memory operating according to a wordline (WL) pulse with an associated WL pulse width; a built-in self-test (BIST) unit that interfaces with the memory, the BIST unit being configured to run a self-test of the internal functionality of the memory and provide a signal indicating if the memory passed or failed the self-test; and an adaptive WL control circuit that interfaces with the BIST unit and the memory, the adaptive WL control circuit being configured to adjust the WL pulse width of the memory based on the signal provided by the BIST unit.

Abstract: An electronic controlling device and method is disclosed. One embodiment provides at least one module performing specific functions within one of a plurality of module modes on reception of a corresponding module mode request. A system control unit is provided to operate the at least module in one of a plurality of module modes by distributing a corresponding system mode request. The at least one module is adapted to translate the distributed system mode request to a module mode request which is configurable.

Abstract: A system includes a plurality of devices that are connected in series and a controller that communicates with the devices. Each of the devices has a plurality of input ports and corresponding output ports. The outputs of one device and the inputs of a next device are interconnected. The controller is coupled to the first device and the last device of the series-connection. The controller applies a test pattern to the plurality of input ports at the first device connected in series, by the controller. Each data channel defines a data path between corresponding pairs of input and output ports of the first and last devices. A data channel is enabled if the test pattern is detected at its corresponding output port.

Abstract: Methods and systems are provided for an intervention-by-choice printhead maintenance method in an ink jet printing system. Profile representations of scheduled print jobs are compiled which are representative of ink jet performance demand therefor. An ink jet failure is detected and related to the profile representations. A likely impact of ink jet failure is assessed relative to job specific print quality requirements for the scheduled print jobs. Print jobs are rescheduled for enhancing system performance efficiency by re-queuing selected jobs that can be executed with a detected ink jet failure while satisfying a job specific print quality requirement before a system repair intervention.

Abstract: Two common varieties of test interfaces exist for ICs and/or cores, the IEEE 1149.1 Test Access Port (TAP) interface and internal scan test ports. The TAP serves as a serial communication port for accessing a variety of circuitry including; IEEE 1149.1 boundary scan circuitry, built in self test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation/debug circuitry, and IEEE P1532 in-system programming circuitry. Internal scan test ports serve as a serial communication port for primarily accessing internal scan circuitry within ICs and cores. Today, the TAP and internal scan test ports are typically viewed as being separate test interfaces, each utilizing different IC pins and/or core terminals.

Abstract: A system receives a program, allocates the program to a first software unit of execution (UE) and a second software UE, executes a first portion of the program with the first and second software UEs in parallel, and determines whether an error is detected during execution of the first portion of the program by the first and second software UEs. The system also sends a signal, between the first and second software UEs, to execute a second portion of the program when the error is detected in the first portion of the program, executes the second portion of the program with the first and second software UEs when the error is detected, and provides for display information associated with execution of the first portion and the second portion of the program by the first and second software UEs.

Abstract: A testing system for an embedded system is provided. The testing system includes a plurality of devices and one or more host computers. Each device, which includes the embedded system to be tested, is connected to the host computer via a network based on the network file system protocol. The host computers are further connected with a control server, and each of the host computers comprises a root file system. The control server is configured for providing an interface for a user to set test parameters, controlling each of the host computers to invoke a test program, thereby testing the embedded system according to the test parameters, and receiving test results of the embedded system from the host computer. A related testing method is also provided.

Abstract: A computer implemented method, apparatus, and computer usable program code for the distributed monitoring of a SOAP service is provided. A test configuration file specifying a test input is distributed from a central reporting location to at least one remote data processing system that has access to a SOAP service to be tested. The test configuration file is created without accessing the SOAP service to be tested. Furthermore, the user that created the test configuration file is not allowed access to the SOAP service to be tested.

Abstract: According to an aspect of an embodiment, a storage apparatus comprising; a pair of control devices for controlling storage devices, each control device being connected with another control device; storage devices for storing data; switches being connected with the plurality of storage devices, the switches being connected between the control devices in series; wherein the control device for controlling the plurality of switches according to a process comprising the steps of: detecting a fault in the connection of the switches, and; controlling the control devices to access the storage devices via the switches such that one of the control devices accesses a part of the storage devices via a part of the switches located between said one of the control devices and the fault, and the other of the control devices accesses remainder of the storage devices via remainder of the switches, respectively.

Abstract: The invention relates to a method and an apparatus for safe parameterization in accordance with IEC 61508 SIL 1 to 3 or EN 954-1 Categories 1 to 4 of safe electronic appliances. One object of the invention is to describe a way which overcomes the explicit reading back of the parameters from the safe electronic appliance and confirmation of each of these parameters by the user. For this purpose, the invention proposes that parameter values which are intended for parameterization, are selected or entered via a user interface of an electronic control device and are then transmitted to the electronic appliance, to be kept in at least one memory which can be accessed by the control device, and be read back at least once from the memory for verification of the safe parameterization.

Abstract: An eye violation and excess jitter trigger for a digital signal uses a mask within a unit interval of the digital signal, such as a rectangular mask having corners defined by a high threshold, a low threshold, an early clock and a late clock, the early and late clocks being derived from a reference clock. The reference clock may be a recovered clock derived from the digital signal or from high and low threshold comparator outputs, or may be an external clock. For the excess jitter trigger, which is a special case of the eye violation trigger, the high and low thresholds are essentially equal. A status of the digital signal with respect to the mask is determined using the high and low thresholds and the early and late clocks, and a violation signal is output when the status indicates that a portion of the digital signal crossed into the mask. The violation signal may then be used to trigger data acquisition or for other purposes.

Abstract: A system for simultaneously interfacing multiple test instruments with multiple processor cores includes an on-chip instrumentation, a probe, and a connection mechanism for providing a transmission path between the probe and the on-chip instrumentation. The on-chip instrumentation includes an on-chip instrumentation concentrator and an on-chip instrumentation de-concentrator. The probe includes a probe concentrator and a probe de-concentrator. The probe concentrator concentrates signals from the test instruments into a first serial signal stream for transmission over the connector mechanism. The on-chip instrumentation de-concentrator de-concentrates the first serial signal stream into signals to be directed to at least one of the processor cores. The on-chip instrumentation concentrator concentrates signals from the processor cores into a second serial signal stream for transmission over the connector mechanism.

Abstract: A configurable and reusable hardware-software NAND system adaptive to various NAND devices independent of the NAND device manufacturer and NAND device characteristics. A device identification signature is decoded from a NAND device in a NAND system; the device identification signature signal is analyzed to obtain a control phase sequence value descriptive of a characteristic of the NAND device; the control phase register is populated with the control phase sequence value; and control phase register provides the control phase sequence values to the command sequencer. The control phase register can be programmed by a low level driver for devices which NAND system cannot decode the device identification signature.

Abstract: To identify errored bits in a binary data set, an ordered plurality of modulo-2 summations of respective selections of the data-set bits are compared with a target syndrome. The selections of data-set bits are defined by the connection of sum nodes to variable nodes in a logical network of nodes and edges where each variable node is associated with a respective data-set bit and each sum node corresponds to a respective modulo-2 summation. Any sum node for which the corresponding summation of selected data-set bits is found to be inconsistent with the target syndrome is identified as errored. Predetermined patterns of errored sum nodes are then looked for to identify one or more associated errored data-set bits.

Abstract: A computer system for hosting computing clusters for clients. The system includes clusters each including a set of computing resources and each implemented in custom or differing configurations. Each of the configurations provides a customized computing environment for performing particular client tasks. The configurations may differ due to configuration of the processing nodes, the data storage, or the private cluster network or its connections. The system includes a monitoring system that monitors the clusters for operational problems on a cluster level and also on a per-node basis such as with monitors provided for each node. The system controls client access to the clusters via a public communications by only allowing clients to access their assigned cluster or the cluster configured per their specifications and performing their computing task. Gateway mechanisms isolate each cluster such that communications within a cluster or on a private cluster communications network are maintained separate.

Abstract: A computer is programmed to execute a diagnostic procedure either on a pre-set schedule or asynchronously in response to an event, such as an error message, or a user command. When executed, the diagnostic procedure automatically checks for integrity of one or more portions of data in the computer, to identify any failure(s). In some embodiments, the failure(s) may be displayed to a human, after revalidation to exclude any failure that no longer exists.

Abstract: An infrastructure is provided for gathering diagnostic data that is relevant to an error or other conditions detected in a monitored system. A diagnosability framework is provided that automates the gathering of relevant diagnostic data upon occurrence of the condition in the monitored system. In one embodiment, context data is determined for the condition detected in the monitored system. A rule-based engine is provided that is configured to automatically determine one or more actions to be performed for the condition detected in the monitored system based on the determined context data. The actions may include performing tasks that gather diagnostic data that is relevant to the detected condition, store the gathered diagnostic data in a repository, recommend one or more diagnostic actions to a user, and other diagnostic related actions.

Abstract: Techniques for proactively and reactively running diagnostic functions. These diagnostic functions help to improve diagnostics of conditions detected in a monitored system and to limit/quarantine the damages caused by the detected conditions. In one embodiment, a health monitor infrastructure is provided that is configured to perform one or more health checks in a monitored system for diagnosing and/or gathering information related to the system. The one or more health checks may be invoked pro-actively on a scheduled basis, reactively in response to a condition detected in the system, or may even be invoked manually by a user such as a system administrator.

Abstract: A system that diagnoses a failure in a computer system is described. During operation, the system tests the computer system using a sequence of tests, where a given test includes a given load associated with a pre-determined failure mechanism for a given failure condition. During the given test, the system obtains results, which include telemetry signals that are monitored within the computer system. If the results indicate the given failure condition, the system ceases the testing and indicates that the computer system has the given failure condition. Otherwise, the system continues the sequence of tests until the sequence is completed, at which point, if no fault has been detected, the system indicates that a no-trouble-found (NTF) condition exists.

Abstract: A system (such as a process control system or communication system) includes one or more sources of configuration data (such as one or more BootP or DHCP servers). A testing mechanism transmits one or more requests for configuration data over a network. One or more sources of configuration data may respond to the requests, such as by providing configuration data (like IP addresses or NTP parameters) to the testing mechanism. The testing mechanism uses the response(s) to identify problems with the sources of configuration data. For example, if responses are received from multiple sources of configuration data, the testing mechanism could generate a notification indicating that a problem exists when the responses contain inconsistent configuration data. Also, if no responses are received, the testing mechanism could generate a notification indicating that a problem exists since no configuration data has been received. Any other or additional problems could also be detected.

Abstract: A method and apparatus to provide identity management deployment interoperability and compliance verification. In one embodiment, the system also provides on-demand services including automated certification, monitoring, alerting, routing, and translation of tokens for federated identity related interactions between multi-domain identity management systems is provided.

Abstract: Internet connectivity evaluation provides for easy, efficient and effective testing of the Internet connectivity behavior between an operating system hosted on a computing device and an IGD (Internet Gateway Device) interacting with the computing device. With a user's computing device communicating with one or more servers, or server-type devices, interacting with, or otherwise communicating with, the Internet, Internet connectivity evaluation can quickly and cost-effectively be performed to identify known major issues in the interaction between the operating system hosted on the user's computing device and an IGD.

Abstract: An error-correction apparatus and method and a three-dimensional (3D) pointing device using the error-correction apparatus are provided. The error-correction apparatus includes a data-collection module which collects current data and calculates an actual variation in the current data; an estimation module which calculates an estimated data variation for the current data based on a number of data variations for respective corresponding previous data; a threshold-calculation module which calculates a variable threshold based on the data variations for the respective previous data; and a determination module which compares the difference between the actual data variation and the estimated data variation with the variable threshold and determines whether the current data is erroneous based on the result of the comparison.

Abstract: A method of pressure testing for peripheral component interconnect (PCI) bus stage that is used in the overall pressure testing of PCI bus. The method includes the steps of reviewing all the PCI buses in a system; obtaining a tree-shaped structure of the all the PCI buses and PCI devices of the entire system, and selecting from them a branch of PCI bus as an object of testing; performing peripheral component interconnect function test, input/output function test, and memory mapping function test of the PCI bus relative to this object of testing; and selecting a branch of PCI bus from among the remaining branches of PCI buses of the system as an object of testing to proceed with the related tests of PCI bus mentioned above, until all the branches of PCI buses to be tested have finished testing.

Abstract: A method establishes a global system model equation including model equations, which contain parameters, of individual components that form the global system. According to said method, the parameters of the individual components are detected using sensor values from the sensors that are allocated to the individual components and it is determined whether it is determined whether it is possible to adapt the parameters to the sensor values and to solve the global system model equation.

Abstract: The inventive subject matter herein is directed toward improved scheduling and planning system in which computer implemented software uses a hierarchical selection list to select at least one of a plurality of unconnected users and contact the selected user(s) as a function of an event. Another aspect of the inventive subject matter includes an improved decision and/or scheduling system that has soft fields for describing resources. Further aspects utilize a hierarchical soft field configuration.

Abstract: Provided are a method and apparatus for evaluating the effectiveness of a test case used for a program test on the basis of error detection capability. The method includes: receiving a target program used for evaluating the effectiveness of the test case; generating an error program by inputting errors to the target program; detecting the errors by executing the test case on the generated error program; and calculating evaluation points of the test case using a ratio of the number of the detected errors to the number of the input errors. Thus, the capability of the test case used for a program test to detect errors can be evaluated.

Abstract: A health check framework for enterprise systems is described herein. In one embodiment, a health check framework includes one or more first layer methods as public interfaces to allow an application client to initiate one or more stages of a health checking session, where the first layer methods are independent of a particular component of the enterprise system. The health check framework further includes one or more second layer methods to provide an abstract interface to the one or more system and/or application components with respect to the one or more first layer methods. The second layer methods include one or more methods that are specific to a corresponding one of the system and/or application components of the enterprise system. During a health check session, the first layer methods invoke the second layer methods to perform health check operations. Other methods and apparatuses are also described.

Abstract: A system and method corrects erroneous sections received in a memory by pre-filling at least a portion of memory with a pre-defined value. If a received data packet is valid, the valid received data packet is stored over the pre-defined values in the memory location associated with the valid data packet. Values associated with a data segment and an adjacent data segment in the memory are compared to the pre-defined value. When the values of each data segment match the pre-defined values, then each data segment is an erroneous data segment.

Abstract: Provided is a memory system and wear-leveling method. A memory system includes a flash memory device and a memory controller. The flash memory device includes a plurality of memory blocks, each including a plurality of memory cells. The memory controller is configured to control the flash memory device based on erase event information and error checking and correction (ECC) event information of each of the memory blocks such that use of the memory blocks is distributed more uniformly.

Abstract: An electronic system includes a counter and a first component. The first component includes a reset input configured to receive a reset event, an interface to a communications interface coupleable to a second component, an error detection module configured to initiate the counter in response to detecting an error in a first communication from the second component, and an event logging module. The event logging module is configured to store a first indicator representative of the counter value of the counter in response to receiving the reset event via the reset input and configured to store a second indicator representative of the error at the communications interface. The counter is initiated at the first component in response to detecting an error in a first communication from the second component. A counter value of the counter is determined in response to detecting a reset event at the first component subsequent to detecting the error in the first communication.